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radeon: fix tile_split of 128-bit surface formats with 8x MSAA
author
Marek Olšák
<maraeo@gmail.com>
Tue, 16 Oct 2012 00:08:02 +0000
(
02:08
+0200)
committer
Marek Olšák
<maraeo@gmail.com>
Fri, 26 Oct 2012 18:00:59 +0000
(20:00 +0200)
The calculation led to the number 8192, which is too high.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
radeon/radeon_surface.c
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diff --git
a/radeon/radeon_surface.c
b/radeon/radeon_surface.c
index
66c2444
..
eb587d2
100644
(file)
--- a/
radeon/radeon_surface.c
+++ b/
radeon/radeon_surface.c
@@
-939,6
+939,8
@@
static int eg_surface_best(struct radeon_surface_manager *surf_man,
} else {
/* tile split must be >= 256 for colorbuffer surfaces */
surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);
+ if (surf->tile_split > 4096)
+ surf->tile_split = 4096;
}
} else {
/* set tile split to row size */