u32 vconf = 0;
struct sd_emmc_config *pconf = (struct sd_emmc_config *)&vconf;
struct mmc_phase *init = &(host->data->sdmmc.init);
- struct mmc_phase *calc = &(host->data->sdmmc.calc);
writel(0, host->base + SD_EMMC_ADJUST_V3);
writel(0, host->base + SD_EMMC_DELAY1_V3);
pclkc->core_phase = init->core_phase; /* 2: 180 phase */
pclkc->rx_phase = init->rx_phase;
pclkc->tx_phase = init->tx_phase;
- if ((host->data->chip_type >= MMC_CHIP_G12A)
- && (host->data->chip_type != MMC_CHIP_TL1)) {
- pclkc->core_phase = calc->core_phase;
- pclkc->tx_phase = calc->tx_phase;
- }
pclkc->always_on = 1; /* Keep clock always on */
writel(vclkc, host->base + SD_EMMC_CLOCK_V3);
#ifdef SD_EMMC_CLK_CTRL
if (clk_ios == 0) {
- aml_mmc_clk_switch_off(host);
+ aml_mmc_clk_switch_off(pdata);
return ret;
}
/* (re)start clock, if non-zero */
if (clk_ios) {
- vclkc = readl(host->base + SD_EMMC_CLOCK_V3);
- pdata->clk_lay.source
- = clk_get_rate(host->cfg_div_clk) * clkc->div;
- pdata->clk_lay.core = clk_get_rate(host->cfg_div_clk);
+ if (pdata->calc_f) {
+ vclkc = readl(host->base + SD_EMMC_CLOCK_V3);
+ pdata->clk_lay.source
+ = clk_get_rate(host->cfg_div_clk) * clkc->div;
+ pdata->clk_lay.core = clk_get_rate(host->cfg_div_clk);
+ }
vcfg = readl(host->base + SD_EMMC_CFG);
conf->stop_clk = 0;
/* overide co-phase by dts */
if (pdata->co_phase)
clkc->core_phase = pdata->co_phase;
- if ((pdata->calc_f)
- && ((host->data->chip_type >= MMC_CHIP_G12A)
- && (host->data->chip_type != MMC_CHIP_TL1))) {
+ if (pdata->calc_f) {
clkc->core_phase = para->calc.core_phase;
clkc->tx_phase = para->calc.tx_phase;
}
} else if (timing == MMC_TIMING_SD_HS) {
if (aml_card_type_non_sdio(pdata))
clkc->core_phase = para->sd_hs.core_phase;
- if ((pdata->calc_f)
- && ((host->data->chip_type >= MMC_CHIP_G12A)
- && (host->data->chip_type != MMC_CHIP_TL1))) {
+ if (pdata->calc_f) {
clkc->core_phase = para->calc.core_phase;
clkc->tx_phase = para->calc.tx_phase;
}
}
}
- if ((pdata->calc_f)
- && ((host->data->chip_type >= MMC_CHIP_G12A)
- && (host->data->chip_type != MMC_CHIP_TL1))) {
+ if (pdata->calc_f) {
if (timing <= MMC_TIMING_SD_HS) {
ret = aml_fixdiv_calc(&fixdiv, &pdata->clk_lay);
if (!ret) {