drm/i915: Move MCHBAR registers to their own header

Registers that exist within the MCH BAR and are mirrored into the GPU's
MMIO space are a good candidate to separate out into their own header.

For reference, the mirror of the MCH BAR starts at the following
locations in the graphics MMIO space (the end of the MCHBAR range
differs slightly on each platform):

 * Pre-gen6:           0x10000
 * Gen6-Gen11 + RKL:  0x140000

v2:
 - Create separate patch to swtich a few register definitions to be
   relative to the MCHBAR mirror base.
 - Drop upper bound of MCHBAR mirror from commit message; there are too
   many different combinations between various platforms to list out,
   and the documentation is spotty for the older pre-gen6 platforms
   anyway.

Bspec: 134, 51771
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220215061342.2055952-2-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 23aa8e0..7bbe0dc 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -10,6 +10,7 @@
 #include "intel_bw.h"
 #include "intel_cdclk.h"
 #include "intel_display_types.h"
+#include "intel_mchbar_regs.h"
 #include "intel_pcode.h"
 #include "intel_pm.h"
 

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 118ef39..8888fda 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -32,6 +32,7 @@
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
+#include "intel_mchbar_regs.h"
 #include "intel_pci_config.h"
 #include "intel_pcode.h"
 #include "intel_psr.h"

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index d2102cc..9ebae7a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -16,6 +16,7 @@
 #include "intel_dpio_phy.h"
 #include "intel_dpll.h"
 #include "intel_hotplug.h"
+#include "intel_mchbar_regs.h"
 #include "intel_pch_refclk.h"
 #include "intel_pcode.h"
 #include "intel_pm.h"

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 4dfed34..0272b24 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -16,6 +16,7 @@
 #include "i915_gem_stolen.h"
 #include "i915_reg.h"
 #include "i915_vgpu.h"
+#include "intel_mchbar_regs.h"
 
 /*
  * The BIOS typically reserves some of the system's memory for the exclusive

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index 95c9145..f294753 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -9,6 +9,7 @@
 #include "i915_pvinfo.h"
 #include "i915_vgpu.h"
 #include "intel_gt_regs.h"
+#include "intel_mchbar_regs.h"
 
 /**
  * DOC: fence register handling

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 4e448c1..3776591 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -15,6 +15,7 @@
 #include "intel_gt_pm_debugfs.h"
 #include "intel_gt_regs.h"
 #include "intel_llc.h"
+#include "intel_mchbar_regs.h"
 #include "intel_pcode.h"
 #include "intel_rc6.h"
 #include "intel_rps.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 75a07e3..e8143fa 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1315,13 +1315,6 @@
 #define LCFUSE02                               _MMIO(0x116c0)
 #define   LCFUSE_HIV_MASK                      0x000000ff
 
-#define ILK_GDSR                               _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
-#define   ILK_GRDOM_FULL                       (0 << 1)
-#define   ILK_GRDOM_RENDER                     (1 << 1)
-#define   ILK_GRDOM_MEDIA                      (3 << 1)
-#define   ILK_GRDOM_MASK                       (3 << 1)
-#define   ILK_GRDOM_RESET_ENABLE               (1 << 0)
-
 #define GAC_ECO_BITS                           _MMIO(0x14090)
 #define   ECOBITS_SNB_BIT                      (1 << 13)
 #define   ECOBITS_PPGTT_CACHE64B               (3 << 8)

diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
index 335c657..40e2e28 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_llc.c
+++ b/drivers/gpu/drm/i915/gt/intel_llc.c
@@ -10,6 +10,7 @@
 #include "i915_reg.h"
 #include "intel_gt.h"
 #include "intel_llc.h"
+#include "intel_mchbar_regs.h"
 #include "intel_pcode.h"
 
 struct ia_constants {

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index b5dae82..ae7542f 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -23,6 +23,7 @@
 #include "intel_gt.h"
 #include "intel_gt_pm.h"
 #include "intel_gt_requests.h"
+#include "intel_mchbar_regs.h"
 #include "intel_pci_config.h"
 #include "intel_reset.h"
 

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 0cb299c..fd95449 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -13,6 +13,7 @@
 #include "intel_gt_irq.h"
 #include "intel_gt_pm_irq.h"
 #include "intel_gt_regs.h"
+#include "intel_mchbar_regs.h"
 #include "intel_pcode.h"
 #include "intel_rps.h"
 #include "vlv_sideband.h"

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 7334656..b3d28b0 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -8,6 +8,7 @@
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "intel_guc_slpc.h"
+#include "intel_mchbar_regs.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_regs.h"
 

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index c2ae790..5e3ae59 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -40,6 +40,7 @@
 #include "i915_reg.h"
 #include "gvt.h"
 #include "i915_pvinfo.h"
+#include "intel_mchbar_regs.h"
 #include "display/intel_display_types.h"
 #include "display/intel_fbc.h"
 #include "gt/intel_gt_regs.h"

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 764fbfd..54c66d4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -49,6 +49,7 @@
 #include "i915_debugfs_params.h"
 #include "i915_irq.h"
 #include "i915_scheduler.h"
+#include "intel_mchbar_regs.h"
 #include "intel_pm.h"
 
 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 69446e8..b23ff4a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1830,117 +1830,8 @@
                                            _PALETTE_B, _CHV_PALETTE_C) + \
                                      (i) * 4)
 
-/* MCH MMIO space */
-
-/*
- * MCHBAR mirror.
- *
- * This mirrors the MCHBAR MMIO space whose location is determined by
- * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
- * every way.  It is not accessible from the CP register read instructions.
- *
- * Starting from Haswell, you can't write registers using the MCHBAR mirror,
- * just read.
- */
-#define MCHBAR_MIRROR_BASE     0x10000
-
-#define MCHBAR_MIRROR_BASE_SNB 0x140000
-
-#define CTG_STOLEN_RESERVED            _MMIO(MCHBAR_MIRROR_BASE + 0x34)
-#define ELK_STOLEN_RESERVED            _MMIO(MCHBAR_MIRROR_BASE + 0x48)
-#define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
-#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
-#define G4X_STOLEN_RESERVED_ENABLE     (1 << 0)
-
-/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
-#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
-
-/* 915-945 and GM965 MCH register controlling DRAM channel access */
-#define DCC                    _MMIO(MCHBAR_MIRROR_BASE + 0x200)
-#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL             (0 << 0)
-#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC    (1 << 0)
-#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED   (2 << 0)
-#define DCC_ADDRESSING_MODE_MASK                       (3 << 0)
-#define DCC_CHANNEL_XOR_DISABLE                                (1 << 10)
-#define DCC_CHANNEL_XOR_BIT_17                         (1 << 9)
-#define DCC2                   _MMIO(MCHBAR_MIRROR_BASE + 0x204)
-#define DCC2_MODIFIED_ENHANCED_DISABLE                 (1 << 20)
-
-/* Pineview MCH register contains DDR3 setting */
-#define CSHRDDR3CTL            _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
-#define CSHRDDR3CTL_DDR3       (1 << 2)
-
-/* 965 MCH register controlling DRAM channel configuration */
-#define C0DRB3_BW              _MMIO(MCHBAR_MIRROR_BASE + 0x206)
-#define C1DRB3_BW              _MMIO(MCHBAR_MIRROR_BASE + 0x606)
-
-/* snb MCH registers for reading the DRAM channel configuration */
-#define MAD_DIMM_C0                    _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
-#define MAD_DIMM_C1                    _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
-#define MAD_DIMM_C2                    _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
-#define   MAD_DIMM_ECC_MASK            (0x3 << 24)
-#define   MAD_DIMM_ECC_OFF             (0x0 << 24)
-#define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
-#define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
-#define   MAD_DIMM_ECC_ON              (0x3 << 24)
-#define   MAD_DIMM_ENH_INTERLEAVE      (0x1 << 22)
-#define   MAD_DIMM_RANK_INTERLEAVE     (0x1 << 21)
-#define   MAD_DIMM_B_WIDTH_X16         (0x1 << 20) /* X8 chips if unset */
-#define   MAD_DIMM_A_WIDTH_X16         (0x1 << 19) /* X8 chips if unset */
-#define   MAD_DIMM_B_DUAL_RANK         (0x1 << 18)
-#define   MAD_DIMM_A_DUAL_RANK         (0x1 << 17)
-#define   MAD_DIMM_A_SELECT            (0x1 << 16)
-/* DIMM sizes are in multiples of 256mb. */
-#define   MAD_DIMM_B_SIZE_SHIFT                8
-#define   MAD_DIMM_B_SIZE_MASK         (0xff << MAD_DIMM_B_SIZE_SHIFT)
-#define   MAD_DIMM_A_SIZE_SHIFT                0
-#define   MAD_DIMM_A_SIZE_MASK         (0xff << MAD_DIMM_A_SIZE_SHIFT)
-
-/* snb MCH registers for priority tuning */
-#define MCH_SSKPD                      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
-#define   MCH_SSKPD_WM0_MASK           0x3f
-#define   MCH_SSKPD_WM0_VAL            0xc
-
-/* Clocking configuration register */
-#define CLKCFG                 _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
-#define CLKCFG_FSB_400                                 (0 << 0)        /* hrawclk 100 */
-#define CLKCFG_FSB_400_ALT                             (5 << 0)        /* hrawclk 100 */
-#define CLKCFG_FSB_533                                 (1 << 0)        /* hrawclk 133 */
-#define CLKCFG_FSB_667                                 (3 << 0)        /* hrawclk 166 */
-#define CLKCFG_FSB_800                                 (2 << 0)        /* hrawclk 200 */
-#define CLKCFG_FSB_1067                                        (6 << 0)        /* hrawclk 266 */
-#define CLKCFG_FSB_1067_ALT                            (0 << 0)        /* hrawclk 266 */
-#define CLKCFG_FSB_1333                                        (7 << 0)        /* hrawclk 333 */
-#define CLKCFG_FSB_1333_ALT                            (4 << 0)        /* hrawclk 333 */
-#define CLKCFG_FSB_1600_ALT                            (6 << 0)        /* hrawclk 400 */
-#define CLKCFG_FSB_MASK                                        (7 << 0)
-#define CLKCFG_MEM_533                                 (1 << 4)
-#define CLKCFG_MEM_667                                 (2 << 4)
-#define CLKCFG_MEM_800                                 (3 << 4)
-#define CLKCFG_MEM_MASK                                        (7 << 4)
-
-#define HPLLVCO                 _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
-#define HPLLVCO_MOBILE          _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
-
-#define TSC1                   _MMIO(MCHBAR_MIRROR_BASE + 0x1001)
-#define   TSE                  (1 << 0)
-#define TR1                    _MMIO(MCHBAR_MIRROR_BASE + 0x1006)
-#define TSFS                   _MMIO(MCHBAR_MIRROR_BASE + 0x1020)
-#define   TSFS_SLOPE_MASK      0x0000ff00
-#define   TSFS_SLOPE_SHIFT     8
-#define   TSFS_INTR_MASK       0x000000ff
-
-#define CSIPLL0                        _MMIO(MCHBAR_MIRROR_BASE + 0x2c10)
-#define DDRMPLL1               _MMIO(MCHBAR_MIRROR_BASE + 0x2c20)
 #define PEG_BAND_GAP_DATA      _MMIO(0x14d68)
 
-#define GEN6_GT_PERF_STATUS    _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
-#define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
-#define GEN6_RP_STATE_LIMITS   _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
-#define GEN6_RP_STATE_CAP      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
-#define   RP0_CAP_MASK         REG_GENMASK(7, 0)
-#define   RP1_CAP_MASK         REG_GENMASK(15, 8)
-#define   RPN_CAP_MASK         REG_GENMASK(23, 16)
 #define BXT_RP_STATE_CAP        _MMIO(0x138170)
 #define GEN9_RP_STATE_LIMITS   _MMIO(0x138148)
 #define XEHPSDV_RP_STATE_CAP   _MMIO(0x250014)
@@ -4319,14 +4210,6 @@
        (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
         ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
 
-/* Memory latency timer register */
-#define MLTR_ILK               _MMIO(MCHBAR_MIRROR_BASE + 0x1222)
-#define  MLTR_WM1_SHIFT                0
-#define  MLTR_WM2_SHIFT                8
-/* the unit of memory self-refresh latency time is 0.5us */
-#define  ILK_SRLT_MASK         0x3f
-
-
 /* the address where we get all kinds of latency value */
 #define SSKPD                  _MMIO(0x5d10)
 #define SSKPD_WM_MASK          0x3f
@@ -8216,93 +8099,7 @@ enum skl_power_gate {
 #define  DC_STATE_DEBUG_MASK_CORES     (1 << 0)
 #define  DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
 
-#define BXT_D_CR_DRP0_DUNIT8                   0x1000
-#define BXT_D_CR_DRP0_DUNIT9                   0x1200
-#define  BXT_D_CR_DRP0_DUNIT_START             8
-#define  BXT_D_CR_DRP0_DUNIT_END               11
-#define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \
-                                     _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
-                                                BXT_D_CR_DRP0_DUNIT9))
-#define  BXT_DRAM_RANK_MASK                    0x3
-#define  BXT_DRAM_RANK_SINGLE                  0x1
-#define  BXT_DRAM_RANK_DUAL                    0x3
-#define  BXT_DRAM_WIDTH_MASK                   (0x3 << 4)
-#define  BXT_DRAM_WIDTH_SHIFT                  4
-#define  BXT_DRAM_WIDTH_X8                     (0x0 << 4)
-#define  BXT_DRAM_WIDTH_X16                    (0x1 << 4)
-#define  BXT_DRAM_WIDTH_X32                    (0x2 << 4)
-#define  BXT_DRAM_WIDTH_X64                    (0x3 << 4)
-#define  BXT_DRAM_SIZE_MASK                    (0x7 << 6)
-#define  BXT_DRAM_SIZE_SHIFT                   6
-#define  BXT_DRAM_SIZE_4GBIT                   (0x0 << 6)
-#define  BXT_DRAM_SIZE_6GBIT                   (0x1 << 6)
-#define  BXT_DRAM_SIZE_8GBIT                   (0x2 << 6)
-#define  BXT_DRAM_SIZE_12GBIT                  (0x3 << 6)
-#define  BXT_DRAM_SIZE_16GBIT                  (0x4 << 6)
-#define  BXT_DRAM_TYPE_MASK                    (0x7 << 22)
-#define  BXT_DRAM_TYPE_SHIFT                   22
-#define  BXT_DRAM_TYPE_DDR3                    (0x0 << 22)
-#define  BXT_DRAM_TYPE_LPDDR3                  (0x1 << 22)
-#define  BXT_DRAM_TYPE_LPDDR4                  (0x2 << 22)
-#define  BXT_DRAM_TYPE_DDR4                    (0x4 << 22)
-
-#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
-#define  DG1_GEAR_TYPE                         REG_BIT(16)
-
-#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
-#define  SKL_DRAM_DDR_TYPE_MASK                        (0x3 << 0)
-#define  SKL_DRAM_DDR_TYPE_DDR4                        (0 << 0)
-#define  SKL_DRAM_DDR_TYPE_DDR3                        (1 << 0)
-#define  SKL_DRAM_DDR_TYPE_LPDDR3              (2 << 0)
-#define  SKL_DRAM_DDR_TYPE_LPDDR4              (3 << 0)
-
-#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN   _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
-#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN   _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
-#define  SKL_DRAM_S_SHIFT                      16
-#define  SKL_DRAM_SIZE_MASK                    0x3F
-#define  SKL_DRAM_WIDTH_MASK                   (0x3 << 8)
-#define  SKL_DRAM_WIDTH_SHIFT                  8
-#define  SKL_DRAM_WIDTH_X8                     (0x0 << 8)
-#define  SKL_DRAM_WIDTH_X16                    (0x1 << 8)
-#define  SKL_DRAM_WIDTH_X32                    (0x2 << 8)
-#define  SKL_DRAM_RANK_MASK                    (0x1 << 10)
-#define  SKL_DRAM_RANK_SHIFT                   10
-#define  SKL_DRAM_RANK_1                       (0x0 << 10)
-#define  SKL_DRAM_RANK_2                       (0x1 << 10)
-#define  SKL_DRAM_RANK_MASK                    (0x1 << 10)
-#define  ICL_DRAM_SIZE_MASK                    0x7F
-#define  ICL_DRAM_WIDTH_MASK                   (0x3 << 7)
-#define  ICL_DRAM_WIDTH_SHIFT                  7
-#define  ICL_DRAM_WIDTH_X8                     (0x0 << 7)
-#define  ICL_DRAM_WIDTH_X16                    (0x1 << 7)
-#define  ICL_DRAM_WIDTH_X32                    (0x2 << 7)
-#define  ICL_DRAM_RANK_MASK                    (0x3 << 9)
-#define  ICL_DRAM_RANK_SHIFT                   9
-#define  ICL_DRAM_RANK_1                       (0x0 << 9)
-#define  ICL_DRAM_RANK_2                       (0x1 << 9)
-#define  ICL_DRAM_RANK_3                       (0x2 << 9)
-#define  ICL_DRAM_RANK_4                       (0x3 << 9)
-
-#define SA_PERF_STATUS_0_0_0_MCHBAR_PC         _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
-#define  DG1_QCLK_RATIO_MASK                   REG_GENMASK(9, 2)
-#define  DG1_QCLK_REFERENCE                    REG_BIT(10)
-
-#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
-#define   DG1_DRAM_T_RDPRE_MASK                        REG_GENMASK(16, 11)
-#define   DG1_DRAM_T_RP_MASK                   REG_GENMASK(6, 0)
-#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
-#define   DG1_DRAM_T_RCD_MASK                  REG_GENMASK(15, 9)
-#define   DG1_DRAM_T_RAS_MASK                  REG_GENMASK(8, 1)
-
-/*
- * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
- * since on HSW we can't write to it using intel_uncore_write.
- */
-#define D_COMP_HSW                     _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
 #define D_COMP_BDW                     _MMIO(0x138144)
-#define  D_COMP_RCOMP_IN_PROGRESS      (1 << 9)
-#define  D_COMP_COMP_FORCE             (1 << 8)
-#define  D_COMP_COMP_DISABLE           (1 << 0)
 
 /* Pipe WM_LINETIME - watermark line time */
 #define _WM_LINETIME_A         0x45270

diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 723bd04..174c95c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -6,6 +6,7 @@
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "intel_dram.h"
+#include "intel_mchbar_regs.h"
 #include "intel_pcode.h"
 
 struct dram_dimm_info {

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9f5e3c3..d4d487f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -50,6 +50,7 @@
 #include "i915_drv.h"
 #include "i915_fixed.h"
 #include "i915_irq.h"
+#include "intel_mchbar_regs.h"
 #include "intel_pcode.h"
 #include "intel_pm.h"
 #include "vlv_sideband.h"