obj-y += reset_manager_s10.o
obj-y += system_manager_soc64.o
obj-y += timer_s10.o
-obj-y += wrap_pinmux_config_s10.o
+obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
obj-y += system_manager_soc64.o
obj-y += timer_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
-obj-y += wrap_pinmux_config_s10.o
+obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
* Offset for HW handoff from Quartus tools
*/
/* HPS handoff */
+#define SOC64_HANDOFF_MAGIC_BOOT 0x424F4F54
#define SOC64_HANDOFF_MAGIC_MUX 0x504D5558
#define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354
#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741
#define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0)
#define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580)
-#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608)
#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C)
#else
#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600)
#endif
+#define SOC64_HANDOFF_MUX_LEN 96
+#define SOC64_HANDOFF_IOCTL_LEN 96
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#define SOC64_HANDOFF_FPGA_LEN 42
+#else
+#define SOC64_HANDOFF_FPGA_LEN 40
+#endif
+#define SOC64_HANDOFF_DELAY_LEN 96
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+enum endianness {
+ LITTLE_ENDIAN = 0,
+ BIG_ENDIAN
+};
+
+int socfpga_get_handoff_size(void *handoff_address, enum endianness endian);
+int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len,
+ enum endianness big_endian);
+#endif
#endif /* _HANDOFF_SOC64_H_ */
void sysmgr_pinmux_init(void);
void populate_sysmgr_fpgaintf_module(void);
void populate_sysmgr_pinmux(void);
-void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
#define SYSMGR_SOC64_WDDBG 0x08
#define SYSMGR_SOC64_DMA 0x20
*
*/
-#include <common.h>
+#include <asm/arch/handoff_soc64.h>
+#include <asm/arch/system_manager.h>
#include <asm/global_data.h>
#include <asm/io.h>
-#include <asm/arch/system_manager.h>
+#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
*/
void populate_sysmgr_pinmux(void)
{
- const u32 *sys_mgr_table_u32;
- unsigned int len, i;
+ u32 len, i;
+ u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX, BIG_ENDIAN);
+ u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL, BIG_ENDIAN);
+ u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA, BIG_ENDIAN);
+ u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY, BIG_ENDIAN);
+
+ len = (len_mux > len_ioctl) ? len_mux : len_ioctl;
+ len = (len > len_fpga) ? len : len_fpga;
+ len = (len > len_delay) ? len : len_delay;
+
+ u32 handoff_table[len];
/* setup the pin sel */
- sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len);
+ len = (len_mux < SOC64_HANDOFF_MUX_LEN) ? len_mux : SOC64_HANDOFF_MUX_LEN;
+ socfpga_handoff_read((void *)SOC64_HANDOFF_MUX, handoff_table, len, BIG_ENDIAN);
for (i = 0; i < len; i = i + 2) {
- writel(sys_mgr_table_u32[i + 1],
- sys_mgr_table_u32[i] +
- (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_PINSEL0);
+ writel(handoff_table[i + 1],
+ handoff_table[i] +
+ (u8 *)socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_PINSEL0);
}
/* setup the pin ctrl */
- sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len);
+ len = (len_ioctl < SOC64_HANDOFF_IOCTL_LEN) ? len_ioctl : SOC64_HANDOFF_IOCTL_LEN;
+ socfpga_handoff_read((void *)SOC64_HANDOFF_IOCTL, handoff_table, len, BIG_ENDIAN);
for (i = 0; i < len; i = i + 2) {
- writel(sys_mgr_table_u32[i + 1],
- sys_mgr_table_u32[i] +
- (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_IOCTRL0);
+ writel(handoff_table[i + 1],
+ handoff_table[i] +
+ (u8 *)socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_IOCTRL0);
}
/* setup the fpga use */
- sysmgr_pinmux_table_fpga(&sys_mgr_table_u32, &len);
+ len = (len_fpga < SOC64_HANDOFF_FPGA_LEN) ? len_fpga : SOC64_HANDOFF_FPGA_LEN;
+ socfpga_handoff_read((void *)SOC64_HANDOFF_FPGA, handoff_table, len, BIG_ENDIAN);
for (i = 0; i < len; i = i + 2) {
- writel(sys_mgr_table_u32[i + 1],
- sys_mgr_table_u32[i] +
+ writel(handoff_table[i + 1],
+ handoff_table[i] +
(u8 *)socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_EMAC0_USEFPGA);
}
/* setup the IO delay */
- sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len);
+ len = (len_delay < SOC64_HANDOFF_DELAY_LEN) ? len_delay : SOC64_HANDOFF_DELAY_LEN;
+ socfpga_handoff_read((void *)SOC64_HANDOFF_DELAY, handoff_table, len, BIG_ENDIAN);
for (i = 0; i < len; i = i + 2) {
- writel(sys_mgr_table_u32[i + 1],
- sys_mgr_table_u32[i] +
- (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_IODELAY0);
+ writel(handoff_table[i + 1],
+ handoff_table[i] +
+ (u8 *)socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_IODELAY0);
}
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <asm/arch/handoff_soc64.h>
+#include <asm/io.h>
+#include <common.h>
+#include <errno.h>
+#include "log.h"
+
+int socfpga_get_handoff_size(void *handoff_address, enum endianness endian)
+{
+ u32 size;
+
+ size = readl(handoff_address + SOC64_HANDOFF_OFFSET_LENGTH);
+ if (endian == BIG_ENDIAN)
+ size = swab32(size);
+
+ size = (size - SOC64_HANDOFF_OFFSET_DATA) / sizeof(u32);
+
+ debug("%s: handoff address = 0x%p handoff size = 0x%08x\n", __func__,
+ (u32 *)handoff_address, size);
+
+ return size;
+}
+
+int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len,
+ enum endianness big_endian)
+{
+ u32 temp, i;
+ u32 *table_x32 = table;
+
+ debug("%s: handoff addr = 0x%p ", __func__, (u32 *)handoff_address);
+
+ if (big_endian) {
+ if (swab32(readl(SOC64_HANDOFF_BASE)) == SOC64_HANDOFF_MAGIC_BOOT) {
+ debug("Handoff table address = 0x%p ", table_x32);
+ debug("table length = 0x%x\n", table_len);
+ debug("%s: handoff data =\n{\n", __func__);
+
+ for (i = 0; i < table_len; i++) {
+ temp = readl(handoff_address +
+ SOC64_HANDOFF_OFFSET_DATA +
+ (i * sizeof(u32)));
+ *table_x32 = swab32(temp);
+
+ if (!(i % 2))
+ debug(" No.%d Addr 0x%08x: ", i,
+ *table_x32);
+ else
+ debug(" 0x%08x\n", *table_x32);
+
+ table_x32++;
+ }
+ debug("\n}\n");
+ } else {
+ debug("%s: Cannot find SOC64_HANDOFF_MAGIC_BOOT ", __func__);
+ debug("at addr 0x%p\n", (u32 *)handoff_address);
+ return -EPERM;
+ }
+ }
+
+ return 0;
+}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
- *
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/handoff_soc64.h>
-
-static void sysmgr_pinmux_handoff_read(void *handoff_address,
- const u32 **table,
- unsigned int *table_len)
-{
- unsigned int handoff_entry = (swab32(readl(handoff_address +
- SOC64_HANDOFF_OFFSET_LENGTH)) -
- SOC64_HANDOFF_OFFSET_DATA) /
- sizeof(unsigned int);
- unsigned int handoff_chunk[handoff_entry], temp, i;
-
- if (swab32(readl(SOC64_HANDOFF_MUX)) == SOC64_HANDOFF_MAGIC_MUX) {
- /* using handoff from Quartus tools if exists */
- for (i = 0; i < handoff_entry; i++) {
- temp = readl(handoff_address +
- SOC64_HANDOFF_OFFSET_DATA + (i * 4));
- handoff_chunk[i] = swab32(temp);
- }
- *table = handoff_chunk;
- *table_len = ARRAY_SIZE(handoff_chunk);
- }
-}
-
-void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len)
-{
- sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_MUX, table,
- table_len);
-}
-
-void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len)
-{
- sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_IOCTL, table,
- table_len);
-}
-
-void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len)
-{
- sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_FPGA, table,
- table_len);
-}
-
-void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len)
-{
- sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_DELAY, table,
- table_len);
-}
projects / platform / kernel / u-boot.git / commitdiff