W_VCBUS_BIT(AFBCE_MODE, 1, 30, 1);
W_VCBUS_BIT(AFBCE_MODE, 0, 30, 1);
}
+
+void vdin_afbce_mode_init(struct vdin_dev_s *devp)
+{
+ /* afbce_valid means can switch into afbce mode */
+ devp->afbce_valid = 0;
+ if (devp->afbce_flag & VDIN_AFBCE_EN) {
+ if ((devp->h_active > 1920) && (devp->v_active > 1080)) {
+ if (devp->afbce_flag & VDIN_AFBCE_EN_4K)
+ devp->afbce_valid = 1;
+ } else if ((devp->h_active > 1280) && (devp->v_active > 720)) {
+ if (devp->afbce_flag & VDIN_AFBCE_EN_1080P)
+ devp->afbce_valid = 1;
+ } else if ((devp->h_active > 720) && (devp->v_active > 576)) {
+ if (devp->afbce_flag & VDIN_AFBCE_EN_720P)
+ devp->afbce_valid = 1;
+ } else {
+ if (devp->afbce_flag & VDIN_AFBCE_EN_SMALL)
+ devp->afbce_valid = 1;
+ }
+
+ /* if is hdr mode, not enable afbc mode*/
+ if (devp->prop.hdr_info.hdr_state == HDR_STATE_GET) {
+ if ((devp->prop.hdr_info.hdr_data.eotf ==
+ EOTF_HDR) ||
+ (devp->prop.hdr_info.hdr_data.eotf ==
+ EOTF_SMPTE_ST_2048) ||
+ (devp->prop.hdr_info.hdr_data.eotf ==
+ EOTF_HLG))
+ devp->afbce_valid = false;
+ }
+
+ if (devp->prop.hdr10p_info.hdr10p_on)
+ devp->afbce_valid = false;
+ }
+
+ /* default non-afbce mode
+ * switch to afbce_mode if need by vpp notify
+ */
+ devp->afbce_mode = 0;
+ devp->afbce_mode_pre = devp->afbce_mode;
+ pr_info("vdin%d init afbce_mode: %d\n", devp->index, devp->afbce_mode);
+}
+
+void vdin_afbce_mode_update(struct vdin_dev_s *devp)
+{
+ /* vdin mif/afbce mode update */
+ if (devp->afbce_mode) {
+ vdin_write_mif_or_afbce(devp, VDIN_OUTPUT_TO_AFBCE);
+ vdin_afbce_hw_enable_rdma(devp);
+ } else {
+ vdin_afbce_hw_disable_rdma(devp);
+ vdin_write_mif_or_afbce(devp, VDIN_OUTPUT_TO_MIF);
+ }
+
+ if (vdin_dbg_en) {
+ pr_info("vdin.%d: change afbce_mode %d->%d\n",
+ devp->index, devp->afbce_mode_pre, devp->afbce_mode);
+ }
+ devp->afbce_mode_pre = devp->afbce_mode;
+}
+
extern void vdin_afbce_hw_disable_rdma(struct vdin_dev_s *devp);
extern void vdin_afbce_hw_enable_rdma(struct vdin_dev_s *devp);
extern void vdin_afbce_soft_reset(void);
+extern void vdin_afbce_mode_init(struct vdin_dev_s *devp);
+extern void vdin_afbce_mode_update(struct vdin_dev_s *devp);
#endif
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_YUV422) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_GBR_YUV422) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_BRG_YUV422)) &&
- (devp->color_depth_mode == 1))
+ (devp->color_depth_mode == VDIN_422_FULL_PK_EN))
devp->canvas_w = (max_buf_width * 5)/2;
else if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
- (devp->color_depth_mode == 0))
+ (devp->color_depth_mode == VDIN_422_FULL_PK_DIS))
devp->canvas_w = max_buf_width *
VDIN_YUV422_10BIT_PER_PIXEL_BYTE;
else
devp->canvas_active_w = devp->canvas_w;
if (devp->force_yuv444_malloc == 1) {
if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
- (devp->color_depth_mode != 1))
+ (devp->color_depth_mode != VDIN_422_FULL_PK_EN))
devp->canvas_w = devp->h_active *
VDIN_YUV444_10BIT_PER_PIXEL_BYTE;
else
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_YUV422) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_GBR_YUV422) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_BRG_YUV422)) &&
- (devp->color_depth_mode == 1))
+ (devp->color_depth_mode == VDIN_422_FULL_PK_EN))
devp->canvas_w = (devp->h_active * 5)/2;
else if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
- (devp->color_depth_mode == 0))
+ (devp->color_depth_mode == VDIN_422_FULL_PK_DIS))
devp->canvas_w = devp->h_active *
VDIN_YUV422_10BIT_PER_PIXEL_BYTE;
else
/*backup before roundup*/
devp->canvas_active_w = devp->canvas_w;
if (devp->force_yuv444_malloc == 1) {
- if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
- (devp->color_depth_mode != 1))
+ if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) /*&&*/
+ /*(devp->color_depth_mode != VDIN_422_FULL_PK_EN)*/)
devp->canvas_w = devp->h_active *
VDIN_YUV444_10BIT_PER_PIXEL_BYTE;
else
(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_GBR) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_BRG) ||
(devp->force_yuv444_malloc == 1)) {
- if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
- (devp->color_depth_mode != 1)) {
+ if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH)/* &&*/
+ /*(devp->color_depth_mode != VDIN_422_FULL_PK_EN)*/) {
h_size = roundup(h_size *
VDIN_YUV444_10BIT_PER_PIXEL_BYTE,
devp->canvas_align);
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_YUV422) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_GBR_YUV422) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_BRG_YUV422)) &&
- (devp->color_depth_mode == 1)) {
+ (devp->color_depth_mode == VDIN_422_FULL_PK_EN)) {
h_size = roundup((h_size * 5)/2, devp->canvas_align);
devp->canvas_alin_w = (h_size * 2) / 5;
} else if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
- (devp->color_depth_mode == 0)) {
+ (devp->color_depth_mode == VDIN_422_FULL_PK_DIS)) {
h_size = roundup(h_size *
VDIN_YUV422_10BIT_PER_PIXEL_BYTE,
devp->canvas_align);
wr_bits(offset, VDIN_MATRIX_CTRL, 1,
VDIN_MATRIX1_EN_BIT, VDIN_MATRIX1_EN_WID);
}
+ pr_info("%s id:%d\n", __func__, matrix_csc);
}
static inline void vdin_set_color_matrix0(unsigned int offset,
wr_bits(offset, VDIN_MATRIX_CTRL, 1,
VDIN_MATRIX_EN_BIT, VDIN_MATRIX_EN_WID);
}
+ pr_info("%s id:%d\n", __func__, matrix_csc);
}
static void vdin_set_color_matrix0_g12a(unsigned int offset,
struct tvin_format_s *tvin_fmt_p,
wr_bits(offset, VDIN_MATRIX_CTRL, 1,
VDIN_MATRIX_EN_BIT, VDIN_MATRIX_EN_WID);
}
+ pr_info("%s id:%d\n", __func__, matrix_csc);
}
/*set matrix based on rgb_info_enable:
struct vframe_s *vf) {
if (devp->prop.hdr10p_info.hdr10p_on) {
- devp->prop.hdr10p_info.hdr10p_on = false;
+ /*devp->prop.hdr10p_info.hdr10p_on = false;*/
vf->signal_type |= (1 << 29);/*present_flag*/
vf->signal_type |= (0 << 25);/*0:limited*/
struct tvin_state_machine_ops_s *sm_ops;
enum tvin_port_e port = TVIN_PORT_NULL;
struct tvin_sig_property_s *prop;
+ /*enum tvin_color_fmt_e color_format;*/
if (!devp)
return;
EOTF_SMPTE_ST_2048) ||
(devp->prop.hdr_info.hdr_data.eotf ==
EOTF_HLG)) {
+ #if 0
+ /*4k 444, afbc mode not support 10bit mode*/
+ color_format = devp->prop.color_format;
+ if (!(((color_format == TVIN_RGB444) ||
+ (color_format == TVIN_YUV444) ||
+ (color_format == TVIN_BGGR) ||
+ (color_format == TVIN_RGGB) ||
+ (color_format == TVIN_GBRG) ||
+ (color_format == TVIN_GRBG)) &&
+ ((devp->h_active > 1920) &&
+ (devp->v_active > 1080)) &&
+ devp->afbce_valid)) {
+ devp->color_depth_config =
+ COLOR_DEEPS_10BIT;
+ pr_info("vdin is hdr mode,force 10bit\n");
+ }
+ #else
+ devp->color_depth_config =
+ COLOR_DEEPS_10BIT;
pr_info("vdin is hdr mode,force 10bit\n");
- devp->color_depth_config = COLOR_DEEPS_10BIT;
+ #endif
}
}
- devp->prop.hdr_info.hdr_data.eotf = 0;
+ /*devp->prop.hdr_info.hdr_data.eotf = 0;*/
}
}
pr_info("frontend_fps:%d\n", devp->prop.fps);
pr_info("frontend_colordepth:%d\n", devp->prop.colordepth);
pr_info("source_bitdepth:%d\n", devp->source_bitdepth);
- pr_info("color_depth_config:%d\n", devp->color_depth_config);
+ pr_info("color_depth_config:0x%x\n", devp->color_depth_config);
pr_info("color_depth_mode:%d\n", devp->color_depth_mode);
pr_info("color_depth_support:0x%x\n", devp->color_depth_support);
pr_info("cma_flag:0x%x\n", devp->cma_config_flag);
seq_printf(seq, "frontend_fps:%d\n", devp->prop.fps);
seq_printf(seq, "frontend_colordepth:%d\n", devp->prop.colordepth);
seq_printf(seq, "source_bitdepth:%d\n", devp->source_bitdepth);
- seq_printf(seq, "color_depth_config:%d\n", devp->color_depth_config);
+ seq_printf(seq, "color_depth_config:0x%x\n", devp->color_depth_config);
seq_printf(seq, "color_depth_mode:%d\n", devp->color_depth_mode);
seq_printf(seq, "color_depth_support:0x%x\n",
devp->color_depth_support);
pr_err("miss parameters .\n");
else if (kstrtoul(parm[1], 10, &val) == 0) {
devp->color_depth_config = val | COLOR_DEEPS_MANUAL;
- pr_info("color_depth(%d):%d\n\n", devp->index,
+ pr_info("color_depth(%d):0x%x\n\n", devp->index,
devp->color_depth_config);
}
} else if (!strcmp(parm[0], "color_depth_support")) {
static struct rdma_op_s vdin_rdma_op[VDIN_MAX_DEVS];
#endif
-static void vdin_afbce_mode_init(struct vdin_dev_s *devp)
-{
- /* afbce_valid means can switch into afbce mode */
- devp->afbce_valid = 0;
- if (devp->afbce_flag & VDIN_AFBCE_EN) {
- if ((devp->h_active > 1920) && (devp->v_active > 1080)) {
- if (devp->afbce_flag & VDIN_AFBCE_EN_4K)
- devp->afbce_valid = 1;
- } else if ((devp->h_active > 1280) && (devp->v_active > 720)) {
- if (devp->afbce_flag & VDIN_AFBCE_EN_1080P)
- devp->afbce_valid = 1;
- } else if ((devp->h_active > 720) && (devp->v_active > 576)) {
- if (devp->afbce_flag & VDIN_AFBCE_EN_720P)
- devp->afbce_valid = 1;
- } else {
- if (devp->afbce_flag & VDIN_AFBCE_EN_SMALL)
- devp->afbce_valid = 1;
- }
- }
-
- /* default non-afbce mode
- * switch to afbce_mode if need by vpp notify
- */
- devp->afbce_mode = 0;
- devp->afbce_mode_pre = devp->afbce_mode;
- pr_info("vdin%d init afbce_mode: %d\n", devp->index, devp->afbce_mode);
-}
-
/*
* 1. config canvas base on canvas_config_mode
* 0: canvas_config in driver probe
return false;
}
-static void vdin_afbce_mode_update(struct vdin_dev_s *devp)
-{
- /* vdin mif/afbce mode update */
- if (devp->afbce_mode) {
- vdin_write_mif_or_afbce(devp, VDIN_OUTPUT_TO_AFBCE);
- vdin_afbce_hw_enable_rdma(devp);
- } else {
- vdin_afbce_hw_disable_rdma(devp);
- vdin_write_mif_or_afbce(devp, VDIN_OUTPUT_TO_MIF);
- }
-
- if (vdin_dbg_en) {
- pr_info("vdin.%d: change afbce_mode %d->%d\n",
- devp->index, devp->afbce_mode_pre, devp->afbce_mode);
- }
- devp->afbce_mode_pre = devp->afbce_mode;
-}
-
/*
*VDIN_FLAG_RDMA_ENABLE=1
* provider_vf_put(devp->last_wr_vfe, devp->vfp);
vdevp->output_color_depth = 10;
if (vdevp->color_depth_support&VDIN_WR_COLOR_DEPTH_10BIT_FULL_PCAK_MODE)
- vdevp->color_depth_mode = 1;
+ vdevp->color_depth_mode = VDIN_422_FULL_PK_EN;
else
- vdevp->color_depth_mode = 0;
+ vdevp->color_depth_mode = VDIN_422_FULL_PK_DIS;
/*set afbce config*/
vdevp->afbce_flag = 0;
/* Ref.2019/04/25: tl1 vdin0 afbce dynamically switch support,
* vpp also should support this function
*/
-#define VDIN_VER "Ref.2019/07/23: pretect dec top/start"
+#define VDIN_VER "Ref.2019/07/30:444 10bit mode buffer size not right"
/*the counter of vdin*/
#define VDIN_MAX_DEVS 2
/*TXL new add*/
#define VDIN_WR_COLOR_DEPTH_10BIT_FULL_PCAK_MODE (1 << 4)
+
+#define VDIN_422_FULL_PK_EN 1
+#define VDIN_422_FULL_PK_DIS 0
+
/* vdin afbce flag */
#define VDIN_AFBCE_EN (1 << 0)
#define VDIN_AFBCE_EN_LOOSY (1 << 1)