aml_append(scope, aml_name_decl("_S5", pkg));
aml_append(dsdt, scope);
+ /* create fw_cfg node, unconditionally */
+ {
+ /* when using port i/o, the 8-bit data register *always* overlaps
+ * with half of the 16-bit control register. Hence, the total size
+ * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
+ * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
+ uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
+ "dma_enabled", NULL) ?
+ ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
+ FW_CFG_CTL_SIZE;
+
+ scope = aml_scope("\\_SB.PCI0");
+ dev = aml_device("FWCF");
+
+ aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
+
+ /* device present, functioning, decoding, not shown in UI */
+ aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
+
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
+ );
+ aml_append(dev, aml_name_decl("_CRS", crs));
+
+ aml_append(scope, dev);
+ aml_append(dsdt, scope);
+ }
+
if (misc->applesmc_io_base) {
scope = aml_scope("\\_SB.PCI0.ISA");
dev = aml_device("SMC");