Revert "mid_pmu: fixing mismatch between ITP and OS PM_SSC configuration"

BZ: 10727

This reverts commit bc7b53aa1dcf178e7f2f5909a2f9e99746b8410a
This reverts patch 27756

Change-Id: Ie4198ab92f820db03e291e09d25fb6f00ac0f1c5
Reviewed-on: http://android.intel.com:8080/30576
Reviewed-by: Chotard, Celine <celine.chotard@intel.com>
Tested-by: Chotard, Celine <celine.chotard@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>

diff --git a/arch/x86/platform/mfld/pmu.c b/arch/x86/platform/mfld/pmu.c
index 303f5d7..45fde47 100755 (executable)
--- a/arch/x86/platform/mfld/pmu.c
+++ b/arch/x86/platform/mfld/pmu.c
@@ -2276,15 +2276,14 @@ static void update_all_lss_states(struct pmu_ss_states *pmu_config)
           table for certain firmwares. This is the case for HSI firmwares,
           SPI3 device is not advertised, and would then prevent s0i3. */
        /* Also take IGNORE_CFG in account (for e.g. GPIO1)*/
-       pmu_config->pmu2_states[0] |= S0IX_TARGET_SSS0 & ~PCIALLDEV_CFG[0];
+       pmu_config->pmu2_states[0] |= S0IX_TARGET_SSS0_MASK & ~PCIALLDEV_CFG[0];
        pmu_config->pmu2_states[0] &= ~IGNORE_SSS0;
-       pmu_config->pmu2_states[1] |= S0IX_TARGET_SSS1 & ~PCIALLDEV_CFG[1];
+       pmu_config->pmu2_states[1] |= S0IX_TARGET_SSS1_MASK & ~PCIALLDEV_CFG[1];
        pmu_config->pmu2_states[1] &= ~IGNORE_SSS1;
-       pmu_config->pmu2_states[2] |= S0IX_TARGET_SSS2 & ~PCIALLDEV_CFG[2];
+       pmu_config->pmu2_states[2] |= S0IX_TARGET_SSS2_MASK & ~PCIALLDEV_CFG[2];
        pmu_config->pmu2_states[2] &= ~IGNORE_SSS2;
-       pmu_config->pmu2_states[3] |= S0IX_TARGET_SSS3 & ~PCIALLDEV_CFG[3];
+       pmu_config->pmu2_states[3] |= S0IX_TARGET_SSS3_MASK & ~PCIALLDEV_CFG[3];
        pmu_config->pmu2_states[3] &= ~IGNORE_SSS3;
-
 }
 
 static pci_power_t _pmu_choose_state(int device_lss)
@@ -2295,7 +2294,9 @@ static pci_power_t _pmu_choose_state(int device_lss)
        case PMU_SECURITY_LSS_04:
                state = PCI_D2;
                break;
+
        case PMU_USB_OTG_LSS_06:
+       case PMU_USB_HSIC_LSS_07:
        case PMU_UART2_LSS_41:
                state = PCI_D1;
                break;

diff --git a/arch/x86/platform/mfld/pmu.h b/arch/x86/platform/mfld/pmu.h
index b8f8140..16de9df 100644 (file)
--- a/arch/x86/platform/mfld/pmu.h
+++ b/arch/x86/platform/mfld/pmu.h
@@ -271,7 +271,6 @@
        SSMSK(D0I3_MASK, PMU_I2C4_LSS_34-32) | \
        SSMSK(D0I3_MASK, PMU_I2C5_LSS_35-32) | \
        SSMSK(D0I3_MASK, PMU_SPI3_LSS_36-32) | \
-       SSMSK(D0I3_MASK, PMU_KEYBRD_LSS_40-32) | \
        SSMSK(D0I3_MASK, PMU_UART2_LSS_41-32))
 
 #define S0IX_TARGET_SSS3_MASK ( \
@@ -301,7 +300,6 @@
        SSMSK(D0I3_MASK, PMU_I2C4_LSS_34-32) | \
        SSMSK(D0I3_MASK, PMU_I2C5_LSS_35-32) | \
        SSMSK(D0I3_MASK, PMU_SPI3_LSS_36-32) | \
-       SSMSK(D0I1_MASK, PMU_KEYBRD_LSS_40-32) | \
        SSMSK(D0I1_MASK, PMU_UART2_LSS_41-32))
 
 #define S0IX_TARGET_SSS3 ( \
@@ -330,7 +328,6 @@
        SSMSK(D0I3_MASK, PMU_I2C4_LSS_34-32) | \
        SSMSK(D0I3_MASK, PMU_I2C5_LSS_35-32) | \
        SSMSK(D0I3_MASK, PMU_SPI3_LSS_36-32) | \
-       SSMSK(D0I3_MASK, PMU_KEYBRD_LSS_40-32) | \
        SSMSK(D0I3_MASK, PMU_UART2_LSS_41-32))
 
 #define LPMP3_TARGET_SSS3_MASK ( \
@@ -359,7 +356,6 @@
        SSMSK(D0I3_MASK, PMU_I2C4_LSS_34-32) | \
        SSMSK(D0I3_MASK, PMU_I2C5_LSS_35-32) | \
        SSMSK(D0I3_MASK, PMU_SPI3_LSS_36-32) | \
-       SSMSK(D0I1_MASK, PMU_KEYBRD_LSS_40-32) | \
        SSMSK(D0I1_MASK, PMU_UART2_LSS_41-32))
 
 #define LPMP3_TARGET_SSS3 ( \
@@ -420,6 +416,7 @@
        SSMSK(D0I2_MASK, PMU_SECURITY_LSS_04) | \
        SSMSK(D0I3_MASK, PMU_EMMC1_LSS_05) | \
        SSMSK(D0I1_MASK, PMU_USB_OTG_LSS_06) | \
+       SSMSK(D0I1_MASK, PMU_USB_HSIC_LSS_07) | \
        SSMSK(D0I3_MASK, PMU_AUDIO_ENGINE_LSS_08) | \
        SSMSK(D0I3_MASK, PMU_AUDIO_DMA_LSS_09) | \
        SSMSK(D0I3_MASK, PMU_SRAM_LSS_12) | \
@@ -442,7 +439,7 @@
        SSMSK(D0I3_MASK, PMU_SPI3_LSS_36-32) | \
        SSMSK(D0I3_MASK, PMU_GPIO1_LSS_37-32) | \
        SSMSK(D0I3_MASK, PMU_PWR_BUTTON_LSS_38-32) | \
-       SSMSK(D0I1_MASK, PMU_KEYBRD_LSS_40-32) | \
+       SSMSK(D0I3_MASK, PMU_KEYBRD_LSS_40-32) | \
        SSMSK(D0I1_MASK, PMU_UART2_LSS_41-32))
 
 #define S0I3_SSS3 ( \
@@ -465,6 +462,7 @@
        SSMSK(D0I2_MASK, PMU_SECURITY_LSS_04) | \
        SSMSK(D0I3_MASK, PMU_EMMC1_LSS_05) | \
        SSMSK(D0I1_MASK, PMU_USB_OTG_LSS_06) | \
+       SSMSK(D0I1_MASK, PMU_USB_HSIC_LSS_07) | \
        SSMSK(D0I3_MASK, PMU_SDIO2_LSS_14))
 
 #define LPMP3_SSS1 ( \
@@ -482,7 +480,7 @@
        SSMSK(D0I3_MASK, PMU_SPI3_LSS_36-32) | \
        SSMSK(D0I3_MASK, PMU_GPIO1_LSS_37-32) | \
        SSMSK(D0I3_MASK, PMU_PWR_BUTTON_LSS_38-32) | \
-       SSMSK(D0I1_MASK, PMU_KEYBRD_LSS_40-32) | \
+       SSMSK(D0I3_MASK, PMU_KEYBRD_LSS_40-32) | \
        SSMSK(D0I1_MASK, PMU_UART2_LSS_41-32))
 
 #define LPMP3_SSS3 ( \