(engine__) && (engine__)->uabi_class == (class__); \
(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
- #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
+ #define INTEL_INFO(i915) (&(i915)->__info)
+#define DISPLAY_INFO(i915) (INTEL_INFO(i915)->display)
- #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
+ #define RUNTIME_INFO(i915) (&(i915)->__runtime)
+#define DISPLAY_RUNTIME_INFO(i915) (&(i915)->__display_runtime)
- #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
+ #define DRIVER_CAPS(i915) (&(i915)->caps)
- #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
+ #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id)
#define IP_VER(ver, rel) ((ver) << 8 | (rel))
* The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
* All later gens can run the final buffer from the ppgtt
*/
- #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
+ #define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
- #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
- #define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
- #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
- #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
- #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
- #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv)
+ #define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
+ #define HAS_4TILE(i915) (INTEL_INFO(i915)->has_4tile)
+ #define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
+ #define HAS_EDRAM(i915) ((i915)->edram_size_mb)
+ #define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
+ #define HAS_WT(i915) HAS_EDRAM(i915)
- #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
+ #define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical)
- #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
- (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
- #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
- (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
+ #define HAS_LOGICAL_RING_CONTEXTS(i915) \
+ (INTEL_INFO(i915)->has_logical_ring_contexts)
+ #define HAS_LOGICAL_RING_ELSQ(i915) \
+ (INTEL_INFO(i915)->has_logical_ring_elsq)
- #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
+ #define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915)
- #define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
- #define HAS_PPGTT(dev_priv) \
- (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
- #define HAS_FULL_PPGTT(dev_priv) \
- (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
+ #define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)
+ #define HAS_PPGTT(i915) \
+ (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE)
+ #define HAS_FULL_PPGTT(i915) \
+ (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL)
- #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
+ #define HAS_PAGE_SIZES(i915, sizes) ({ \
GEM_BUG_ON((sizes) == 0); \
- ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
+ ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
})
-#define HAS_OVERLAY(i915) (INTEL_INFO(i915)->display.has_overlay)
-#define OVERLAY_NEEDS_PHYSICAL(i915) \
- (INTEL_INFO(i915)->display.overlay_needs_physical)
-
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
- #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
+ #define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915))
- #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
- (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
+ #define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \
+ (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)
/* WaRsDisableCoarsePowerGating:skl,cnl */
- #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
- (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
+ #define NEEDS_WaRsDisableCoarsePowerGating(i915) \
+ (IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
-#define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4)
-#define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 11 || \
- IS_GEMINILAKE(i915) || \
- IS_KABYLAKE(i915))
-
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming.
*/
- #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
- !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
+ #define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
+ !(IS_I915G(i915) || IS_I915GM(i915)))
-#define SUPPORTS_TV(i915) (INTEL_INFO(i915)->display.supports_tv)
-#define I915_HAS_HOTPLUG(i915) (INTEL_INFO(i915)->display.has_hotplug)
-
-#define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2)
-#define HAS_FBC(i915) (RUNTIME_INFO(i915)->fbc_mask != 0)
-#define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
-
-#define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13)
-
-#define HAS_IPS(i915) (IS_HSW_ULT(i915) || IS_BROADWELL(i915))
-
-#define HAS_DP_MST(i915) (INTEL_INFO(i915)->display.has_dp_mst)
-#define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
-
-#define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
-
-#define HAS_CDCLK_CRAWL(i915) (INTEL_INFO(i915)->display.has_cdclk_crawl)
-#define HAS_CDCLK_SQUASH(i915) (INTEL_INFO(i915)->display.has_cdclk_squash)
-#define HAS_DDI(i915) (INTEL_INFO(i915)->display.has_ddi)
-#define HAS_FPGA_DBG_UNCLAIMED(i915) (INTEL_INFO(i915)->display.has_fpga_dbg)
-#define HAS_PSR(i915) (INTEL_INFO(i915)->display.has_psr)
-#define HAS_PSR_HW_TRACKING(i915) \
- (INTEL_INFO(i915)->display.has_psr_hw_tracking)
-#define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12)
-#define HAS_TRANSCODER(i915, trans) ((RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
+ #define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
+ #define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
+ #define HAS_RC6pp(i915) (false) /* HW was never validated */
- #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
- #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
- #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
+ #define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
- #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
-#define HAS_DMC(i915) (RUNTIME_INFO(i915)->has_dmc)
-#define HAS_DSB(i915) (INTEL_INFO(i915)->display.has_dsb)
-#define HAS_DSC(__i915) (RUNTIME_INFO(__i915)->has_dsc)
-#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
-
+ #define HAS_HECI_PXP(i915) \
+ (INTEL_INFO(i915)->has_heci_pxp)
- #define HAS_HECI_PXP(dev_priv) \
- (INTEL_INFO(dev_priv)->has_heci_pxp)
+ #define HAS_HECI_GSCFI(i915) \
+ (INTEL_INFO(i915)->has_heci_gscfi)
- #define HAS_HECI_GSCFI(dev_priv) \
- (INTEL_INFO(dev_priv)->has_heci_gscfi)
+ #define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))
- #define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
-#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
-
+ #define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
+ #define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
- #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
- #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
-
- #define HAS_OA_BPC_REPORTING(dev_priv) \
- (INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
- #define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
- (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
- #define HAS_OAM(dev_priv) \
- (INTEL_INFO(dev_priv)->has_oam)
+ #define HAS_OA_BPC_REPORTING(i915) \
+ (INTEL_INFO(i915)->has_oa_bpc_reporting)
+ #define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \
+ (INTEL_INFO(i915)->has_oa_slice_contrib_limits)
+ #define HAS_OAM(i915) \
+ (INTEL_INFO(i915)->has_oam)
/*
* Set this flag, when platform requires 64K GTT page sizes or larger for
* device local memory access.
*/
- #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
+ #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
-#define HAS_IPC(i915) (INTEL_INFO(i915)->display.has_ipc)
-#define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
-
#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
* Platform has the dedicated compression control state for each lmem surfaces
* stored in lmem to support the 3D and media compression formats.
*/
- #define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs)
+ #define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs)
- #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
+ #define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc)
- #define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu)
+ #define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu)
- #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
+ #define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
-#define HAS_GMCH(i915) (INTEL_INFO(i915)->display.has_gmch)
-
#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
-#define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
-
#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
/* DPF == dynamic parity feature */
- #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
- #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
- 2 : HAS_L3_DPF(dev_priv))
+ #define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
+ #define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \
+ 2 : HAS_L3_DPF(i915))
-#define INTEL_NUM_PIPES(i915) (hweight8(RUNTIME_INFO(i915)->pipe_mask))
-
-#define HAS_DISPLAY(i915) (RUNTIME_INFO(i915)->pipe_mask != 0)
-
-#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
-
-#define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
-
/* Only valid when HAS_DISPLAY() is true */
- #define INTEL_DISPLAY_ENABLED(dev_priv) \
- (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), \
- !(dev_priv)->params.disable_display && \
- !intel_opregion_headless_sku(dev_priv))
+ #define INTEL_DISPLAY_ENABLED(i915) \
+ (drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)), \
+ !(i915)->params.disable_display && \
+ !intel_opregion_headless_sku(i915))
- #define HAS_GUC_DEPRIVILEGE(dev_priv) \
- (INTEL_INFO(dev_priv)->has_guc_deprivilege)
+ #define HAS_GUC_DEPRIVILEGE(i915) \
+ (INTEL_INFO(i915)->has_guc_deprivilege)
-#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || \
- IS_ALDERLAKE_S(i915))
-
-#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
-
#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
gen11_gt_irq_handler(gt, master_ctl);
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
- if (master_ctl & GEN11_DISPLAY_IRQ)
- gen11_display_irq_handler(i915);
-
- gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
-
- gen11_master_intr_enable(regs);
-
- gen11_gu_misc_irq_handler(i915, gu_misc_iir);
-
- pmu_irq_stats(i915, IRQ_HANDLED);
-
- return IRQ_HANDLED;
-}
-
-static inline u32 dg1_master_intr_disable(void __iomem * const regs)
-{
- u32 val;
-
- /* First disable interrupts */
- raw_reg_write(regs, DG1_MSTR_TILE_INTR, 0);
-
- /* Get the indication levels and ack the master unit */
- val = raw_reg_read(regs, DG1_MSTR_TILE_INTR);
- if (unlikely(!val))
- return 0;
-
- raw_reg_write(regs, DG1_MSTR_TILE_INTR, val);
-
- return val;
-}
-
-static inline void dg1_master_intr_enable(void __iomem * const regs)
-{
- raw_reg_write(regs, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
-}
-
-static irqreturn_t dg1_irq_handler(int irq, void *arg)
-{
- struct drm_i915_private * const i915 = arg;
- struct intel_gt *gt = to_gt(i915);
- void __iomem * const regs = gt->uncore->regs;
- u32 master_tile_ctl, master_ctl;
- u32 gu_misc_iir;
-
- if (!intel_irqs_enabled(i915))
- return IRQ_NONE;
-
- master_tile_ctl = dg1_master_intr_disable(regs);
- if (!master_tile_ctl) {
- dg1_master_intr_enable(regs);
- return IRQ_NONE;
- }
-
- /* FIXME: we only support tile 0 for now. */
- if (master_tile_ctl & DG1_MSTR_TILE(0)) {
- master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
- raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl);
- } else {
- drm_err(&i915->drm, "Tile not supported: 0x%08x\n",
- master_tile_ctl);
- dg1_master_intr_enable(regs);
- return IRQ_NONE;
- }
-
- gen11_gt_irq_handler(gt, master_ctl);
-
- if (master_ctl & GEN11_DISPLAY_IRQ)
- gen11_display_irq_handler(i915);
-
- gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
-
- dg1_master_intr_enable(regs);
-
- gen11_gu_misc_irq_handler(i915, gu_misc_iir);
-
- pmu_irq_stats(i915, IRQ_HANDLED);
-
- return IRQ_HANDLED;
-}
-
-/* Called from drm generic code, passed 'crtc' which
- * we use as a pipe index
- */
-int i8xx_enable_vblank(struct drm_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- enum pipe pipe = to_intel_crtc(crtc)->pipe;
- unsigned long irqflags;
-
- spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
- spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
-
- return 0;
-}
-
-int i915gm_enable_vblank(struct drm_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-
- /*
- * Vblank interrupts fail to wake the device up from C2+.
- * Disabling render clock gating during C-states avoids
- * the problem. There is a small power cost so we do this
- * only when vblank interrupts are actually enabled.
- */
- if (dev_priv->vblank_enabled++ == 0)
- intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
-
- return i8xx_enable_vblank(crtc);
-}
-
-int i965_enable_vblank(struct drm_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- enum pipe pipe = to_intel_crtc(crtc)->pipe;
- unsigned long irqflags;
-
- spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- i915_enable_pipestat(dev_priv, pipe,
- PIPE_START_VBLANK_INTERRUPT_STATUS);
- spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
-
- return 0;
-}
-
-int ilk_enable_vblank(struct drm_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- enum pipe pipe = to_intel_crtc(crtc)->pipe;
- unsigned long irqflags;
- u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
- DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
-
- spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- ilk_enable_display_irq(dev_priv, bit);
- spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
-
- /* Even though there is no DMC, frame counter can get stuck when
- * PSR is active as no frames are generated.
- */
- if (HAS_PSR(dev_priv))
- drm_crtc_vblank_restore(crtc);
-
- return 0;
-}
-
-static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc,
- bool enable)
-{
- struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
- enum port port;
-
- if (!(intel_crtc->mode_flags &
- (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0)))
- return false;
-
- /* for dual link cases we consider TE from slave */
- if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
- port = PORT_B;
- else
- port = PORT_A;
-
- intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_MASK_REG(port), DSI_TE_EVENT,
- enable ? 0 : DSI_TE_EVENT);
-
- intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), 0, 0);
-
- return true;
-}
-
-int bdw_enable_vblank(struct drm_crtc *_crtc)
-{
- struct intel_crtc *crtc = to_intel_crtc(_crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
- unsigned long irqflags;
-
- if (gen11_dsi_configure_te(crtc, true))
- return 0;
-
- spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
- spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
-
- /* Even if there is no DMC, frame counter can get stuck when
- * PSR is active as no frames are generated, so check only for PSR.
- */
- if (HAS_PSR(dev_priv))
- drm_crtc_vblank_restore(&crtc->base);
-
- return 0;
-}
-
-/* Called from drm generic code, passed 'crtc' which
- * we use as a pipe index
- */
-void i8xx_disable_vblank(struct drm_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- enum pipe pipe = to_intel_crtc(crtc)->pipe;
- unsigned long irqflags;
-
- spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
- spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
-}
-
-void i915gm_disable_vblank(struct drm_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-
- i8xx_disable_vblank(crtc);
-
- if (--dev_priv->vblank_enabled == 0)
- intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
-}
-
-void i965_disable_vblank(struct drm_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- enum pipe pipe = to_intel_crtc(crtc)->pipe;
- unsigned long irqflags;
-
- spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- i915_disable_pipestat(dev_priv, pipe,
- PIPE_START_VBLANK_INTERRUPT_STATUS);
- spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
-}
-
-void ilk_disable_vblank(struct drm_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- enum pipe pipe = to_intel_crtc(crtc)->pipe;
- unsigned long irqflags;
- u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
- DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
-
- spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- ilk_disable_display_irq(dev_priv, bit);
- spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
-}
-
-void bdw_disable_vblank(struct drm_crtc *_crtc)
-{
- struct intel_crtc *crtc = to_intel_crtc(_crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
- unsigned long irqflags;
-
- if (gen11_dsi_configure_te(crtc, false))
- return;
-
- spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
- spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
-}
-
-static void ibx_irq_reset(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
-
- if (HAS_PCH_NOP(dev_priv))
- return;
-
- GEN3_IRQ_RESET(uncore, SDE);
-
- if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
- intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff);
-}
-
-static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
-
- if (IS_CHERRYVIEW(dev_priv))
- intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
- else
- intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_VLV);
-
- i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
- intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT, 0, 0);
-
- i9xx_pipestat_irq_reset(dev_priv);
-
- GEN3_IRQ_RESET(uncore, VLV_);
- dev_priv->irq_mask = ~0u;
-}
-
-static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
-
- u32 pipestat_mask;
- u32 enable_mask;
- enum pipe pipe;
-
- pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
-
- i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
- for_each_pipe(dev_priv, pipe)
- i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
-
- enable_mask = I915_DISPLAY_PORT_INTERRUPT |
- I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
- I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
- I915_LPE_PIPE_A_INTERRUPT |
- I915_LPE_PIPE_B_INTERRUPT;
-
- if (IS_CHERRYVIEW(dev_priv))
- enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
- I915_LPE_PIPE_C_INTERRUPT;
-
- drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);
-
- dev_priv->irq_mask = ~enable_mask;
-
- GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
-}
-
-/* drm_dma.h hooks
-*/
-static void ilk_irq_reset(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
-
- GEN3_IRQ_RESET(uncore, DE);
- dev_priv->irq_mask = ~0u;
-
- if (GRAPHICS_VER(dev_priv) == 7)
- intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
-
- if (IS_HASWELL(dev_priv)) {
- intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
- intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
- }
-
- gen5_gt_irq_reset(to_gt(dev_priv));
-
- ibx_irq_reset(dev_priv);
-}
-
-static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
-{
- intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
- intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
-
- gen5_gt_irq_reset(to_gt(dev_priv));
-
- spin_lock_irq(&dev_priv->irq_lock);
- if (dev_priv->display_irqs_enabled)
- vlv_display_irq_reset(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
-}
-
-static void gen8_display_irq_reset(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
- enum pipe pipe;
-
- if (!HAS_DISPLAY(dev_priv))
- return;
-
- intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
- intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
-
- for_each_pipe(dev_priv, pipe)
- if (intel_display_power_is_enabled(dev_priv,
- POWER_DOMAIN_PIPE(pipe)))
- GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
-
- GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
- GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
-}
-
-static void gen8_irq_reset(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
-
- gen8_master_intr_disable(uncore->regs);
-
- gen8_gt_irq_reset(to_gt(dev_priv));
- gen8_display_irq_reset(dev_priv);
- GEN3_IRQ_RESET(uncore, GEN8_PCU_);
-
- if (HAS_PCH_SPLIT(dev_priv))
- ibx_irq_reset(dev_priv);
-
-}
-
-static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
- enum pipe pipe;
- u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
-
- if (!HAS_DISPLAY(dev_priv))
- return;
-
- intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
-
- if (DISPLAY_VER(dev_priv) >= 12) {
- enum transcoder trans;
-
- for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
- enum intel_display_power_domain domain;
-
- domain = POWER_DOMAIN_TRANSCODER(trans);
- if (!intel_display_power_is_enabled(dev_priv, domain))
- continue;
-
- intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
- intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
- }
- } else {
- intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
- intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
- }
-
- for_each_pipe(dev_priv, pipe)
- if (intel_display_power_is_enabled(dev_priv,
- POWER_DOMAIN_PIPE(pipe)))
- GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
-
- GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
- GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
- GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
-
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- GEN3_IRQ_RESET(uncore, SDE);
-}
-
-static void gen11_irq_reset(struct drm_i915_private *dev_priv)
-{
- struct intel_gt *gt = to_gt(dev_priv);
- struct intel_uncore *uncore = gt->uncore;
-
- gen11_master_intr_disable(dev_priv->uncore.regs);
-
- gen11_gt_irq_reset(gt);
- gen11_display_irq_reset(dev_priv);
-
- GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
- GEN3_IRQ_RESET(uncore, GEN8_PCU_);
-}
-
-static void dg1_irq_reset(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
- struct intel_gt *gt;
- unsigned int i;
-
- dg1_master_intr_disable(dev_priv->uncore.regs);
-
- for_each_gt(gt, dev_priv, i)
- gen11_gt_irq_reset(gt);
-
- gen11_display_irq_reset(dev_priv);
-
- GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
- GEN3_IRQ_RESET(uncore, GEN8_PCU_);
-}
-
-void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
- u8 pipe_mask)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
- u32 extra_ier = GEN8_PIPE_VBLANK |
- gen8_de_pipe_underrun_mask(dev_priv) |
- gen8_de_pipe_flip_done_mask(dev_priv);
- enum pipe pipe;
-
- spin_lock_irq(&dev_priv->irq_lock);
-
- if (!intel_irqs_enabled(dev_priv)) {
- spin_unlock_irq(&dev_priv->irq_lock);
- return;
- }
-
- for_each_pipe_masked(dev_priv, pipe, pipe_mask)
- GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
- dev_priv->de_irq_mask[pipe],
- ~dev_priv->de_irq_mask[pipe] | extra_ier);
-
- spin_unlock_irq(&dev_priv->irq_lock);
-}
-
-void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
- u8 pipe_mask)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
- enum pipe pipe;
-
- spin_lock_irq(&dev_priv->irq_lock);
-
- if (!intel_irqs_enabled(dev_priv)) {
- spin_unlock_irq(&dev_priv->irq_lock);
- return;
- }
-
- for_each_pipe_masked(dev_priv, pipe, pipe_mask)
- GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
-
- spin_unlock_irq(&dev_priv->irq_lock);
-
- /* make sure we're done processing display irqs */
- intel_synchronize_irq(dev_priv);
-}
-
-static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
-
- intel_uncore_write(uncore, GEN8_MASTER_IRQ, 0);
- intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
-
- gen8_gt_irq_reset(to_gt(dev_priv));
-
- GEN3_IRQ_RESET(uncore, GEN8_PCU_);
-
- spin_lock_irq(&dev_priv->irq_lock);
- if (dev_priv->display_irqs_enabled)
- vlv_display_irq_reset(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
-}
-
-static u32 ibx_hotplug_enables(struct intel_encoder *encoder)
-{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-
- switch (encoder->hpd_pin) {
- case HPD_PORT_A:
- /*
- * When CPU and PCH are on the same package, port A
- * HPD must be enabled in both north and south.
- */
- return HAS_PCH_LPT_LP(i915) ?
- PORTA_HOTPLUG_ENABLE : 0;
- case HPD_PORT_B:
- return PORTB_HOTPLUG_ENABLE |
- PORTB_PULSE_DURATION_2ms;
- case HPD_PORT_C:
- return PORTC_HOTPLUG_ENABLE |
- PORTC_PULSE_DURATION_2ms;
- case HPD_PORT_D:
- return PORTD_HOTPLUG_ENABLE |
- PORTD_PULSE_DURATION_2ms;
- default:
- return 0;
- }
-}
-
-static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
-{
- /*
- * Enable digital hotplug on the PCH, and configure the DP short pulse
- * duration to 2ms (which is the minimum in the Display Port spec).
- * The pulse duration bits are reserved on LPT+.
- */
- intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
- PORTA_HOTPLUG_ENABLE |
- PORTB_HOTPLUG_ENABLE |
- PORTC_HOTPLUG_ENABLE |
- PORTD_HOTPLUG_ENABLE |
- PORTB_PULSE_DURATION_MASK |
- PORTC_PULSE_DURATION_MASK |
- PORTD_PULSE_DURATION_MASK,
- intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables));
-}
-
-static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
-{
- u32 hotplug_irqs, enabled_irqs;
-
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
-
- ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
+ if (master_ctl & GEN11_DISPLAY_IRQ)
+ gen11_display_irq_handler(i915);
- ibx_hpd_detection_setup(dev_priv);
-}
+ gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
-static u32 icp_ddi_hotplug_enables(struct intel_encoder *encoder)
-{
- switch (encoder->hpd_pin) {
- case HPD_PORT_A:
- case HPD_PORT_B:
- case HPD_PORT_C:
- case HPD_PORT_D:
- return SHOTPLUG_CTL_DDI_HPD_ENABLE(encoder->hpd_pin);
- default:
- return 0;
- }
-}
+ gen11_master_intr_enable(regs);
-static u32 icp_tc_hotplug_enables(struct intel_encoder *encoder)
-{
- switch (encoder->hpd_pin) {
- case HPD_PORT_TC1:
- case HPD_PORT_TC2:
- case HPD_PORT_TC3:
- case HPD_PORT_TC4:
- case HPD_PORT_TC5:
- case HPD_PORT_TC6:
- return ICP_TC_HPD_ENABLE(encoder->hpd_pin);
- default:
- return 0;
- }
-}
+ gen11_gu_misc_irq_handler(i915, gu_misc_iir);
-static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
-{
- intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_DDI,
- SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A) |
- SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) |
- SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) |
- SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_D),
- intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables));
-}
+ pmu_irq_stats(i915, IRQ_HANDLED);
-static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
-{
- intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_TC,
- ICP_TC_HPD_ENABLE(HPD_PORT_TC1) |
- ICP_TC_HPD_ENABLE(HPD_PORT_TC2) |
- ICP_TC_HPD_ENABLE(HPD_PORT_TC3) |
- ICP_TC_HPD_ENABLE(HPD_PORT_TC4) |
- ICP_TC_HPD_ENABLE(HPD_PORT_TC5) |
- ICP_TC_HPD_ENABLE(HPD_PORT_TC6),
- intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables));
+ return IRQ_HANDLED;
}
-static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static inline u32 dg1_master_intr_disable(void __iomem * const regs)
{
- u32 hotplug_irqs, enabled_irqs;
+ u32 val;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
+ /* First disable interrupts */
+ raw_reg_write(regs, DG1_MSTR_TILE_INTR, 0);
- if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
- intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
+ /* Get the indication levels and ack the master unit */
+ val = raw_reg_read(regs, DG1_MSTR_TILE_INTR);
+ if (unlikely(!val))
+ return 0;
- ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
+ raw_reg_write(regs, DG1_MSTR_TILE_INTR, val);
- icp_ddi_hpd_detection_setup(dev_priv);
- icp_tc_hpd_detection_setup(dev_priv);
+ return val;
}
-static u32 gen11_hotplug_enables(struct intel_encoder *encoder)
+static inline void dg1_master_intr_enable(void __iomem * const regs)
{
- switch (encoder->hpd_pin) {
- case HPD_PORT_TC1:
- case HPD_PORT_TC2:
- case HPD_PORT_TC3:
- case HPD_PORT_TC4:
- case HPD_PORT_TC5:
- case HPD_PORT_TC6:
- return GEN11_HOTPLUG_CTL_ENABLE(encoder->hpd_pin);
- default:
- return 0;
- }
+ raw_reg_write(regs, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
}
-static void dg1_hpd_invert(struct drm_i915_private *i915)
+static irqreturn_t dg1_irq_handler(int irq, void *arg)
{
- u32 val = (INVERT_DDIA_HPD |
- INVERT_DDIB_HPD |
- INVERT_DDIC_HPD |
- INVERT_DDID_HPD);
- intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN1, 0, val);
-}
+ struct drm_i915_private * const i915 = arg;
+ struct intel_gt *gt = to_gt(i915);
+ void __iomem * const regs = gt->uncore->regs;
+ u32 master_tile_ctl, master_ctl;
+ u32 gu_misc_iir;
-static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
-{
- dg1_hpd_invert(dev_priv);
- icp_hpd_irq_setup(dev_priv);
-}
+ if (!intel_irqs_enabled(i915))
+ return IRQ_NONE;
-static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
-{
- intel_uncore_rmw(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL,
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6),
- intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables));
-}
+ master_tile_ctl = dg1_master_intr_disable(regs);
+ if (!master_tile_ctl) {
+ dg1_master_intr_enable(regs);
+ return IRQ_NONE;
+ }
-static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
-{
- intel_uncore_rmw(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL,
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
- GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6),
- intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables));
-}
+ /* FIXME: we only support tile 0 for now. */
+ if (master_tile_ctl & DG1_MSTR_TILE(0)) {
+ master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
+ raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl);
+ } else {
+ drm_err(&i915->drm, "Tile not supported: 0x%08x\n",
+ master_tile_ctl);
+ dg1_master_intr_enable(regs);
+ return IRQ_NONE;
+ }
-static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
-{
- u32 hotplug_irqs, enabled_irqs;
+ gen11_gt_irq_handler(gt, master_ctl);
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
+ if (master_ctl & GEN11_DISPLAY_IRQ)
+ gen11_display_irq_handler(i915);
- intel_uncore_rmw(&dev_priv->uncore, GEN11_DE_HPD_IMR, hotplug_irqs,
- ~enabled_irqs & hotplug_irqs);
- intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
+ gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
- gen11_tc_hpd_detection_setup(dev_priv);
- gen11_tbt_hpd_detection_setup(dev_priv);
+ dg1_master_intr_enable(regs);
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- icp_hpd_irq_setup(dev_priv);
-}
+ gen11_gu_misc_irq_handler(i915, gu_misc_iir);
-static u32 spt_hotplug_enables(struct intel_encoder *encoder)
-{
- switch (encoder->hpd_pin) {
- case HPD_PORT_A:
- return PORTA_HOTPLUG_ENABLE;
- case HPD_PORT_B:
- return PORTB_HOTPLUG_ENABLE;
- case HPD_PORT_C:
- return PORTC_HOTPLUG_ENABLE;
- case HPD_PORT_D:
- return PORTD_HOTPLUG_ENABLE;
- default:
- return 0;
- }
-}
+ pmu_irq_stats(i915, IRQ_HANDLED);
-static u32 spt_hotplug2_enables(struct intel_encoder *encoder)
-{
- switch (encoder->hpd_pin) {
- case HPD_PORT_E:
- return PORTE_HOTPLUG_ENABLE;
- default:
- return 0;
- }
+ return IRQ_HANDLED;
}
-static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
+static void ibx_irq_reset(struct drm_i915_private *dev_priv)
{
- /* Display WA #1179 WaHardHangonHotPlug: cnp */
- if (HAS_PCH_CNP(dev_priv)) {
- intel_uncore_rmw(&dev_priv->uncore, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK,
- CHASSIS_CLK_REQ_DURATION(0xf));
- }
+ struct intel_uncore *uncore = &dev_priv->uncore;
- /* Enable digital hotplug on the PCH */
- intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
- PORTA_HOTPLUG_ENABLE |
- PORTB_HOTPLUG_ENABLE |
- PORTC_HOTPLUG_ENABLE |
- PORTD_HOTPLUG_ENABLE,
- intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables));
+ if (HAS_PCH_NOP(dev_priv))
+ return;
+
+ GEN3_IRQ_RESET(uncore, SDE);
- intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG2, PORTE_HOTPLUG_ENABLE,
- intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables));
+ if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
+ intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff);
}
-static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
+/* drm_dma.h hooks
+*/
+static void ilk_irq_reset(struct drm_i915_private *dev_priv)
{
- u32 hotplug_irqs, enabled_irqs;
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
+ GEN3_IRQ_RESET(uncore, DE);
+ dev_priv->irq_mask = ~0u;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
- intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
+ if (GRAPHICS_VER(dev_priv) == 7)
+ intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
+ if (IS_HASWELL(dev_priv)) {
+ intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
+ intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
+ }
- ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
+ gen5_gt_irq_reset(to_gt(dev_priv));
- spt_hpd_detection_setup(dev_priv);
+ ibx_irq_reset(dev_priv);
}
-static u32 ilk_hotplug_enables(struct intel_encoder *encoder)
+static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
{
- switch (encoder->hpd_pin) {
- case HPD_PORT_A:
- return DIGITAL_PORTA_HOTPLUG_ENABLE |
- DIGITAL_PORTA_PULSE_DURATION_2ms;
- default:
- return 0;
- }
-}
+ intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
+ intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
-static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
-{
- /*
- * Enable digital hotplug on the CPU, and configure the DP short pulse
- * duration to 2ms (which is the minimum in the Display Port spec)
- * The pulse duration bits are reserved on HSW+.
- */
- intel_uncore_rmw(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL,
- DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_MASK,
- intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables));
+ gen5_gt_irq_reset(to_gt(dev_priv));
+
+ spin_lock_irq(&dev_priv->irq_lock);
+ if (dev_priv->display_irqs_enabled)
+ vlv_display_irq_reset(dev_priv);
+ spin_unlock_irq(&dev_priv->irq_lock);
}
-static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static void gen8_irq_reset(struct drm_i915_private *dev_priv)
{
- u32 hotplug_irqs, enabled_irqs;
+ struct intel_uncore *uncore = &dev_priv->uncore;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
+ gen8_master_intr_disable(uncore->regs);
- if (DISPLAY_VER(dev_priv) >= 8)
- bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
- else
- ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
+ gen8_gt_irq_reset(to_gt(dev_priv));
+ gen8_display_irq_reset(dev_priv);
+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
- ilk_hpd_detection_setup(dev_priv);
+ if (HAS_PCH_SPLIT(dev_priv))
+ ibx_irq_reset(dev_priv);
- ibx_hpd_irq_setup(dev_priv);
}
-static u32 bxt_hotplug_enables(struct intel_encoder *encoder)
+static void gen11_irq_reset(struct drm_i915_private *dev_priv)
{
- u32 hotplug;
-
- switch (encoder->hpd_pin) {
- case HPD_PORT_A:
- hotplug = PORTA_HOTPLUG_ENABLE;
- if (intel_bios_encoder_hpd_invert(encoder->devdata))
- hotplug |= BXT_DDIA_HPD_INVERT;
- return hotplug;
- case HPD_PORT_B:
- hotplug = PORTB_HOTPLUG_ENABLE;
- if (intel_bios_encoder_hpd_invert(encoder->devdata))
- hotplug |= BXT_DDIB_HPD_INVERT;
- return hotplug;
- case HPD_PORT_C:
- hotplug = PORTC_HOTPLUG_ENABLE;
- if (intel_bios_encoder_hpd_invert(encoder->devdata))
- hotplug |= BXT_DDIC_HPD_INVERT;
- return hotplug;
- default:
- return 0;
- }
-}
+ struct intel_gt *gt = to_gt(dev_priv);
+ struct intel_uncore *uncore = gt->uncore;
-static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
-{
- intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
- PORTA_HOTPLUG_ENABLE |
- PORTB_HOTPLUG_ENABLE |
- PORTC_HOTPLUG_ENABLE |
- BXT_DDI_HPD_INVERT_MASK,
- intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables));
+ gen11_master_intr_disable(dev_priv->uncore.regs);
+
+ gen11_gt_irq_reset(gt);
+ gen11_display_irq_reset(dev_priv);
+
+ GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
}
-static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static void dg1_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_gt *gt = to_gt(dev_priv);
- struct intel_uncore *uncore = gt->uncore;
- u32 hotplug_irqs, enabled_irqs;
++ struct intel_uncore *uncore = &dev_priv->uncore;
++ struct intel_gt *gt;
++ unsigned int i;
+
+ dg1_master_intr_disable(dev_priv->uncore.regs);
- gen11_gt_irq_reset(gt);
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
++ for_each_gt(gt, dev_priv, i)
++ gen11_gt_irq_reset(gt);
+
- bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
+ gen11_display_irq_reset(dev_priv);
- bxt_hpd_detection_setup(dev_priv);
+ GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
}
-/*
- * SDEIER is also touched by the interrupt handler to work around missed PCH
- * interrupts. Hence we can't update it after the interrupt handler is enabled -
- * instead we unconditionally enable all PCH interrupt sources here, but then
- * only unmask them as needed with SDEIMR.
- *
- * Note that we currently do this after installing the interrupt handler,
- * but before we enable the master interrupt. That should be sufficient
- * to avoid races with the irq handler, assuming we have MSI. Shared legacy
- * interrupts could still race.
- */
-static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
+static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
- u32 mask;
- if (HAS_PCH_NOP(dev_priv))
- return;
+ intel_uncore_write(uncore, GEN8_MASTER_IRQ, 0);
+ intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
- if (HAS_PCH_IBX(dev_priv))
- mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
- else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
- mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
- else
- mask = SDE_GMBUS_CPT;
+ gen8_gt_irq_reset(to_gt(dev_priv));
- GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+
+ spin_lock_irq(&dev_priv->irq_lock);
+ if (dev_priv->display_irqs_enabled)
+ vlv_display_irq_reset(dev_priv);
+ spin_unlock_irq(&dev_priv->irq_lock);
}
static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
#include <drm/i915_pciids.h>
#include "display/intel_display.h"
+#include "display/intel_display_driver.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_sa_media.h"
+ #include "gem/i915_gem_object_types.h"
#include "i915_driver.h"
#include "i915_drv.h"
#define PLATFORM(x) .platform = (x)
#define GEN(x) \
.__runtime.graphics.ip.ver = (x), \
- .__runtime.media.ip.ver = (x), \
- .__runtime.display.ip.ver = (x)
-
-#define NO_DISPLAY .__runtime.pipe_mask = 0
-
-#define I845_PIPE_OFFSETS \
- .display.pipe_offsets = { \
- [TRANSCODER_A] = PIPE_A_OFFSET, \
- }, \
- .display.trans_offsets = { \
- [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- }
-
-#define I9XX_PIPE_OFFSETS \
- .display.pipe_offsets = { \
- [TRANSCODER_A] = PIPE_A_OFFSET, \
- [TRANSCODER_B] = PIPE_B_OFFSET, \
- }, \
- .display.trans_offsets = { \
- [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- }
-
-#define IVB_PIPE_OFFSETS \
- .display.pipe_offsets = { \
- [TRANSCODER_A] = PIPE_A_OFFSET, \
- [TRANSCODER_B] = PIPE_B_OFFSET, \
- [TRANSCODER_C] = PIPE_C_OFFSET, \
- }, \
- .display.trans_offsets = { \
- [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
- }
-
-#define HSW_PIPE_OFFSETS \
- .display.pipe_offsets = { \
- [TRANSCODER_A] = PIPE_A_OFFSET, \
- [TRANSCODER_B] = PIPE_B_OFFSET, \
- [TRANSCODER_C] = PIPE_C_OFFSET, \
- [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
- }, \
- .display.trans_offsets = { \
- [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
- [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
- }
-
-#define CHV_PIPE_OFFSETS \
- .display.pipe_offsets = { \
- [TRANSCODER_A] = PIPE_A_OFFSET, \
- [TRANSCODER_B] = PIPE_B_OFFSET, \
- [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
- }, \
- .display.trans_offsets = { \
- [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
- }
-
-#define I845_CURSOR_OFFSETS \
- .display.cursor_offsets = { \
- [PIPE_A] = CURSOR_A_OFFSET, \
- }
-
-#define I9XX_CURSOR_OFFSETS \
- .display.cursor_offsets = { \
- [PIPE_A] = CURSOR_A_OFFSET, \
- [PIPE_B] = CURSOR_B_OFFSET, \
- }
-
-#define CHV_CURSOR_OFFSETS \
- .display.cursor_offsets = { \
- [PIPE_A] = CURSOR_A_OFFSET, \
- [PIPE_B] = CURSOR_B_OFFSET, \
- [PIPE_C] = CHV_CURSOR_C_OFFSET, \
- }
-
-#define IVB_CURSOR_OFFSETS \
- .display.cursor_offsets = { \
- [PIPE_A] = CURSOR_A_OFFSET, \
- [PIPE_B] = IVB_CURSOR_B_OFFSET, \
- [PIPE_C] = IVB_CURSOR_C_OFFSET, \
- }
-
-#define TGL_CURSOR_OFFSETS \
- .display.cursor_offsets = { \
- [PIPE_A] = CURSOR_A_OFFSET, \
- [PIPE_B] = IVB_CURSOR_B_OFFSET, \
- [PIPE_C] = IVB_CURSOR_C_OFFSET, \
- [PIPE_D] = TGL_CURSOR_D_OFFSET, \
- }
-
-#define I845_COLORS \
- .display.color = { .gamma_lut_size = 256 }
-#define I9XX_COLORS \
- .display.color = { .gamma_lut_size = 129, \
- .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- }
-#define ILK_COLORS \
- .display.color = { .gamma_lut_size = 1024 }
-#define IVB_COLORS \
- .display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
-#define CHV_COLORS \
- .display.color = { \
- .degamma_lut_size = 65, .gamma_lut_size = 257, \
- .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- }
-#define GLK_COLORS \
- .display.color = { \
- .degamma_lut_size = 33, .gamma_lut_size = 1024, \
- .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
- DRM_COLOR_LUT_EQUAL_CHANNELS, \
- }
-#define ICL_COLORS \
- .display.color = { \
- .degamma_lut_size = 33, .gamma_lut_size = 262145, \
- .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
- DRM_COLOR_LUT_EQUAL_CHANNELS, \
- .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- }
+ .__runtime.media.ip.ver = (x)
+ #define LEGACY_CACHELEVEL \
+ .cachelevel_to_pat = { \
+ [I915_CACHE_NONE] = 0, \
+ [I915_CACHE_LLC] = 1, \
+ [I915_CACHE_L3_LLC] = 2, \
+ [I915_CACHE_WT] = 3, \
+ }
+
+ #define TGL_CACHELEVEL \
+ .cachelevel_to_pat = { \
+ [I915_CACHE_NONE] = 3, \
+ [I915_CACHE_LLC] = 0, \
+ [I915_CACHE_L3_LLC] = 0, \
+ [I915_CACHE_WT] = 2, \
+ }
+
+ #define PVC_CACHELEVEL \
+ .cachelevel_to_pat = { \
+ [I915_CACHE_NONE] = 0, \
+ [I915_CACHE_LLC] = 3, \
+ [I915_CACHE_L3_LLC] = 3, \
+ [I915_CACHE_WT] = 2, \
+ }
+
+ #define MTL_CACHELEVEL \
+ .cachelevel_to_pat = { \
+ [I915_CACHE_NONE] = 2, \
+ [I915_CACHE_LLC] = 3, \
+ [I915_CACHE_L3_LLC] = 3, \
+ [I915_CACHE_WT] = 1, \
+ }
+
/* Keep in gen based order, and chronological order within a gen */
#define GEN_DEFAULT_PAGE_SIZES \
.has_snoop = true, \
.has_coherent_ggtt = false, \
.dma_mask_size = 32, \
- I9XX_PIPE_OFFSETS, \
- I9XX_CURSOR_OFFSETS, \
- I9XX_COLORS, \
+ .max_pat_index = 3, \
GEN_DEFAULT_PAGE_SIZES, \
- GEN_DEFAULT_REGIONS
+ GEN_DEFAULT_REGIONS, \
+ LEGACY_CACHELEVEL
#define I845_FEATURES \
GEN(2), \
.has_snoop = true, \
.has_coherent_ggtt = false, \
.dma_mask_size = 32, \
- I845_PIPE_OFFSETS, \
- I845_CURSOR_OFFSETS, \
- I845_COLORS, \
+ .max_pat_index = 3, \
GEN_DEFAULT_PAGE_SIZES, \
- GEN_DEFAULT_REGIONS
+ GEN_DEFAULT_REGIONS, \
+ LEGACY_CACHELEVEL
static const struct intel_device_info i830_info = {
I830_FEATURES,
.has_snoop = true, \
.has_coherent_ggtt = true, \
.dma_mask_size = 32, \
- I9XX_PIPE_OFFSETS, \
- I9XX_CURSOR_OFFSETS, \
- I9XX_COLORS, \
+ .max_pat_index = 3, \
GEN_DEFAULT_PAGE_SIZES, \
- GEN_DEFAULT_REGIONS
+ GEN_DEFAULT_REGIONS, \
+ LEGACY_CACHELEVEL
static const struct intel_device_info i915g_info = {
GEN3_FEATURES,
.has_snoop = true, \
.has_coherent_ggtt = true, \
.dma_mask_size = 36, \
- I9XX_PIPE_OFFSETS, \
- I9XX_CURSOR_OFFSETS, \
- I9XX_COLORS, \
+ .max_pat_index = 3, \
GEN_DEFAULT_PAGE_SIZES, \
- GEN_DEFAULT_REGIONS
+ GEN_DEFAULT_REGIONS, \
+ LEGACY_CACHELEVEL
static const struct intel_device_info i965g_info = {
GEN4_FEATURES,
/* ilk does support rc6, but we do not implement [power] contexts */ \
.has_rc6 = 0, \
.dma_mask_size = 36, \
- I9XX_PIPE_OFFSETS, \
- I9XX_CURSOR_OFFSETS, \
- ILK_COLORS, \
+ .max_pat_index = 3, \
GEN_DEFAULT_PAGE_SIZES, \
- GEN_DEFAULT_REGIONS
+ GEN_DEFAULT_REGIONS, \
+ LEGACY_CACHELEVEL
static const struct intel_device_info ilk_d_info = {
GEN5_FEATURES,
.has_rc6p = 0, \
.has_rps = true, \
.dma_mask_size = 40, \
+ .max_pat_index = 3, \
.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
.__runtime.ppgtt_size = 31, \
- I9XX_PIPE_OFFSETS, \
- I9XX_CURSOR_OFFSETS, \
- ILK_COLORS, \
GEN_DEFAULT_PAGE_SIZES, \
- GEN_DEFAULT_REGIONS
+ GEN_DEFAULT_REGIONS, \
+ LEGACY_CACHELEVEL
#define SNB_D_PLATFORM \
GEN6_FEATURES, \
.has_reset_engine = true, \
.has_rps = true, \
.dma_mask_size = 40, \
+ .max_pat_index = 3, \
.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
.__runtime.ppgtt_size = 31, \
- IVB_PIPE_OFFSETS, \
- IVB_CURSOR_OFFSETS, \
- IVB_COLORS, \
GEN_DEFAULT_PAGE_SIZES, \
- GEN_DEFAULT_REGIONS
+ GEN_DEFAULT_REGIONS, \
+ LEGACY_CACHELEVEL
#define IVB_D_PLATFORM \
GEN7_FEATURES, \
.has_rc6 = 1,
.has_reset_engine = true,
.has_rps = true,
- .display.has_gmch = 1,
- .display.has_hotplug = 1,
.dma_mask_size = 40,
+ .max_pat_index = 3,
.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
.__runtime.ppgtt_size = 31,
.has_snoop = true,
.has_coherent_ggtt = false,
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
- .display.mmio_offset = VLV_DISPLAY_BASE,
- I9XX_PIPE_OFFSETS,
- I9XX_CURSOR_OFFSETS,
- I9XX_COLORS,
GEN_DEFAULT_PAGE_SIZES,
GEN_DEFAULT_REGIONS,
+ LEGACY_CACHELEVEL,
};
#define G75_FEATURES \
.has_rc6 = 1,
.has_rps = true,
.has_logical_ring_contexts = 1,
- .display.has_gmch = 1,
.dma_mask_size = 39,
+ .max_pat_index = 3,
.__runtime.ppgtt_type = INTEL_PPGTT_FULL,
.__runtime.ppgtt_size = 32,
.has_reset_engine = 1,
.has_snoop = true,
.has_coherent_ggtt = false,
- .display.mmio_offset = VLV_DISPLAY_BASE,
- CHV_PIPE_OFFSETS,
- CHV_CURSOR_OFFSETS,
- CHV_COLORS,
GEN_DEFAULT_PAGE_SIZES,
GEN_DEFAULT_REGIONS,
+ LEGACY_CACHELEVEL,
};
#define GEN9_DEFAULT_PAGE_SIZES \
.has_reset_engine = 1, \
.has_snoop = true, \
.has_coherent_ggtt = false, \
- .display.has_ipc = 1, \
+ .max_pat_index = 3, \
- HSW_PIPE_OFFSETS, \
- IVB_CURSOR_OFFSETS, \
- IVB_COLORS, \
GEN9_DEFAULT_PAGE_SIZES, \
- GEN_DEFAULT_REGIONS
+ GEN_DEFAULT_REGIONS, \
+ LEGACY_CACHELEVEL
static const struct intel_device_info bxt_info = {
GEN9_LP_FEATURES,
#define GEN12_FEATURES \
GEN11_FEATURES, \
GEN(12), \
- .display.abox_mask = GENMASK(2, 1), \
- .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
- BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
- .display.pipe_offsets = { \
- [TRANSCODER_A] = PIPE_A_OFFSET, \
- [TRANSCODER_B] = PIPE_B_OFFSET, \
- [TRANSCODER_C] = PIPE_C_OFFSET, \
- [TRANSCODER_D] = PIPE_D_OFFSET, \
- [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
- [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
- }, \
- .display.trans_offsets = { \
- [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
- [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
- [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
- [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
- }, \
- TGL_CURSOR_OFFSETS, \
+ TGL_CACHELEVEL, \
.has_global_mocs = 1, \
- .has_pxp = 1
+ .has_pxp = 1, \
- .display.has_dsb = 1, \
+ .max_pat_index = 3
static const struct intel_device_info tgl_info = {
GEN12_FEATURES,
.__runtime.graphics.ip.rel = 60,
.__runtime.media.ip.rel = 60,
PLATFORM(INTEL_PONTEVECCHIO),
- NO_DISPLAY,
.has_flat_ccs = 0,
+ .max_pat_index = 7,
.__runtime.platform_engine_mask =
BIT(BCS0) |
BIT(VCS0) |
BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
.require_force_probe = 1,
+ PVC_CACHELEVEL,
};
-#define XE_LPDP_FEATURES \
- XE_LPD_FEATURES, \
- .__runtime.display.ip.ver = 14, \
- .display.has_cdclk_crawl = 1, \
- .display.has_cdclk_squash = 1, \
- .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
-
static const struct intel_gt_definition xelpmp_extra_gt[] = {
{
.type = GT_MEDIA,
projects / platform / kernel / linux-starfive.git / commitdiff