drm/amd/powerplay: add some new structures for Vega10

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
index 2930a33..c0193e0 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
@@ -30,15 +30,17 @@
 
 struct phm_ppt_v1_clock_voltage_dependency_record {
        uint32_t clk;
-       uint8_t vddInd;
+       uint8_t  vddInd;
+       uint8_t  vddciInd;
+       uint8_t  mvddInd;
        uint16_t vdd_offset;
        uint16_t vddc;
        uint16_t vddgfx;
        uint16_t vddci;
        uint16_t mvdd;
-       uint8_t phases;
-       uint8_t cks_enable;
-       uint8_t cks_voffset;
+       uint8_t  phases;
+       uint8_t  cks_enable;
+       uint8_t  cks_voffset;
        uint32_t sclk_offset;
 };
 
@@ -94,6 +96,7 @@ struct phm_ppt_v1_pcie_record {
        uint8_t gen_speed;
        uint8_t lane_width;
        uint16_t usreserved;
+       uint16_t reserved;
        uint32_t pcie_sclk;
 };
 typedef struct phm_ppt_v1_pcie_record phm_ppt_v1_pcie_record;
@@ -104,5 +107,10 @@ struct phm_ppt_v1_pcie_table {
 };
 typedef struct phm_ppt_v1_pcie_table phm_ppt_v1_pcie_table;
 
+struct phm_ppt_v1_gpio_table {
+       uint8_t vrhot_triggered_sclk_dpm_index;           /* SCLK DPM level index to switch to when VRHot is triggered */
+};
+typedef struct phm_ppt_v1_gpio_table phm_ppt_v1_gpio_table;
+
 #endif
 

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index 80ed659..b485bec 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -182,6 +182,7 @@ enum phm_platform_caps {
        PHM_PlatformCaps_Thermal2GPIO17,                        /* indicates thermal2GPIO17 table support */
        PHM_PlatformCaps_ThermalOutGPIO,                        /* indicates ThermalOutGPIO support, pin number is assigned by VBIOS */
        PHM_PlatformCaps_DisableMclkSwitchingForFrameLock,      /* Disable memory clock switch during Framelock */
+       PHM_PlatformCaps_ForceMclkHigh,                         /* Disable memory clock switching by forcing memory clock high */
        PHM_PlatformCaps_VRHotGPIOConfigurable,                 /* indicates VR_HOT GPIO configurable */
        PHM_PlatformCaps_TempInversion,                         /* enable Temp Inversion feature */
        PHM_PlatformCaps_IOIC3,
@@ -212,6 +213,20 @@ enum phm_platform_caps {
        PHM_PlatformCaps_TablelessHardwareInterface,
        PHM_PlatformCaps_EnableDriverEVV,
        PHM_PlatformCaps_SPLLShutdownSupport,
+       PHM_PlatformCaps_VirtualBatteryState,
+       PHM_PlatformCaps_IgnoreForceHighClockRequestsInAPUs,
+       PHM_PlatformCaps_DisableMclkSwitchForVR,
+       PHM_PlatformCaps_SMU8,
+       PHM_PlatformCaps_VRHotPolarityHigh,
+       PHM_PlatformCaps_IPS_UlpsExclusive,
+       PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme,
+       PHM_PlatformCaps_GeminiAsymmetricPower,
+       PHM_PlatformCaps_OCLPowerOptimization,
+       PHM_PlatformCaps_MaxPCIEBandWidth,
+       PHM_PlatformCaps_PerfPerWattOptimizationSupport,
+       PHM_PlatformCaps_UVDClientMCTuning,
+       PHM_PlatformCaps_ODNinACSupport,
+       PHM_PlatformCaps_ODNinDCSupport,
        PHM_PlatformCaps_Max
 };
 
@@ -290,6 +305,8 @@ struct PP_Clocks {
        uint32_t memoryClock;
        uint32_t BusBandwidth;
        uint32_t engineClockInSR;
+       uint32_t dcefClock;
+       uint32_t dcefClockInSR;
 };
 
 struct pp_clock_info {
@@ -334,6 +351,21 @@ struct phm_clocks {
        uint32_t clock[MAX_NUM_CLOCKS];
 };
 
+struct phm_odn_performance_level {
+       uint32_t clock;
+       uint32_t vddc;
+       bool enabled;
+};
+
+struct phm_odn_clock_levels {
+       uint32_t size;
+       uint32_t options;
+       uint32_t flags;
+       uint32_t number_of_performance_levels;
+       /* variable-sized array, specify by ulNumberOfPerformanceLevels. */
+       struct phm_odn_performance_level performance_level_entries[8];
+};
+
 extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
 extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
 extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index d5aa6cd..02185d4 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -83,7 +83,8 @@ enum PP_FEATURE_MASK {
        PP_ULV_MASK = 0x100,
        PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
        PP_CLOCK_STRETCH_MASK = 0x400,
-       PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800
+       PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
+       PP_SOCCLK_DPM_MASK = 0x1000,
 };
 
 enum PHM_BackEnd_Magic {
@@ -412,6 +413,7 @@ struct phm_cac_tdp_table {
        uint16_t usLowCACLeakage;
        uint16_t usHighCACLeakage;
        uint16_t usMaximumPowerDeliveryLimit;
+       uint16_t usEDCLimit;
        uint16_t usOperatingTempMinLimit;
        uint16_t usOperatingTempMaxLimit;
        uint16_t usOperatingTempStep;
@@ -438,6 +440,46 @@ struct phm_cac_tdp_table {
        uint8_t  ucCKS_LDO_REFSEL;
 };
 
+struct phm_tdp_table {
+       uint16_t usTDP;
+       uint16_t usConfigurableTDP;
+       uint16_t usTDC;
+       uint16_t usBatteryPowerLimit;
+       uint16_t usSmallPowerLimit;
+       uint16_t usLowCACLeakage;
+       uint16_t usHighCACLeakage;
+       uint16_t usMaximumPowerDeliveryLimit;
+       uint16_t usEDCLimit;
+       uint16_t usOperatingTempMinLimit;
+       uint16_t usOperatingTempMaxLimit;
+       uint16_t usOperatingTempStep;
+       uint16_t usOperatingTempHyst;
+       uint16_t usDefaultTargetOperatingTemp;
+       uint16_t usTargetOperatingTemp;
+       uint16_t usPowerTuneDataSetID;
+       uint16_t usSoftwareShutdownTemp;
+       uint16_t usClockStretchAmount;
+       uint16_t usTemperatureLimitTedge;
+       uint16_t usTemperatureLimitHotspot;
+       uint16_t usTemperatureLimitLiquid1;
+       uint16_t usTemperatureLimitLiquid2;
+       uint16_t usTemperatureLimitHBM;
+       uint16_t usTemperatureLimitVrVddc;
+       uint16_t usTemperatureLimitVrMvdd;
+       uint16_t usTemperatureLimitPlx;
+       uint8_t  ucLiquid1_I2C_address;
+       uint8_t  ucLiquid2_I2C_address;
+       uint8_t  ucLiquid_I2C_Line;
+       uint8_t  ucVr_I2C_address;
+       uint8_t  ucVr_I2C_Line;
+       uint8_t  ucPlx_I2C_address;
+       uint8_t  ucPlx_I2C_Line;
+       uint8_t  ucLiquid_I2C_LineSDA;
+       uint8_t  ucVr_I2C_LineSDA;
+       uint8_t  ucPlx_I2C_LineSDA;
+       uint32_t usBoostPowerLimit;
+};
+
 struct phm_ppm_table {
        uint8_t   ppm_design;
        uint16_t  cpu_core_number;
@@ -472,9 +514,11 @@ struct phm_vq_budgeting_table {
 struct phm_clock_and_voltage_limits {
        uint32_t sclk;
        uint32_t mclk;
+       uint32_t gfxclk;
        uint16_t vddc;
        uint16_t vddci;
        uint16_t vddgfx;
+       uint16_t vddmem;
 };
 
 /* Structure to hold PPTable information */
@@ -482,18 +526,77 @@ struct phm_clock_and_voltage_limits {
 struct phm_ppt_v1_information {
        struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
        struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
+       struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
+       struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
        struct phm_clock_array *valid_sclk_values;
        struct phm_clock_array *valid_mclk_values;
+       struct phm_clock_array *valid_socclk_values;
+       struct phm_clock_array *valid_dcefclk_values;
        struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
        struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
        struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
        struct phm_ppm_table *ppm_parameter_table;
        struct phm_cac_tdp_table *cac_dtp_table;
+       struct phm_tdp_table *tdp_table;
+       struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
+       struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
+       struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
+       struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
+       struct phm_ppt_v1_pcie_table *pcie_table;
+       struct phm_ppt_v1_gpio_table *gpio_table;
+       uint16_t us_ulv_voltage_offset;
+       uint16_t us_ulv_smnclk_did;
+       uint16_t us_ulv_mp1clk_did;
+       uint16_t us_ulv_gfxclk_bypass;
+       uint16_t us_gfxclk_slew_rate;
+       uint16_t us_min_gfxclk_freq_limit;
+};
+
+struct phm_ppt_v2_information {
+       struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
+       struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
+       struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
+       struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
+       struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
+       struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
+       struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
        struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
+
+       struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
+
+       struct phm_clock_array *valid_sclk_values;
+       struct phm_clock_array *valid_mclk_values;
+       struct phm_clock_array *valid_socclk_values;
+       struct phm_clock_array *valid_dcefclk_values;
+
+       struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
+       struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
+
+       struct phm_ppm_table *ppm_parameter_table;
+       struct phm_cac_tdp_table *cac_dtp_table;
+       struct phm_tdp_table *tdp_table;
+
        struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
        struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
+       struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
+       struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
+
        struct phm_ppt_v1_pcie_table *pcie_table;
+
        uint16_t us_ulv_voltage_offset;
+       uint16_t us_ulv_smnclk_did;
+       uint16_t us_ulv_mp1clk_did;
+       uint16_t us_ulv_gfxclk_bypass;
+       uint16_t us_gfxclk_slew_rate;
+       uint16_t us_min_gfxclk_freq_limit;
+
+       uint8_t  uc_gfx_dpm_voltage_mode;
+       uint8_t  uc_soc_dpm_voltage_mode;
+       uint8_t  uc_uclk_dpm_voltage_mode;
+       uint8_t  uc_uvd_dpm_voltage_mode;
+       uint8_t  uc_vce_dpm_voltage_mode;
+       uint8_t  uc_mp0_dpm_voltage_mode;
+       uint8_t  uc_dcef_dpm_voltage_mode;
 };
 
 struct phm_dynamic_state_info {
@@ -572,6 +675,13 @@ struct pp_advance_fan_control_parameters {
        uint16_t  usFanGainVrMvdd;
        uint16_t  usFanGainPlx;
        uint16_t  usFanGainHbm;
+       uint8_t   ucEnableZeroRPM;
+       uint8_t   ucFanStopTemperature;
+       uint8_t   ucFanStartTemperature;
+       uint32_t  ulMaxFanSCLKAcousticLimit;       /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */
+       uint32_t  ulTargetGfxClk;
+       uint16_t  usZeroRPMStartTemperature;
+       uint16_t  usZeroRPMStopTemperature;
 };
 
 struct pp_thermal_controller_info {