MachineOperand &Src0 = MI.getOperand(Src0Idx);
if (Src0.isReg()) {
Register Reg = Src0.getReg();
- if (Reg.isVirtual() && MRI->hasOneUse(Reg)) {
+ if (Reg.isVirtual()) {
MachineInstr *Def = MRI->getUniqueVRegDef(Reg);
if (Def && Def->isMoveImmediate()) {
MachineOperand &MovSrc = Def->getOperand(1);
}
if (ConstantFolded) {
- assert(MRI->use_empty(Reg));
- Def->eraseFromParent();
+ if (MRI->use_nodbg_empty(Reg))
+ Def->eraseFromParent();
++NumLiteralConstantsFolded;
return true;
}
}
}
- // FIXME: We also need to consider movs of constant operands since
- // immediate operands are not folded if they have more than one use, and
- // the operand folding pass is unaware if the immediate will be free since
- // it won't know if the src == dest constraint will end up being
- // satisfied.
+ // Try to use S_ADDK_I32 and S_MULK_I32.
if (MI.getOpcode() == AMDGPU::S_ADD_I32 ||
MI.getOpcode() == AMDGPU::S_MUL_I32) {
const MachineOperand *Dest = &MI.getOperand(0);
; GFX8-LABEL: v_add_v2i16_fneg_lhs_fneg_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_mov_b32 s4, 0x80008000
-; GFX8-NEXT: v_xor_b32_e32 v0, s4, v0
-; GFX8-NEXT: v_xor_b32_e32 v1, s4, v1
+; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
; GFX8-NEXT: v_add_u16_e32 v2, v0, v1
; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
; GFX7-LABEL: v_uaddo_i8:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_movk_i32 s4, 0xff
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v0
; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX8-LABEL: v_uaddo_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s4, 0xff
-; GFX8-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX8-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
-; GFX8-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v0
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
; GFX7-LABEL: v_uaddo_i7:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_movk_i32 s4, 0x7f
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0x7f, v0
; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX8-LABEL: v_uaddo_i7:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s4, 0x7f
-; GFX8-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX8-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
-; GFX8-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v0
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
; GFX9-LABEL: v_uaddo_i7:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_movk_i32 s4, 0x7f
-; GFX9-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX9-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
-; GFX9-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v0
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
; GFX7-LABEL: s_uaddo_i8:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_movk_i32 s4, 0xff
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v0
; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX8-LABEL: s_uaddo_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s4, 0xff
-; GFX8-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX8-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
-; GFX8-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v0
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
; GFX7-LABEL: s_uaddo_i7:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_movk_i32 s4, 0x7f
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0x7f, v0
; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX8-LABEL: s_uaddo_i7:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s4, 0x7f
-; GFX8-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX8-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
-; GFX8-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v0
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
; GFX9-LABEL: s_uaddo_i7:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_movk_i32 s4, 0x7f
-; GFX9-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX9-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
-; GFX9-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v0
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
define amdgpu_ps i16 @uaddo_i16_sv(i16 inreg %a, i16 %b) {
; GFX7-LABEL: uaddo_i16_sv:
; GFX7: ; %bb.0:
-; GFX7-NEXT: s_mov_b32 s1, 0xffff
; GFX7-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX7-NEXT: v_and_b32_e32 v0, s1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_add_i32_e32 v0, vcc, s0, v0
-; GFX7-NEXT: v_and_b32_e32 v1, s1, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v0
; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
;
; GFX8-LABEL: uaddo_i16_sv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_mov_b32 s1, 0xffff
; GFX8-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX8-NEXT: v_and_b32_e32 v0, s1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
-; GFX8-NEXT: v_and_b32_e32 v1, s1, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v0
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
; GFX6-LABEL: v_andn2_v2i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_and_b32_e32 v0, v0, v4
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v4
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX6-NEXT: v_and_b32_e32 v0, v0, v1
; GFX6-LABEL: v_andn2_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v8, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_and_b32_e32 v0, v0, v8
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v8
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v5
-; GFX6-NEXT: v_and_b32_e32 v3, v4, v8
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v4
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX6-NEXT: v_and_b32_e32 v4, v6, v8
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v6
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX6-NEXT: v_xor_b32_e32 v3, -1, v3
; GFX6-LABEL: v_ashr_v2i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v1, v2, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
define amdgpu_ps float @ashr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {
; GFX6-LABEL: ashr_v2i16_sv:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_mov_b32 s2, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: v_ashr_i32_e32 v0, s0, v0
-; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: s_sext_i32_i16 s0, s1
; GFX6-NEXT: v_ashr_i32_e32 v1, s0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog
; GFX6-NEXT: v_ashrrev_i32_e32 v0, s0, v0
; GFX6-NEXT: s_and_b32 s0, s1, 0xffff
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v1, s0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog
; GFX6-LABEL: v_ashr_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v0, v4, v0
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v5
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v1, v4, v1
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v6
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v6
; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v2, v4, v2
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v7
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7
; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v3, v4, v3
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX6-LABEL: v_ashr_v8i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v8
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v0, v8, v0
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v9
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v9
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v1, v8, v1
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v10
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v10
; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v2, v8, v2
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v11
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v11
; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16
-; GFX6-NEXT: v_mov_b32_e32 v16, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v3, v8, v3
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v12
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v12
; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v4, v8, v4
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v13
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v13
; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16
-; GFX6-NEXT: v_and_b32_e32 v1, v1, v16
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v5, v8, v5
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v14
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v14
; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16
-; GFX6-NEXT: v_and_b32_e32 v0, v0, v16
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v6, v8, v6
-; GFX6-NEXT: v_and_b32_e32 v8, v15, v16
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v15
; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, v2, v16
-; GFX6-NEXT: v_and_b32_e32 v2, v3, v16
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v7, v8, v7
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_and_b32_e32 v3, v5, v16
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v5
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_and_b32_e32 v2, v4, v16
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_and_b32_e32 v4, v7, v16
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX6-NEXT: v_and_b32_e32 v3, v6, v16
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX9-CONTRACT-LABEL: test_f16_sub_ext_neg_mul:
; GFX9-CONTRACT: ; %bb.0: ; %entry
; GFX9-CONTRACT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-CONTRACT-NEXT: s_mov_b32 s4, 0x8000
-; GFX9-CONTRACT-NEXT: v_xor_b32_e32 v1, s4, v1
-; GFX9-CONTRACT-NEXT: v_xor_b32_e32 v2, s4, v2
+; GFX9-CONTRACT-NEXT: v_xor_b32_e32 v1, 0x8000, v1
+; GFX9-CONTRACT-NEXT: v_xor_b32_e32 v2, 0x8000, v2
; GFX9-CONTRACT-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX9-CONTRACT-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_movk_i32 s0, 0xff
-; GFX7-NEXT: s_lshr_b32 s1, s2, 2
-; GFX7-NEXT: s_and_b32 s2, s2, 3
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s1, 1
+; GFX7-NEXT: s_lshr_b32 s0, s2, 2
+; GFX7-NEXT: s_and_b32 s1, s2, 3
+; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
+; GFX7-NEXT: s_lshl_b32 s0, s1, 3
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_bfe_u32 v5, v0, 8, 8
; GFX7-NEXT: v_bfe_u32 v7, v1, 8, 8
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 24, v1
-; GFX7-NEXT: v_and_b32_e32 v4, s0, v0
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v6, s0, v1
+; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v1
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v7
; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
; GFX7-NEXT: v_or_b32_e32 v1, v1, v3
; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX7-NEXT: s_lshl_b32 s0, s2, 3
; GFX7-NEXT: v_lshrrev_b32_e32 v0, s0, v0
; GFX7-NEXT: v_readfirstlane_b32 s0, v0
; GFX7-NEXT: ; return to shader part epilog
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_movk_i32 s4, 0xff
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 2, v2
; GFX7-NEXT: v_and_b32_e32 v2, 3, v2
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
; GFX7-NEXT: v_bfe_u32 v9, v1, 8, 8
; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v1
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v8, s4, v1
+; GFX7-NEXT: v_and_b32_e32 v8, 0xff, v1
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v7
; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_movk_i32 s0, 0xff
-; GFX7-NEXT: v_mov_b32_e32 v4, 0xff
-; GFX7-NEXT: s_lshr_b32 s1, s2, 2
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s1, 1
-; GFX7-NEXT: s_and_b32 s2, s2, 3
+; GFX7-NEXT: s_lshr_b32 s0, s2, 2
+; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
+; GFX7-NEXT: s_and_b32 s1, s2, 3
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v10, v0, 8, 8
-; GFX7-NEXT: v_bfe_u32 v12, v1, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v1
-; GFX7-NEXT: v_and_b32_e32 v9, s0, v0
+; GFX7-NEXT: v_bfe_u32 v9, v0, 8, 8
+; GFX7-NEXT: v_bfe_u32 v11, v1, 8, 8
+; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v1
+; GFX7-NEXT: v_and_b32_e32 v8, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v11, s0, v1
+; GFX7-NEXT: v_and_b32_e32 v10, 0xff, v1
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_bfe_u32 v14, v2, 8, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v10, 8, v10
-; GFX7-NEXT: v_lshlrev_b32_e32 v12, 8, v12
-; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v2
-; GFX7-NEXT: v_and_b32_e32 v13, v2, v4
+; GFX7-NEXT: v_bfe_u32 v13, v2, 8, 8
+; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; GFX7-NEXT: v_lshlrev_b32_e32 v11, 8, v11
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v2
+; GFX7-NEXT: v_and_b32_e32 v12, 0xff, v2
; GFX7-NEXT: v_bfe_u32 v2, v2, 16, 8
; GFX7-NEXT: v_bfe_u32 v15, v3, 8, 8
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_lshlrev_b32_e32 v14, 8, v14
-; GFX7-NEXT: v_or_b32_e32 v9, v9, v10
-; GFX7-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v3
-; GFX7-NEXT: v_and_b32_e32 v4, v3, v4
+; GFX7-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; GFX7-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX7-NEXT: v_or_b32_e32 v9, v10, v11
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v3
+; GFX7-NEXT: v_and_b32_e32 v14, 0xff, v3
; GFX7-NEXT: v_bfe_u32 v3, v3, 16, 8
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 24, v5
-; GFX7-NEXT: v_lshlrev_b32_e32 v6, 24, v6
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v15, 8, v15
-; GFX7-NEXT: v_or_b32_e32 v11, v13, v14
-; GFX7-NEXT: v_or_b32_e32 v0, v9, v0
-; GFX7-NEXT: v_or_b32_e32 v1, v10, v1
-; GFX7-NEXT: v_lshlrev_b32_e32 v7, 24, v7
+; GFX7-NEXT: v_or_b32_e32 v10, v12, v13
+; GFX7-NEXT: v_or_b32_e32 v0, v8, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v9, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v6, 24, v6
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX7-NEXT: v_or_b32_e32 v4, v4, v15
-; GFX7-NEXT: v_or_b32_e32 v2, v11, v2
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v5
-; GFX7-NEXT: v_or_b32_e32 v1, v1, v6
-; GFX7-NEXT: v_lshlrev_b32_e32 v8, 24, v8
-; GFX7-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX7-NEXT: v_or_b32_e32 v2, v2, v7
+; GFX7-NEXT: v_or_b32_e32 v11, v14, v15
+; GFX7-NEXT: v_or_b32_e32 v2, v10, v2
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX7-NEXT: v_or_b32_e32 v1, v1, v5
+; GFX7-NEXT: v_lshlrev_b32_e32 v7, 24, v7
+; GFX7-NEXT: v_or_b32_e32 v3, v11, v3
+; GFX7-NEXT: v_or_b32_e32 v2, v2, v6
; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s1, 2
-; GFX7-NEXT: v_or_b32_e32 v3, v3, v8
+; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 2
+; GFX7-NEXT: v_or_b32_e32 v3, v3, v7
; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s1, 3
+; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 3
; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX7-NEXT: s_lshl_b32 s0, s2, 3
+; GFX7-NEXT: s_lshl_b32 s0, s1, 3
; GFX7-NEXT: v_lshrrev_b32_e32 v0, s0, v0
; GFX7-NEXT: v_readfirstlane_b32 s0, v0
; GFX7-NEXT: ; return to shader part epilog
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_dwordx4 v[3:6], v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_movk_i32 s4, 0xff
-; GFX7-NEXT: v_mov_b32_e32 v0, 0xff
; GFX7-NEXT: v_lshrrev_b32_e32 v17, 2, v2
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v17
; GFX7-NEXT: v_and_b32_e32 v2, 3, v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v11, v3, 8, 8
-; GFX7-NEXT: v_bfe_u32 v13, v4, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v3
-; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX7-NEXT: v_and_b32_e32 v10, s4, v3
+; GFX7-NEXT: v_bfe_u32 v10, v3, 8, 8
+; GFX7-NEXT: v_bfe_u32 v12, v4, 8, 8
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v3
+; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v4
+; GFX7-NEXT: v_and_b32_e32 v9, 0xff, v3
; GFX7-NEXT: v_bfe_u32 v3, v3, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v12, s4, v4
+; GFX7-NEXT: v_and_b32_e32 v11, 0xff, v4
; GFX7-NEXT: v_bfe_u32 v4, v4, 16, 8
-; GFX7-NEXT: v_bfe_u32 v15, v5, 8, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v11, 8, v11
-; GFX7-NEXT: v_lshlrev_b32_e32 v13, 8, v13
-; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v5
-; GFX7-NEXT: v_and_b32_e32 v14, v5, v0
+; GFX7-NEXT: v_bfe_u32 v14, v5, 8, 8
+; GFX7-NEXT: v_lshlrev_b32_e32 v10, 8, v10
+; GFX7-NEXT: v_lshlrev_b32_e32 v12, 8, v12
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v5
+; GFX7-NEXT: v_and_b32_e32 v13, 0xff, v5
; GFX7-NEXT: v_bfe_u32 v5, v5, 16, 8
; GFX7-NEXT: v_bfe_u32 v16, v6, 8, 8
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX7-NEXT: v_lshlrev_b32_e32 v15, 8, v15
-; GFX7-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX7-NEXT: v_or_b32_e32 v11, v12, v13
-; GFX7-NEXT: v_lshrrev_b32_e32 v9, 24, v6
-; GFX7-NEXT: v_and_b32_e32 v0, v6, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v14, 8, v14
+; GFX7-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX7-NEXT: v_or_b32_e32 v10, v11, v12
+; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v6
+; GFX7-NEXT: v_and_b32_e32 v15, 0xff, v6
; GFX7-NEXT: v_bfe_u32 v6, v6, 16, 8
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX7-NEXT: v_lshlrev_b32_e32 v7, 24, v7
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v16, 8, v16
-; GFX7-NEXT: v_or_b32_e32 v12, v14, v15
-; GFX7-NEXT: v_or_b32_e32 v3, v10, v3
-; GFX7-NEXT: v_or_b32_e32 v4, v11, v4
-; GFX7-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; GFX7-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX7-NEXT: v_or_b32_e32 v3, v9, v3
+; GFX7-NEXT: v_or_b32_e32 v4, v10, v4
+; GFX7-NEXT: v_lshlrev_b32_e32 v7, 24, v7
; GFX7-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v16
-; GFX7-NEXT: v_or_b32_e32 v5, v12, v5
-; GFX7-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX7-NEXT: v_or_b32_e32 v3, v4, v7
-; GFX7-NEXT: v_lshlrev_b32_e32 v9, 24, v9
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v6
-; GFX7-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX7-NEXT: v_or_b32_e32 v12, v15, v16
+; GFX7-NEXT: v_or_b32_e32 v5, v11, v5
+; GFX7-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; GFX7-NEXT: v_or_b32_e32 v6, v12, v6
+; GFX7-NEXT: v_or_b32_e32 v3, v5, v7
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 2, v17
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v9
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX7-NEXT: v_or_b32_e32 v4, v6, v8
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 3, v17
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v2
; GFX7-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
; GFX6-FLUSH-LABEL: v_rcp_v2f16:
; GFX6-FLUSH: ; %bb.0:
; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-FLUSH-NEXT: s_movk_i32 s6, 0x3c00
-; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, s6
+; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, 1.0
; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v2
; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5
; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6
-; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s6
+; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, 1.0
; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v0, v2
; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; GFX6-FLUSH-LABEL: v_rcp_v2f16_arcp:
; GFX6-FLUSH: ; %bb.0:
; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-FLUSH-NEXT: s_movk_i32 s6, 0x3c00
-; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, s6
+; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, 1.0
; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v2
; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5
; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6
-; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s6
+; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, 1.0
; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v0, v2
; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; GFX6-FLUSH-LABEL: v_rcp_v2f16_ulp25:
; GFX6-FLUSH: ; %bb.0:
; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-FLUSH-NEXT: s_movk_i32 s6, 0x3c00
-; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, s6
+; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, 1.0
; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v2
; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5
; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6
-; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s6
+; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, 1.0
; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v0, v2
; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, 4
; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
-; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, 15
+; GFX9-NEXT: v_add_u32_e32 v1, 4, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 15
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NEXT: scratch_store_dword v1, v3, off
+; GFX9-NEXT: scratch_store_dword v1, v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u32_e32 v0, v2, v0
+; GFX9-NEXT: v_add_u32_e32 v0, 4, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, s32
; GFX9-NEXT: v_and_b32_e32 v0, 15, v0
-; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, 15
+; GFX9-NEXT: v_add_u32_e32 v1, s32, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 15
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NEXT: scratch_store_dword v1, v3, off
+; GFX9-NEXT: scratch_store_dword v1, v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u32_e32 v0, v2, v0
+; GFX9-NEXT: v_add_u32_e32 v0, s32, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x104
; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0
-; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, 15
+; GFX9-NEXT: v_add_u32_e32 v1, 0x104, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 15
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NEXT: scratch_store_dword v1, v3, off
+; GFX9-NEXT: scratch_store_dword v1, v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u32_e32 v0, v2, v0
+; GFX9-NEXT: v_add_u32_e32 v0, 0x104, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: scratch_load_dword v1, off, s32 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: s_add_i32 vcc_hi, s32, 0x100
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, vcc_hi
+; GFX9-NEXT: s_add_i32 vcc_hi, s32, 0x100
; GFX9-NEXT: v_and_b32_e32 v0, 15, v0
-; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, 15
+; GFX9-NEXT: v_add_u32_e32 v1, vcc_hi, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 15
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NEXT: scratch_store_dword v1, v3, off
+; GFX9-NEXT: s_add_i32 vcc_hi, s32, 0x100
+; GFX9-NEXT: scratch_store_dword v1, v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u32_e32 v0, v2, v0
+; GFX9-NEXT: v_add_u32_e32 v0, vcc_hi, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x4004
; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0
-; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, 15
+; GFX9-NEXT: v_add_u32_e32 v1, 0x4004, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 15
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NEXT: scratch_store_dword v1, v3, off
+; GFX9-NEXT: scratch_store_dword v1, v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u32_e32 v0, v2, v0
+; GFX9-NEXT: v_add_u32_e32 v0, 0x4004, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: scratch_load_dword v1, off, s32 offset:4 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: s_add_i32 vcc_hi, s32, 0x4004
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
-; GFX9-NEXT: v_mov_b32_e32 v2, vcc_hi
+; GFX9-NEXT: s_add_i32 vcc_hi, s32, 0x4004
; GFX9-NEXT: v_and_b32_e32 v0, 15, v0
-; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, 15
+; GFX9-NEXT: v_add_u32_e32 v1, vcc_hi, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 15
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NEXT: scratch_store_dword v1, v3, off
+; GFX9-NEXT: s_add_i32 vcc_hi, s32, 0x4004
+; GFX9-NEXT: scratch_store_dword v1, v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u32_e32 v0, v2, v0
+; GFX9-NEXT: v_add_u32_e32 v0, vcc_hi, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b32 s2, 0x80000000
-; SI-NEXT: v_sub_f32_e32 v2, s2, v2
+; SI-NEXT: v_sub_f32_e32 v2, 0x80000000, v2
; SI-NEXT: v_sub_f32_e64 v4, s2, |v4|
; SI-NEXT: v_med3_f32 v2, v2, |v3|, v4
; SI-NEXT: s_mov_b64 s[2:3], s[10:11]
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v4, s2, v7
+; VI-NEXT: v_sub_f32_e32 v4, 0x80000000, v7
; VI-NEXT: v_sub_f32_e64 v3, s2, |v3|
; VI-NEXT: v_med3_f32 v2, v4, |v2|, v3
; VI-NEXT: flat_store_dword v[0:1], v2
; GFX9-NEXT: global_load_dword v3, v0, s[6:7] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s2, 0x80000000
-; GFX9-NEXT: v_sub_f32_e32 v1, s2, v1
+; GFX9-NEXT: v_sub_f32_e32 v1, 0x80000000, v1
; GFX9-NEXT: v_sub_f32_e64 v3, s2, |v3|
; GFX9-NEXT: v_med3_f32 v1, v1, |v2|, v3
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX8-LABEL: v_fmul_v4f16_fneg_lhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_mov_b32 s4, 0x80008000
-; GFX8-NEXT: v_xor_b32_e32 v0, s4, v0
-; GFX8-NEXT: v_xor_b32_e32 v1, s4, v1
+; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
; GFX8-NEXT: v_mul_f16_e32 v4, v0, v2
; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_mul_f16_e32 v2, v1, v3
; GFX8-LABEL: v_fmul_v4f16_fneg_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_mov_b32 s4, 0x80008000
-; GFX8-NEXT: v_xor_b32_e32 v2, s4, v2
-; GFX8-NEXT: v_xor_b32_e32 v3, s4, v3
+; GFX8-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX8-NEXT: v_xor_b32_e32 v3, 0x80008000, v3
; GFX8-NEXT: v_mul_f16_e32 v4, v0, v2
; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_mul_f16_e32 v2, v1, v3
; GFX8-LABEL: v_fmul_v6f16_fneg_lhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_mov_b32 s4, 0x80008000
-; GFX8-NEXT: v_xor_b32_e32 v0, s4, v0
-; GFX8-NEXT: v_xor_b32_e32 v1, s4, v1
-; GFX8-NEXT: v_xor_b32_e32 v2, s4, v2
+; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; GFX8-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX8-NEXT: v_mul_f16_e32 v6, v0, v3
; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_mul_f16_e32 v3, v1, v4
; GFX8-LABEL: v_fmul_v6f16_fneg_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_mov_b32 s4, 0x80008000
-; GFX8-NEXT: v_xor_b32_e32 v3, s4, v3
-; GFX8-NEXT: v_xor_b32_e32 v4, s4, v4
-; GFX8-NEXT: v_xor_b32_e32 v5, s4, v5
+; GFX8-NEXT: v_xor_b32_e32 v3, 0x80008000, v3
+; GFX8-NEXT: v_xor_b32_e32 v4, 0x80008000, v4
+; GFX8-NEXT: v_xor_b32_e32 v5, 0x80008000, v5
; GFX8-NEXT: v_mul_f16_e32 v6, v0, v3
; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_mul_f16_e32 v3, v1, v4
; GFX8-LABEL: v_fmul_v8f16_fneg_lhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_mov_b32 s4, 0x80008000
-; GFX8-NEXT: v_xor_b32_e32 v0, s4, v0
-; GFX8-NEXT: v_xor_b32_e32 v1, s4, v1
-; GFX8-NEXT: v_xor_b32_e32 v2, s4, v2
-; GFX8-NEXT: v_xor_b32_e32 v3, s4, v3
+; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; GFX8-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX8-NEXT: v_xor_b32_e32 v3, 0x80008000, v3
; GFX8-NEXT: v_mul_f16_e32 v8, v0, v4
; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_mul_f16_e32 v4, v1, v5
; GFX8-LABEL: v_fmul_v8f16_fneg_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_mov_b32 s4, 0x80008000
-; GFX8-NEXT: v_xor_b32_e32 v4, s4, v4
-; GFX8-NEXT: v_xor_b32_e32 v5, s4, v5
-; GFX8-NEXT: v_xor_b32_e32 v6, s4, v6
-; GFX8-NEXT: v_xor_b32_e32 v7, s4, v7
+; GFX8-NEXT: v_xor_b32_e32 v4, 0x80008000, v4
+; GFX8-NEXT: v_xor_b32_e32 v5, 0x80008000, v5
+; GFX8-NEXT: v_xor_b32_e32 v6, 0x80008000, v6
+; GFX8-NEXT: v_xor_b32_e32 v7, 0x80008000, v7
; GFX8-NEXT: v_mul_f16_e32 v8, v0, v4
; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_mul_f16_e32 v4, v1, v5
; GFX6-LABEL: v_pow_v2f16_fneg_lhs_rhs:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_and_b32_e32 v0, v0, v4
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX6-NEXT: s_mov_b32 s4, 0x80008000
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v4
-; GFX6-NEXT: v_xor_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX6-NEXT: v_xor_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX6-NEXT: v_log_f32_e32 v0, v0
; GFX8-LABEL: v_pow_v2f16_fneg_lhs_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_mov_b32 s4, 0x80008000
-; GFX8-NEXT: v_xor_b32_e32 v0, s4, v0
+; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX8-NEXT: v_log_f16_e32 v2, v0
; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: v_xor_b32_e32 v1, s4, v1
+; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1
; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-LABEL: v_pow_v2f16_fneg_lhs_rhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s4, 0x80008000
-; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0
+; GFX9-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX9-NEXT: v_log_f16_e32 v2, v0
; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1
+; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1
; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3
; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX6-NEXT: s_movk_i32 s3, 0x7f
; GFX6-NEXT: s_bfe_u32 s1, s1, 0x60001
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 7, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 6, v0
-; GFX6-NEXT: v_and_b32_e32 v0, s3, v0
-; GFX6-NEXT: v_and_b32_e32 v1, s3, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0
; GFX6-NEXT: v_lshr_b32_e32 v1, s1, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_and_b32 s2, s2, 0x7f
; GFX8-NEXT: s_and_b32 s1, s1, 0x7f
-; GFX8-NEXT: s_movk_i32 s3, 0x7f
+; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_lshr_b32 s1, s1, 1
; GFX8-NEXT: v_mul_lo_u32 v1, -7, v0
; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 7, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX8-NEXT: v_sub_u16_e32 v1, 6, v0
-; GFX8-NEXT: v_and_b32_e32 v0, s3, v0
-; GFX8-NEXT: v_and_b32_e32 v1, s3, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX8-NEXT: v_lshlrev_b16_e64 v0, v0, s0
; GFX8-NEXT: v_lshrrev_b16_e64 v1, v1, s1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_and_b32 s2, s2, 0x7f
; GFX9-NEXT: s_and_b32 s1, s1, 0x7f
-; GFX9-NEXT: s_movk_i32 s3, 0x7f
+; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX9-NEXT: s_lshr_b32 s1, s1, 1
; GFX9-NEXT: v_mul_lo_u32 v1, -7, v0
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 7, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT: v_sub_u16_e32 v1, 6, v0
-; GFX9-NEXT: v_and_b32_e32 v0, s3, v0
-; GFX9-NEXT: v_and_b32_e32 v1, s3, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX9-NEXT: v_lshlrev_b16_e64 v0, v0, s0
; GFX9-NEXT: v_lshrrev_b16_e64 v1, v1, s1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3
-; GFX6-NEXT: v_mov_b32_e32 v4, 0x7f
; GFX6-NEXT: v_mul_lo_u32 v3, v3, 7
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 7, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 6, v2
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v4
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, v3, v4
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7f, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, 1, v1
; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX8-NEXT: v_mul_lo_u32 v4, -7, v3
; GFX8-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v4
; GFX8-NEXT: v_mul_hi_u32 v3, v2, v3
-; GFX8-NEXT: v_mov_b32_e32 v4, 0x7f
-; GFX8-NEXT: v_and_b32_e32 v1, v1, v4
-; GFX8-NEXT: v_lshrrev_b16_e32 v1, 1, v1
; GFX8-NEXT: v_mul_lo_u32 v3, v3, 7
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 7, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_sub_u16_e32 v3, 6, v2
-; GFX8-NEXT: v_and_b32_e32 v2, v2, v4
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX8-NEXT: v_lshlrev_b16_e32 v0, v2, v0
-; GFX8-NEXT: v_and_b32_e32 v2, v3, v4
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v3
; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX9-NEXT: v_and_b32_e32 v2, 0x7f, v2
+; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v1
+; GFX9-NEXT: v_lshrrev_b16_e32 v1, 1, v1
; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: v_mul_lo_u32 v4, -7, v3
; GFX9-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, 0x7f
-; GFX9-NEXT: v_and_b32_e32 v1, v1, v4
-; GFX9-NEXT: v_lshrrev_b16_e32 v1, 1, v1
; GFX9-NEXT: v_mul_lo_u32 v3, v3, 7
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v3
; GFX9-NEXT: v_subrev_u32_e32 v3, 7, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: v_sub_u16_e32 v3, 6, v2
-; GFX9-NEXT: v_and_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v0, v2, v0
-; GFX9-NEXT: v_and_b32_e32 v2, v3, v4
+; GFX9-NEXT: v_and_b32_e32 v2, 0x7f, v3
; GFX9-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX6-NEXT: v_lshlrev_b32_e32 v2, v2, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v4, v1
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_mov_b32_e32 v2, 0xff
-; GFX6-NEXT: v_and_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX6-NEXT: v_bfe_u32 v4, v1, 16, 8
; GFX6-NEXT: v_and_b32_e32 v6, 7, v6
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
-; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v6, v4
; GFX6-NEXT: v_xor_b32_e32 v6, -1, v8
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: v_and_b32_e32 v4, 7, v8
; GFX6-NEXT: v_and_b32_e32 v6, 7, v6
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 25, v1
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v4, v4, v5
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v6, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX6-NEXT: v_or_b32_e32 v1, v4, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
+; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_lshrrev_b16_e32 v1, v6, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_mov_b32_e32 v1, 8
-; GFX8-NEXT: s_movk_i32 s4, 0xff
; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v2, s4, v4
+; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_and_or_b32 v1, v2, s4, v1
-; GFX9-NEXT: v_and_b32_e32 v2, s4, v4
-; GFX9-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX6-NEXT: s_and_b32 s2, s2, 0xffffff
-; GFX6-NEXT: s_mov_b32 s3, 0xffffff
+; GFX6-NEXT: s_bfe_u32 s1, s1, 0x170001
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: s_bfe_u32 s1, s1, 0x170001
; GFX6-NEXT: v_mul_lo_u32 v1, v1, v0
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 23, v0
-; GFX6-NEXT: v_and_b32_e32 v0, s3, v0
-; GFX6-NEXT: v_and_b32_e32 v1, s3, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0
; GFX6-NEXT: v_lshr_b32_e32 v1, s1, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX8-NEXT: s_and_b32 s2, s2, 0xffffff
-; GFX8-NEXT: s_mov_b32 s3, 0xffffff
+; GFX8-NEXT: s_bfe_u32 s1, s1, 0x170001
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x170001
; GFX8-NEXT: v_mul_lo_u32 v1, v1, v0
; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, 23, v0
-; GFX8-NEXT: v_and_b32_e32 v0, s3, v0
-; GFX8-NEXT: v_and_b32_e32 v1, s3, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX8-NEXT: v_lshlrev_b32_e64 v0, v0, s0
; GFX8-NEXT: v_lshrrev_b32_e64 v1, v1, s1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX9-NEXT: s_and_b32 s2, s2, 0xffffff
-; GFX9-NEXT: s_mov_b32 s3, 0xffffff
+; GFX9-NEXT: s_bfe_u32 s1, s1, 0x170001
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x170001
; GFX9-NEXT: v_mul_lo_u32 v1, v1, v0
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT: v_sub_u32_e32 v1, 23, v0
-; GFX9-NEXT: v_and_b32_e32 v1, s3, v1
-; GFX9-NEXT: v_and_b32_e32 v0, s3, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GFX9-NEXT: v_lshrrev_b32_e64 v1, v1, s1
; GFX9-NEXT: v_lshl_or_b32 v0, s0, v0, v1
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3
-; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffff
; GFX6-NEXT: v_mul_lo_u32 v3, v3, 24
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v2
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v4
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, v3, v4
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v4
; GFX8-NEXT: v_mul_hi_u32 v3, v2, v3
-; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffff
; GFX8-NEXT: v_mul_lo_u32 v3, v3, 24
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v2
-; GFX8-NEXT: v_and_b32_e32 v2, v2, v4
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v2, v0
-; GFX8-NEXT: v_and_b32_e32 v2, v3, v4
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, 0xffffff
; GFX9-NEXT: v_mul_lo_u32 v3, v3, 24
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v3
; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: v_sub_u32_e32 v3, 23, v2
-; GFX9-NEXT: v_and_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_and_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffffff, v3
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v1, v3, v1
; GFX9-NEXT: v_lshl_or_b32 v0, v0, v2, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_lshr_b32 s6, s0, 16
; GFX6-NEXT: s_lshr_b32 s7, s0, 24
-; GFX6-NEXT: s_and_b32 s10, s0, 0xff
+; GFX6-NEXT: s_and_b32 s9, s0, 0xff
; GFX6-NEXT: s_bfe_u32 s0, s0, 0x80008
; GFX6-NEXT: s_lshl_b32 s0, s0, 8
; GFX6-NEXT: s_and_b32 s6, s6, 0xff
-; GFX6-NEXT: s_or_b32 s0, s10, s0
+; GFX6-NEXT: s_or_b32 s0, s9, s0
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: s_lshr_b32 s8, s1, 8
; GFX6-NEXT: s_or_b32 s1, s1, s6
; GFX6-NEXT: s_lshr_b32 s6, s2, 16
; GFX6-NEXT: s_lshr_b32 s7, s2, 24
-; GFX6-NEXT: s_and_b32 s10, s2, 0xff
+; GFX6-NEXT: s_and_b32 s9, s2, 0xff
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x80008
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v0
; GFX6-NEXT: s_lshl_b32 s2, s2, 8
; GFX6-NEXT: s_and_b32 s6, s6, 0xff
-; GFX6-NEXT: s_or_b32 s2, s10, s2
+; GFX6-NEXT: s_or_b32 s2, s9, s2
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX6-NEXT: s_lshr_b32 s8, s3, 8
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX6-NEXT: s_or_b32 s3, s3, s6
; GFX6-NEXT: s_lshr_b32 s6, s4, 16
; GFX6-NEXT: s_lshr_b32 s7, s4, 24
-; GFX6-NEXT: s_and_b32 s10, s4, 0xff
+; GFX6-NEXT: s_and_b32 s9, s4, 0xff
; GFX6-NEXT: s_bfe_u32 s4, s4, 0x80008
; GFX6-NEXT: s_lshl_b32 s4, s4, 8
; GFX6-NEXT: s_and_b32 s6, s6, 0xff
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
-; GFX6-NEXT: s_or_b32 s4, s10, s4
+; GFX6-NEXT: s_or_b32 s4, s9, s4
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
-; GFX6-NEXT: s_mov_b32 s6, 0xffffff
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GFX6-NEXT: v_mul_lo_u32 v1, v1, 24
-; GFX6-NEXT: v_and_b32_e32 v0, s6, v0
; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0
; GFX6-NEXT: s_lshr_b32 s0, s2, 1
-; GFX6-NEXT: v_and_b32_e32 v2, s6, v3
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v3
; GFX6-NEXT: v_lshr_b32_e32 v2, s0, v2
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffff
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v1
-; GFX6-NEXT: v_and_b32_e32 v1, v1, v4
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX6-NEXT: s_lshr_b32 s0, s3, 1
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v4
-; GFX6-NEXT: s_movk_i32 s9, 0xff
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX6-NEXT: v_lshl_b32_e32 v1, s1, v1
; GFX6-NEXT: v_lshr_b32_e32 v2, s0, v2
; GFX6-NEXT: v_bfe_u32 v3, v0, 8, 8
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s9, v0
+; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX6-NEXT: v_bfe_u32 v0, v0, 16, 8
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, s9, v1
+; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_bfe_u32 v2, v1, 8, 8
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v1
; GFX8-NEXT: v_mul_hi_u32 v1, s5, v1
-; GFX8-NEXT: s_mov_b32 s6, 0xffffff
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
-; GFX8-NEXT: v_and_b32_e32 v0, s6, v0
; GFX8-NEXT: v_lshlrev_b32_e64 v0, v0, s0
; GFX8-NEXT: s_lshr_b32 s0, s2, 1
-; GFX8-NEXT: v_and_b32_e32 v2, s6, v3
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v3
; GFX8-NEXT: v_lshrrev_b32_e64 v2, v2, s0
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffff
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v1
-; GFX8-NEXT: v_and_b32_e32 v1, v1, v4
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX8-NEXT: s_lshr_b32 s0, s3, 1
-; GFX8-NEXT: v_and_b32_e32 v2, v2, v4
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_lshlrev_b32_e64 v1, v1, s1
; GFX8-NEXT: v_lshrrev_b32_e64 v2, v2, s0
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX9-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX9-NEXT: s_mov_b32 s7, 0xffffff
-; GFX9-NEXT: v_sub_u32_e32 v3, 23, v0
+; GFX9-NEXT: v_sub_u32_e32 v2, 23, v0
; GFX9-NEXT: s_lshr_b32 s2, s2, 1
-; GFX9-NEXT: v_and_b32_e32 v3, s7, v3
-; GFX9-NEXT: v_and_b32_e32 v0, s7, v0
-; GFX9-NEXT: v_lshrrev_b32_e64 v3, v3, s2
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX9-NEXT: v_lshrrev_b32_e64 v2, v2, s2
; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, s0, v0, v3
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, s0, v0, v2
+; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX9-NEXT: v_mov_b32_e32 v2, 0xffffff
-; GFX9-NEXT: v_sub_u32_e32 v3, 23, v1
-; GFX9-NEXT: v_and_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_sub_u32_e32 v2, 23, v1
; GFX9-NEXT: s_lshr_b32 s0, s3, 1
-; GFX9-NEXT: v_and_b32_e32 v2, v3, v2
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX9-NEXT: v_lshrrev_b32_e64 v2, v2, s0
; GFX9-NEXT: s_mov_b32 s6, 8
; GFX9-NEXT: v_lshl_or_b32 v1, s1, v1, v2
-; GFX9-NEXT: s_movk_i32 s0, 0xff
; GFX9-NEXT: s_mov_b32 s8, 16
+; GFX9-NEXT: s_movk_i32 s0, 0xff
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX9-NEXT: v_and_b32_e32 v3, s0, v1
+; GFX9-NEXT: v_and_b32_e32 v3, 0xff, v1
; GFX9-NEXT: v_and_or_b32 v2, v0, s0, v2
; GFX9-NEXT: v_lshlrev_b32_sdwa v0, s8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX6-NEXT: v_mov_b32_e32 v7, 0xffffffe8
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v9, v9
; GFX6-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX6-NEXT: v_bfe_u32 v2, v2, 1, 23
; GFX6-NEXT: v_mul_lo_u32 v8, v7, v6
; GFX6-NEXT: v_mul_hi_u32 v8, v6, v8
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v8, v9
; GFX6-NEXT: v_mul_hi_u32 v6, v4, v6
-; GFX6-NEXT: v_mov_b32_e32 v9, 0xffffff
-; GFX6-NEXT: v_and_b32_e32 v5, v5, v9
-; GFX6-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX6-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v9
; GFX6-NEXT: v_cvt_u32_f32_e32 v8, v8
; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX6-NEXT: v_mul_lo_u32 v7, v7, v8
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GFX6-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 23, v4
-; GFX6-NEXT: v_and_b32_e32 v4, v4, v9
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v4, v0
-; GFX6-NEXT: v_and_b32_e32 v4, v6, v9
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v6
; GFX6-NEXT: v_mul_lo_u32 v6, v7, 24
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 23, v2
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v9
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v2, v1
; GFX6-NEXT: v_bfe_u32 v2, v3, 1, 23
-; GFX6-NEXT: v_and_b32_e32 v3, v4, v9
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffffff, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v3, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX8-NEXT: v_mov_b32_e32 v7, 0xffffffe8
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v9, v9
; GFX8-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX8-NEXT: v_bfe_u32 v2, v2, 1, 23
; GFX8-NEXT: v_mul_lo_u32 v8, v7, v6
; GFX8-NEXT: v_mul_hi_u32 v8, v6, v8
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v8, v9
; GFX8-NEXT: v_mul_hi_u32 v6, v4, v6
-; GFX8-NEXT: v_mov_b32_e32 v9, 0xffffff
-; GFX8-NEXT: v_and_b32_e32 v5, v5, v9
-; GFX8-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX8-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v9
; GFX8-NEXT: v_cvt_u32_f32_e32 v8, v8
; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX8-NEXT: v_mul_lo_u32 v7, v7, v8
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v8, v7
; GFX8-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 23, v4
-; GFX8-NEXT: v_and_b32_e32 v4, v4, v9
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v4, v0
-; GFX8-NEXT: v_and_b32_e32 v4, v6, v9
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v6
; GFX8-NEXT: v_mul_lo_u32 v6, v7, 24
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 23, v2
-; GFX8-NEXT: v_and_b32_e32 v2, v2, v9
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v1, v2, v1
; GFX8-NEXT: v_bfe_u32 v2, v3, 1, 23
-; GFX8-NEXT: v_and_b32_e32 v3, v4, v9
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v3, v2
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: v_mul_f32_e32 v9, 0x4f7ffffe, v9
; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v9
; GFX9-NEXT: v_mul_lo_u32 v8, v7, v6
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX9-NEXT: v_bfe_u32 v2, v2, 1, 23
-; GFX9-NEXT: v_bfe_u32 v3, v3, 1, 23
; GFX9-NEXT: v_mul_lo_u32 v7, v7, v9
; GFX9-NEXT: v_mul_hi_u32 v8, v6, v8
+; GFX9-NEXT: v_bfe_u32 v3, v3, 1, 23
; GFX9-NEXT: v_mul_hi_u32 v7, v9, v7
; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
; GFX9-NEXT: v_mul_hi_u32 v6, v4, v6
-; GFX9-NEXT: v_mov_b32_e32 v8, 0xffffff
-; GFX9-NEXT: v_and_b32_e32 v5, v5, v8
+; GFX9-NEXT: v_add_u32_e32 v7, v9, v7
; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX9-NEXT: v_sub_u32_e32 v4, v4, v6
; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX9-NEXT: v_add_u32_e32 v6, v9, v7
-; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6
+; GFX9-NEXT: v_mul_hi_u32 v6, v5, v7
; GFX9-NEXT: v_sub_u32_e32 v7, 23, v4
-; GFX9-NEXT: v_and_b32_e32 v7, v7, v8
-; GFX9-NEXT: v_and_b32_e32 v4, v4, v8
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffffff, v7
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX9-NEXT: v_lshrrev_b32_e32 v2, v7, v2
; GFX9-NEXT: v_lshl_or_b32 v0, v0, v4, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_sub_u32_e32 v4, 23, v2
-; GFX9-NEXT: v_and_b32_e32 v4, v4, v8
-; GFX9-NEXT: v_and_b32_e32 v2, v2, v8
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v3, v4, v3
; GFX9-NEXT: v_lshl_or_b32 v1, v1, v2, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_v2i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s4, 0xf000f
-; GFX9-NEXT: v_and_b32_e32 v3, s4, v2
+; GFX9-NEXT: v_and_b32_e32 v3, 0xf000f, v2
; GFX9-NEXT: v_xor_b32_e32 v2, -1, v2
-; GFX9-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX9-NEXT: v_and_b32_e32 v2, 0xf000f, v2
; GFX9-NEXT: v_pk_lshrrev_b16 v1, 1, v1 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_lshlrev_b16 v0, v3, v0
; GFX9-NEXT: v_pk_lshrrev_b16 v1, v2, v1
;
; GFX9-LABEL: v_fshl_v2i16_ssv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_mov_b32 s2, 0xf000f
-; GFX9-NEXT: v_and_b32_e32 v1, s2, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0xf000f, v0
; GFX9-NEXT: v_pk_lshlrev_b16 v1, v1, s0
; GFX9-NEXT: s_lshr_b32 s0, s1, 16
; GFX9-NEXT: s_and_b32 s1, s1, 0xffff
; GFX9-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX9-NEXT: s_lshr_b32 s1, s1, 0x10001
; GFX9-NEXT: s_lshr_b32 s0, s0, 1
-; GFX9-NEXT: v_and_b32_e32 v0, s2, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xf000f, v0
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s1, s0
; GFX9-NEXT: v_pk_lshrrev_b16 v0, v0, s0
; GFX9-NEXT: v_or_b32_e32 v0, v1, v0
; GFX9-LABEL: v_fshl_v4i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s4, 0xf000f
-; GFX9-NEXT: v_and_b32_e32 v6, s4, v4
+; GFX9-NEXT: v_and_b32_e32 v6, 0xf000f, v4
; GFX9-NEXT: v_xor_b32_e32 v4, -1, v4
-; GFX9-NEXT: v_and_b32_e32 v4, s4, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xf000f, v4
; GFX9-NEXT: v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_lshlrev_b16 v0, v6, v0
; GFX9-NEXT: v_pk_lshrrev_b16 v2, v4, v2
; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX9-NEXT: v_and_b32_e32 v2, s4, v5
+; GFX9-NEXT: v_and_b32_e32 v2, 0xf000f, v5
; GFX9-NEXT: v_xor_b32_e32 v4, -1, v5
-; GFX9-NEXT: v_and_b32_e32 v4, s4, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xf000f, v4
; GFX9-NEXT: v_pk_lshlrev_b16 v1, v2, v1
; GFX9-NEXT: v_pk_lshrrev_b16 v2, 1, v3 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_lshrrev_b16 v2, v4, v2
; GFX6-LABEL: v_fshl_i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_movk_i32 s4, 0x7f
-; GFX6-NEXT: v_and_b32_e32 v14, s4, v8
+; GFX6-NEXT: v_and_b32_e32 v14, 0x7f, v8
; GFX6-NEXT: v_xor_b32_e32 v8, -1, v8
-; GFX6-NEXT: v_and_b32_e32 v15, s4, v8
+; GFX6-NEXT: v_and_b32_e32 v15, 0x7f, v8
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 64, v14
; GFX6-NEXT: v_subrev_i32_e32 v16, vcc, 64, v14
; GFX6-NEXT: v_lshr_b64 v[8:9], v[0:1], v8
; GFX8-LABEL: v_fshl_i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s4, 0x7f
-; GFX8-NEXT: v_and_b32_e32 v14, s4, v8
+; GFX8-NEXT: v_and_b32_e32 v14, 0x7f, v8
; GFX8-NEXT: v_xor_b32_e32 v8, -1, v8
-; GFX8-NEXT: v_and_b32_e32 v15, s4, v8
+; GFX8-NEXT: v_and_b32_e32 v15, 0x7f, v8
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 64, v14
; GFX8-NEXT: v_subrev_u32_e32 v16, vcc, 64, v14
; GFX8-NEXT: v_lshrrev_b64 v[8:9], v8, v[0:1]
; GFX9-LABEL: v_fshl_i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_movk_i32 s4, 0x7f
-; GFX9-NEXT: v_and_b32_e32 v14, s4, v8
+; GFX9-NEXT: v_and_b32_e32 v14, 0x7f, v8
; GFX9-NEXT: v_xor_b32_e32 v8, -1, v8
-; GFX9-NEXT: v_and_b32_e32 v15, s4, v8
+; GFX9-NEXT: v_and_b32_e32 v15, 0x7f, v8
; GFX9-NEXT: v_sub_u32_e32 v8, 64, v14
; GFX9-NEXT: v_subrev_u32_e32 v16, 64, v14
; GFX9-NEXT: v_lshrrev_b64 v[8:9], v8, v[0:1]
define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, i128 %amt) {
; GFX6-LABEL: v_fshl_i128_ssv:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_movk_i32 s8, 0x7f
-; GFX6-NEXT: v_and_b32_e32 v6, s8, v0
+; GFX6-NEXT: v_and_b32_e32 v6, 0x7f, v0
; GFX6-NEXT: v_xor_b32_e32 v0, -1, v0
-; GFX6-NEXT: v_and_b32_e32 v7, s8, v0
+; GFX6-NEXT: v_and_b32_e32 v7, 0x7f, v0
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, 64, v6
; GFX6-NEXT: v_lshr_b64 v[0:1], s[0:1], v0
; GFX6-NEXT: v_lshl_b64 v[2:3], s[2:3], v6
;
; GFX8-LABEL: v_fshl_i128_ssv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_movk_i32 s8, 0x7f
-; GFX8-NEXT: v_and_b32_e32 v6, s8, v0
+; GFX8-NEXT: v_and_b32_e32 v6, 0x7f, v0
; GFX8-NEXT: v_xor_b32_e32 v0, -1, v0
-; GFX8-NEXT: v_and_b32_e32 v7, s8, v0
+; GFX8-NEXT: v_and_b32_e32 v7, 0x7f, v0
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, 64, v6
; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1]
; GFX8-NEXT: v_lshlrev_b64 v[2:3], v6, s[2:3]
;
; GFX9-LABEL: v_fshl_i128_ssv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_movk_i32 s8, 0x7f
-; GFX9-NEXT: v_and_b32_e32 v6, s8, v0
+; GFX9-NEXT: v_and_b32_e32 v6, 0x7f, v0
; GFX9-NEXT: v_xor_b32_e32 v0, -1, v0
-; GFX9-NEXT: v_and_b32_e32 v7, s8, v0
+; GFX9-NEXT: v_and_b32_e32 v7, 0x7f, v0
; GFX9-NEXT: v_sub_u32_e32 v0, 64, v6
; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1]
; GFX9-NEXT: v_lshlrev_b64 v[2:3], v6, s[2:3]
; GFX6-LABEL: v_fshl_v2i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_movk_i32 s6, 0x7f
-; GFX6-NEXT: v_and_b32_e32 v23, s6, v16
+; GFX6-NEXT: v_and_b32_e32 v23, 0x7f, v16
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, 64, v23
; GFX6-NEXT: v_lshr_b64 v[17:18], v[0:1], v17
; GFX6-NEXT: v_lshl_b64 v[21:22], v[2:3], v23
; GFX6-NEXT: v_xor_b32_e32 v16, -1, v16
; GFX6-NEXT: v_or_b32_e32 v21, v17, v21
; GFX6-NEXT: v_lshlrev_b32_e32 v17, 31, v10
-; GFX6-NEXT: v_and_b32_e32 v24, s6, v16
+; GFX6-NEXT: v_and_b32_e32 v24, 0x7f, v16
; GFX6-NEXT: v_lshr_b64 v[10:11], v[10:11], 1
; GFX6-NEXT: v_or_b32_e32 v9, v9, v17
; GFX6-NEXT: v_sub_i32_e32 v16, vcc, 64, v24
; GFX6-NEXT: v_or_b32_e32 v1, v18, v3
; GFX6-NEXT: v_or_b32_e32 v2, v17, v8
; GFX6-NEXT: v_or_b32_e32 v3, v16, v9
-; GFX6-NEXT: v_and_b32_e32 v16, s6, v20
+; GFX6-NEXT: v_and_b32_e32 v16, 0x7f, v20
; GFX6-NEXT: v_xor_b32_e32 v8, -1, v20
-; GFX6-NEXT: v_and_b32_e32 v17, s6, v8
+; GFX6-NEXT: v_and_b32_e32 v17, 0x7f, v8
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 64, v16
; GFX6-NEXT: v_lshr_b64 v[8:9], v[4:5], v8
; GFX6-NEXT: v_lshl_b64 v[10:11], v[6:7], v16
; GFX8-LABEL: v_fshl_v2i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s6, 0x7f
-; GFX8-NEXT: v_and_b32_e32 v23, s6, v16
+; GFX8-NEXT: v_and_b32_e32 v23, 0x7f, v16
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, 64, v23
; GFX8-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1]
; GFX8-NEXT: v_lshlrev_b64 v[21:22], v23, v[2:3]
; GFX8-NEXT: v_xor_b32_e32 v16, -1, v16
; GFX8-NEXT: v_or_b32_e32 v21, v17, v21
; GFX8-NEXT: v_lshlrev_b32_e32 v17, 31, v10
-; GFX8-NEXT: v_and_b32_e32 v24, s6, v16
+; GFX8-NEXT: v_and_b32_e32 v24, 0x7f, v16
; GFX8-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
; GFX8-NEXT: v_or_b32_e32 v9, v9, v17
; GFX8-NEXT: v_sub_u32_e32 v16, vcc, 64, v24
; GFX8-NEXT: v_or_b32_e32 v1, v18, v3
; GFX8-NEXT: v_or_b32_e32 v2, v17, v8
; GFX8-NEXT: v_or_b32_e32 v3, v16, v9
-; GFX8-NEXT: v_and_b32_e32 v16, s6, v20
+; GFX8-NEXT: v_and_b32_e32 v16, 0x7f, v20
; GFX8-NEXT: v_xor_b32_e32 v8, -1, v20
-; GFX8-NEXT: v_and_b32_e32 v17, s6, v8
+; GFX8-NEXT: v_and_b32_e32 v17, 0x7f, v8
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 64, v16
; GFX8-NEXT: v_lshrrev_b64 v[8:9], v8, v[4:5]
; GFX8-NEXT: v_lshlrev_b64 v[10:11], v16, v[6:7]
; GFX9-LABEL: v_fshl_v2i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_movk_i32 s6, 0x7f
-; GFX9-NEXT: v_and_b32_e32 v23, s6, v16
+; GFX9-NEXT: v_and_b32_e32 v23, 0x7f, v16
; GFX9-NEXT: v_sub_u32_e32 v17, 64, v23
; GFX9-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1]
; GFX9-NEXT: v_lshlrev_b64 v[21:22], v23, v[2:3]
; GFX9-NEXT: v_xor_b32_e32 v16, -1, v16
; GFX9-NEXT: v_or_b32_e32 v21, v17, v21
; GFX9-NEXT: v_lshlrev_b32_e32 v17, 31, v10
-; GFX9-NEXT: v_and_b32_e32 v24, s6, v16
+; GFX9-NEXT: v_and_b32_e32 v24, 0x7f, v16
; GFX9-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
; GFX9-NEXT: v_or_b32_e32 v9, v9, v17
; GFX9-NEXT: v_sub_u32_e32 v16, 64, v24
; GFX9-NEXT: v_or_b32_e32 v1, v18, v3
; GFX9-NEXT: v_or_b32_e32 v2, v17, v8
; GFX9-NEXT: v_or_b32_e32 v3, v16, v9
-; GFX9-NEXT: v_and_b32_e32 v16, s6, v20
+; GFX9-NEXT: v_and_b32_e32 v16, 0x7f, v20
; GFX9-NEXT: v_xor_b32_e32 v8, -1, v20
-; GFX9-NEXT: v_and_b32_e32 v17, s6, v8
+; GFX9-NEXT: v_and_b32_e32 v17, 0x7f, v8
; GFX9-NEXT: v_sub_u32_e32 v8, 64, v16
; GFX9-NEXT: v_lshrrev_b64 v[8:9], v8, v[4:5]
; GFX9-NEXT: v_lshlrev_b64 v[10:11], v16, v[6:7]
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX6-NEXT: s_movk_i32 s3, 0x7f
; GFX6-NEXT: s_lshl_b32 s0, s0, 1
+; GFX6-NEXT: s_and_b32 s1, s1, 0x7f
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: s_and_b32 s1, s1, 0x7f
; GFX6-NEXT: v_mul_lo_u32 v1, -7, v0
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 7, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 6, v0
-; GFX6-NEXT: v_and_b32_e32 v0, s3, v0
-; GFX6-NEXT: v_and_b32_e32 v1, s3, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX6-NEXT: v_lshl_b32_e32 v1, s0, v1
; GFX6-NEXT: v_lshr_b32_e32 v0, s1, v0
; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX8-NEXT: s_movk_i32 s3, 0x7f
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
+; GFX8-NEXT: s_and_b32 s1, s1, 0x7f
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: s_and_b32 s1, s1, 0x7f
; GFX8-NEXT: v_mul_lo_u32 v1, -7, v0
; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 7, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX8-NEXT: v_sub_u16_e32 v1, 6, v0
-; GFX8-NEXT: v_and_b32_e32 v0, s3, v0
-; GFX8-NEXT: v_and_b32_e32 v1, s3, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX8-NEXT: v_lshlrev_b16_e64 v1, v1, s0
; GFX8-NEXT: v_lshrrev_b16_e64 v0, v0, s1
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX9-NEXT: s_movk_i32 s3, 0x7f
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
+; GFX9-NEXT: s_and_b32 s1, s1, 0x7f
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_and_b32 s1, s1, 0x7f
; GFX9-NEXT: v_mul_lo_u32 v1, -7, v0
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 7, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT: v_sub_u16_e32 v1, 6, v0
-; GFX9-NEXT: v_and_b32_e32 v0, s3, v0
-; GFX9-NEXT: v_and_b32_e32 v1, s3, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX9-NEXT: v_lshlrev_b16_e64 v1, v1, s0
; GFX9-NEXT: v_lshrrev_b16_e64 v0, v0, s1
; GFX9-NEXT: v_or_b32_e32 v0, v1, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX6-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX6-NEXT: v_mul_lo_u32 v4, -7, v3
; GFX6-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3
-; GFX6-NEXT: v_mov_b32_e32 v4, 0x7f
-; GFX6-NEXT: v_and_b32_e32 v1, v1, v4
; GFX6-NEXT: v_mul_lo_u32 v3, v3, 7
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 7, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 6, v2
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v4
-; GFX6-NEXT: v_and_b32_e32 v3, v3, v4
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7f, v2
+; GFX6-NEXT: v_and_b32_e32 v3, 0x7f, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX8-NEXT: v_mul_lo_u32 v4, -7, v3
; GFX8-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v4
; GFX8-NEXT: v_mul_hi_u32 v3, v2, v3
-; GFX8-NEXT: v_mov_b32_e32 v4, 0x7f
-; GFX8-NEXT: v_and_b32_e32 v1, v1, v4
; GFX8-NEXT: v_mul_lo_u32 v3, v3, 7
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 7, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_sub_u16_e32 v3, 6, v2
-; GFX8-NEXT: v_and_b32_e32 v2, v2, v4
-; GFX8-NEXT: v_and_b32_e32 v3, v3, v4
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v2
+; GFX8-NEXT: v_and_b32_e32 v3, 0x7f, v3
; GFX8-NEXT: v_lshlrev_b16_e32 v0, v3, v0
; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX9-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 1, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: v_mul_lo_u32 v4, -7, v3
; GFX9-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, 0x7f
-; GFX9-NEXT: v_and_b32_e32 v1, v1, v4
; GFX9-NEXT: v_mul_lo_u32 v3, v3, 7
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v3
; GFX9-NEXT: v_subrev_u32_e32 v3, 7, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: v_sub_u16_e32 v3, 6, v2
-; GFX9-NEXT: v_and_b32_e32 v2, v2, v4
-; GFX9-NEXT: v_and_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_and_b32_e32 v2, 0x7f, v2
+; GFX9-NEXT: v_and_b32_e32 v3, 0x7f, v3
; GFX9-NEXT: v_lshlrev_b16_e32 v0, v3, v0
; GFX9-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v0
; GFX6-NEXT: v_and_b32_e32 v2, 7, v2
-; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v5, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_and_b32_e32 v2, 7, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, v4, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX6-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 24, v0
; GFX6-NEXT: v_and_b32_e32 v2, 7, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX6-NEXT: v_and_b32_e32 v11, 0xff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v10, v10, v11
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v10
-; GFX6-NEXT: v_and_b32_e32 v10, 7, v7
+; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, v10, v2
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 7, v7
; GFX6-NEXT: v_xor_b32_e32 v7, -1, v7
; GFX6-NEXT: v_and_b32_e32 v7, 7, v7
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 1, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v3, v7, v3
; GFX6-NEXT: v_bfe_u32 v7, v1, 8, 8
-; GFX6-NEXT: v_lshrrev_b32_e32 v7, v10, v7
-; GFX6-NEXT: v_or_b32_e32 v3, v3, v7
-; GFX6-NEXT: v_and_b32_e32 v7, 7, v8
-; GFX6-NEXT: v_xor_b32_e32 v8, -1, v8
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, v2, v7
+; GFX6-NEXT: v_xor_b32_e32 v7, -1, v8
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 24, v1
-; GFX6-NEXT: v_and_b32_e32 v8, 7, v8
+; GFX6-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX6-NEXT: v_and_b32_e32 v3, 7, v8
+; GFX6-NEXT: v_and_b32_e32 v7, 7, v7
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 1, v4
; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX6-NEXT: v_mov_b32_e32 v2, 0xff
-; GFX6-NEXT: v_lshlrev_b32_e32 v4, v8, v4
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, v7, v1
-; GFX6-NEXT: v_xor_b32_e32 v7, -1, v9
+; GFX6-NEXT: v_lshlrev_b32_e32 v4, v7, v4
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, v3, v1
; GFX6-NEXT: v_or_b32_e32 v1, v4, v1
-; GFX6-NEXT: v_and_b32_e32 v4, 7, v9
-; GFX6-NEXT: v_and_b32_e32 v7, 7, v7
+; GFX6-NEXT: v_xor_b32_e32 v4, -1, v9
+; GFX6-NEXT: v_and_b32_e32 v3, 7, v9
+; GFX6-NEXT: v_and_b32_e32 v4, 7, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 1, v5
-; GFX6-NEXT: v_and_b32_e32 v3, v3, v2
-; GFX6-NEXT: v_lshlrev_b32_e32 v5, v7, v5
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, v4, v6
-; GFX6-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX6-NEXT: v_and_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v3
+; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v4, v4, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, v3, v6
+; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX6-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, v4, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_mov_b32_e32 v1, 8
-; GFX8-NEXT: s_movk_i32 s4, 0xff
; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v2, s4, v4
+; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_and_or_b32 v1, v2, s4, v1
-; GFX9-NEXT: v_and_b32_e32 v2, s4, v4
-; GFX9-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX6-NEXT: s_and_b32 s2, s2, 0xffffff
-; GFX6-NEXT: s_mov_b32 s3, 0xffffff
+; GFX6-NEXT: s_lshl_b32 s0, s0, 1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: s_lshl_b32 s0, s0, 1
; GFX6-NEXT: s_and_b32 s1, s1, 0xffffff
; GFX6-NEXT: v_mul_lo_u32 v1, v1, v0
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 23, v0
-; GFX6-NEXT: v_and_b32_e32 v0, s3, v0
-; GFX6-NEXT: v_and_b32_e32 v1, s3, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX6-NEXT: v_lshl_b32_e32 v1, s0, v1
; GFX6-NEXT: v_lshr_b32_e32 v0, s1, v0
; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX8-NEXT: s_and_b32 s2, s2, 0xffffff
-; GFX8-NEXT: s_mov_b32 s3, 0xffffff
+; GFX8-NEXT: s_lshl_b32 s0, s0, 1
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: s_lshl_b32 s0, s0, 1
; GFX8-NEXT: s_and_b32 s1, s1, 0xffffff
; GFX8-NEXT: v_mul_lo_u32 v1, v1, v0
; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, 23, v0
-; GFX8-NEXT: v_and_b32_e32 v0, s3, v0
-; GFX8-NEXT: v_and_b32_e32 v1, s3, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX8-NEXT: v_lshlrev_b32_e64 v1, v1, s0
; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s1
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX9-NEXT: s_and_b32 s2, s2, 0xffffff
-; GFX9-NEXT: s_mov_b32 s3, 0xffffff
+; GFX9-NEXT: s_and_b32 s1, s1, 0xffffff
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_and_b32 s1, s1, 0xffffff
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
; GFX9-NEXT: v_mul_lo_u32 v1, v1, v0
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT: v_sub_u32_e32 v1, 23, v0
-; GFX9-NEXT: v_and_b32_e32 v0, s3, v0
-; GFX9-NEXT: v_and_b32_e32 v1, s3, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s1
; GFX9-NEXT: v_lshl_or_b32 v0, s0, v1, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX6-NEXT: v_mul_lo_u32 v4, v4, v3
; GFX6-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3
-; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffff
-; GFX6-NEXT: v_and_b32_e32 v1, v1, v4
; GFX6-NEXT: v_mul_lo_u32 v3, v3, 24
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v2
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v4
-; GFX6-NEXT: v_and_b32_e32 v3, v3, v4
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX8-NEXT: v_mul_lo_u32 v4, v4, v3
; GFX8-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v4
; GFX8-NEXT: v_mul_hi_u32 v3, v2, v3
-; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffff
-; GFX8-NEXT: v_and_b32_e32 v1, v1, v4
; GFX8-NEXT: v_mul_lo_u32 v3, v3, 24
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v2
-; GFX8-NEXT: v_and_b32_e32 v2, v2, v4
-; GFX8-NEXT: v_and_b32_e32 v3, v3, v4
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX9-NEXT: v_mov_b32_e32 v4, 0xffffffe8
; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX9-NEXT: v_mul_lo_u32 v4, v4, v3
; GFX9-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, 0xffffff
-; GFX9-NEXT: v_and_b32_e32 v1, v1, v4
; GFX9-NEXT: v_mul_lo_u32 v3, v3, 24
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v3
; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: v_sub_u32_e32 v3, 23, v2
-; GFX9-NEXT: v_and_b32_e32 v2, v2, v4
-; GFX9-NEXT: v_and_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX9-NEXT: v_lshl_or_b32 v0, v0, v3, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX6-NEXT: s_lshr_b32 s8, s1, 8
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: s_and_b32 s10, s0, 0xff
+; GFX6-NEXT: s_and_b32 s9, s0, 0xff
; GFX6-NEXT: s_bfe_u32 s0, s0, 0x80008
; GFX6-NEXT: s_and_b32 s1, s1, 0xff
; GFX6-NEXT: s_lshl_b32 s0, s0, 8
; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: v_mov_b32_e32 v1, 0xffffffe8
-; GFX6-NEXT: s_or_b32 s0, s10, s0
+; GFX6-NEXT: s_or_b32 s0, s9, s0
; GFX6-NEXT: s_or_b32 s1, s7, s1
; GFX6-NEXT: s_and_b32 s7, s8, 0xff
; GFX6-NEXT: s_lshr_b32 s8, s2, 16
-; GFX6-NEXT: s_lshr_b32 s10, s2, 24
-; GFX6-NEXT: s_and_b32 s12, s2, 0xff
+; GFX6-NEXT: s_lshr_b32 s9, s2, 24
+; GFX6-NEXT: s_and_b32 s11, s2, 0xff
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x80008
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v0
; GFX6-NEXT: s_lshl_b32 s2, s2, 8
; GFX6-NEXT: s_and_b32 s8, s8, 0xff
-; GFX6-NEXT: s_or_b32 s2, s12, s2
+; GFX6-NEXT: s_or_b32 s2, s11, s2
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
-; GFX6-NEXT: s_lshr_b32 s11, s3, 8
+; GFX6-NEXT: s_lshr_b32 s10, s3, 8
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
; GFX6-NEXT: s_and_b32 s3, s3, 0xff
; GFX6-NEXT: s_or_b32 s2, s2, s8
; GFX6-NEXT: s_lshl_b32 s3, s3, 8
-; GFX6-NEXT: s_and_b32 s8, s11, 0xff
+; GFX6-NEXT: s_and_b32 s8, s10, 0xff
; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
-; GFX6-NEXT: s_or_b32 s3, s10, s3
+; GFX6-NEXT: s_or_b32 s3, s9, s3
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX6-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
; GFX6-NEXT: s_or_b32 s3, s3, s8
; GFX6-NEXT: s_lshr_b32 s8, s4, 16
-; GFX6-NEXT: s_lshr_b32 s10, s4, 24
-; GFX6-NEXT: s_and_b32 s12, s4, 0xff
+; GFX6-NEXT: s_lshr_b32 s9, s4, 24
+; GFX6-NEXT: s_and_b32 s11, s4, 0xff
; GFX6-NEXT: s_bfe_u32 s4, s4, 0x80008
; GFX6-NEXT: s_lshl_b32 s4, s4, 8
; GFX6-NEXT: s_and_b32 s8, s8, 0xff
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
-; GFX6-NEXT: s_or_b32 s4, s12, s4
+; GFX6-NEXT: s_or_b32 s4, s11, s4
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX6-NEXT: s_lshr_b32 s11, s5, 8
+; GFX6-NEXT: s_lshr_b32 s10, s5, 8
; GFX6-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX6-NEXT: s_and_b32 s5, s5, 0xff
; GFX6-NEXT: v_mul_lo_u32 v1, v1, v2
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX6-NEXT: v_mul_hi_u32 v1, v2, v1
-; GFX6-NEXT: s_and_b32 s8, s11, 0xff
+; GFX6-NEXT: s_and_b32 s8, s10, 0xff
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT: s_or_b32 s5, s10, s5
+; GFX6-NEXT: s_or_b32 s5, s9, s5
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v0
; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX6-NEXT: v_mul_lo_u32 v1, v1, 24
-; GFX6-NEXT: s_mov_b32 s8, 0xffffff
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v0
; GFX6-NEXT: s_lshl_b32 s4, s6, 17
; GFX6-NEXT: s_lshl_b32 s0, s0, 1
; GFX6-NEXT: s_or_b32 s0, s4, s0
-; GFX6-NEXT: v_and_b32_e32 v2, s8, v3
-; GFX6-NEXT: v_and_b32_e32 v0, s8, v0
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v3
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GFX6-NEXT: v_lshl_b32_e32 v2, s0, v2
; GFX6-NEXT: v_lshr_b32_e32 v0, s2, v0
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
; GFX6-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX6-NEXT: s_bfe_u32 s7, s7, 0x100000
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffff
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v1
; GFX6-NEXT: s_lshl_b32 s0, s7, 17
; GFX6-NEXT: s_lshl_b32 s1, s1, 1
; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v4
-; GFX6-NEXT: v_and_b32_e32 v1, v1, v4
-; GFX6-NEXT: s_movk_i32 s9, 0xff
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX6-NEXT: v_lshl_b32_e32 v2, s0, v2
; GFX6-NEXT: v_lshr_b32_e32 v1, s3, v1
; GFX6-NEXT: v_bfe_u32 v3, v0, 8, 8
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_and_b32_e32 v2, s9, v0
+; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX6-NEXT: v_bfe_u32 v0, v0, 16, 8
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, s9, v1
+; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_bfe_u32 v2, v1, 8, 8
; GFX8-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX8-NEXT: s_mov_b32 s8, 0xffffff
-; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v0
+; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX8-NEXT: s_lshl_b32 s4, s6, 17
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
; GFX8-NEXT: s_or_b32 s0, s4, s0
-; GFX8-NEXT: v_and_b32_e32 v2, s8, v3
-; GFX8-NEXT: v_and_b32_e32 v0, s8, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v3
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GFX8-NEXT: v_lshlrev_b32_e64 v2, v2, s0
; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s2
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_bfe_u32 s7, s7, 0x100000
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffff
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v1
; GFX8-NEXT: s_lshl_b32 s0, s7, 17
; GFX8-NEXT: s_lshl_b32 s1, s1, 1
; GFX8-NEXT: s_or_b32 s0, s0, s1
-; GFX8-NEXT: v_and_b32_e32 v2, v2, v4
-; GFX8-NEXT: v_and_b32_e32 v1, v1, v4
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX8-NEXT: v_lshlrev_b32_e64 v2, v2, s0
; GFX8-NEXT: v_lshrrev_b32_e64 v1, v1, s3
; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX9-NEXT: s_bfe_u32 s7, s7, 0x100000
-; GFX9-NEXT: s_mov_b32 s10, 0xffffff
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_sub_u32_e32 v3, 23, v0
; GFX9-NEXT: s_lshl_b32 s4, s7, 17
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
-; GFX9-NEXT: v_and_b32_e32 v0, s10, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GFX9-NEXT: s_or_b32 s0, s4, s0
-; GFX9-NEXT: v_and_b32_e32 v3, s10, v3
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v3
; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s2
; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, s0, v3, v0
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, s0, v2, v0
+; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX9-NEXT: s_bfe_u32 s9, s9, 0x100000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0xffffff
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX9-NEXT: v_sub_u32_e32 v3, 23, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_sub_u32_e32 v2, 23, v1
; GFX9-NEXT: s_lshl_b32 s0, s9, 17
; GFX9-NEXT: s_lshl_b32 s1, s1, 1
-; GFX9-NEXT: v_and_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: v_and_b32_e32 v3, v3, v2
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX9-NEXT: v_lshrrev_b32_e64 v1, v1, s3
; GFX9-NEXT: s_mov_b32 s6, 8
-; GFX9-NEXT: v_lshl_or_b32 v1, s0, v3, v1
-; GFX9-NEXT: s_movk_i32 s0, 0xff
+; GFX9-NEXT: v_lshl_or_b32 v1, s0, v2, v1
; GFX9-NEXT: s_mov_b32 s8, 16
+; GFX9-NEXT: s_movk_i32 s0, 0xff
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX9-NEXT: v_and_b32_e32 v3, s0, v1
+; GFX9-NEXT: v_and_b32_e32 v3, 0xff, v1
; GFX9-NEXT: v_and_or_b32 v2, v0, s0, v2
; GFX9-NEXT: v_lshlrev_b32_sdwa v0, s8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
; GFX6-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 1, v1
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX6-NEXT: v_mul_lo_u32 v8, v7, v6
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 1, v1
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX6-NEXT: v_mul_hi_u32 v8, v6, v8
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; GFX6-NEXT: v_mul_hi_u32 v6, v4, v6
; GFX6-NEXT: v_rcp_iflag_f32_e32 v8, v9
-; GFX6-NEXT: v_mov_b32_e32 v9, 0xffffff
-; GFX6-NEXT: v_and_b32_e32 v5, v5, v9
; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX6-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
; GFX6-NEXT: v_cvt_u32_f32_e32 v8, v8
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v9
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v7, v8
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, 23, v4
-; GFX6-NEXT: v_and_b32_e32 v7, v7, v9
+; GFX6-NEXT: v_and_b32_e32 v7, 0xffffff, v7
; GFX6-NEXT: v_mul_hi_u32 v6, v8, v6
-; GFX6-NEXT: v_and_b32_e32 v4, v4, v9
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v7, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; GFX6-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_and_b32_e32 v3, v3, v9
; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v5, v6
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 24, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 23, v2
-; GFX6-NEXT: v_and_b32_e32 v4, v4, v9
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v9
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v4, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v2, v3
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
; GFX8-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_mul_lo_u32 v8, v7, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX8-NEXT: v_mul_hi_u32 v8, v6, v8
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8
; GFX8-NEXT: v_mul_hi_u32 v6, v4, v6
; GFX8-NEXT: v_rcp_iflag_f32_e32 v8, v9
-; GFX8-NEXT: v_mov_b32_e32 v9, 0xffffff
-; GFX8-NEXT: v_and_b32_e32 v5, v5, v9
; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX8-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
; GFX8-NEXT: v_cvt_u32_f32_e32 v8, v8
-; GFX8-NEXT: v_and_b32_e32 v2, v2, v9
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v6
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-NEXT: v_mul_lo_u32 v6, v7, v8
; GFX8-NEXT: v_sub_u32_e32 v7, vcc, 23, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v7, v9
+; GFX8-NEXT: v_and_b32_e32 v7, 0xffffff, v7
; GFX8-NEXT: v_mul_hi_u32 v6, v8, v6
-; GFX8-NEXT: v_and_b32_e32 v4, v4, v9
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v7, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v8, v6
; GFX8-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_and_b32_e32 v3, v3, v9
; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v5, v6
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 24, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 23, v2
-; GFX8-NEXT: v_and_b32_e32 v4, v4, v9
-; GFX8-NEXT: v_and_b32_e32 v2, v2, v9
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v1, v4, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v2, v3
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v9
; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX9-NEXT: v_mul_lo_u32 v8, v7, v6
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX9-NEXT: v_mul_lo_u32 v7, v7, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v1
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v6, v8
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX9-NEXT: v_mul_hi_u32 v7, v9, v7
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
; GFX9-NEXT: v_mul_hi_u32 v6, v4, v6
-; GFX9-NEXT: v_mov_b32_e32 v8, 0xffffff
-; GFX9-NEXT: v_and_b32_e32 v5, v5, v8
; GFX9-NEXT: v_add_u32_e32 v7, v9, v7
-; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX9-NEXT: v_mul_hi_u32 v7, v5, v7
-; GFX9-NEXT: v_and_b32_e32 v2, v2, v8
-; GFX9-NEXT: v_and_b32_e32 v3, v3, v8
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v1
+; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
; GFX9-NEXT: v_sub_u32_e32 v4, v4, v6
; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT: v_sub_u32_e32 v6, 23, v4
-; GFX9-NEXT: v_and_b32_e32 v4, v4, v8
-; GFX9-NEXT: v_and_b32_e32 v6, v6, v8
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffffff, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX9-NEXT: v_lshl_or_b32 v0, v0, v6, v2
; GFX9-NEXT: v_sub_u32_e32 v2, v5, v7
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_sub_u32_e32 v4, 23, v2
-; GFX9-NEXT: v_and_b32_e32 v2, v2, v8
-; GFX9-NEXT: v_and_b32_e32 v4, v4, v8
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v2, v2, v3
; GFX9-NEXT: v_lshl_or_b32 v1, v1, v4, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_v2i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s4, 0xf000f
-; GFX9-NEXT: v_and_b32_e32 v3, s4, v2
+; GFX9-NEXT: v_and_b32_e32 v3, 0xf000f, v2
; GFX9-NEXT: v_xor_b32_e32 v2, -1, v2
-; GFX9-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX9-NEXT: v_and_b32_e32 v2, 0xf000f, v2
; GFX9-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_lshlrev_b16 v0, v2, v0
; GFX9-NEXT: v_pk_lshrrev_b16 v1, v3, v1
;
; GFX9-LABEL: v_fshr_v2i16_ssv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_mov_b32 s2, 0xf000f
-; GFX9-NEXT: v_and_b32_e32 v1, s2, v0
-; GFX9-NEXT: v_xor_b32_e32 v0, -1, v0
-; GFX9-NEXT: v_and_b32_e32 v0, s2, v0
; GFX9-NEXT: s_lshr_b32 s2, s0, 16
+; GFX9-NEXT: v_and_b32_e32 v1, 0xf000f, v0
+; GFX9-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX9-NEXT: s_lshl_b32 s0, s0, 0x10001
; GFX9-NEXT: s_lshl_b32 s2, s2, 1
+; GFX9-NEXT: v_and_b32_e32 v0, 0xf000f, v0
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX9-NEXT: v_pk_lshlrev_b16 v0, v0, s0
; GFX9-NEXT: v_pk_lshrrev_b16 v1, v1, s1
; GFX6-LABEL: v_fshr_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v12, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX6-NEXT: v_and_b32_e32 v8, v8, v12
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX6-NEXT: v_or_b32_e32 v8, v9, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v9, 16, v11
-; GFX6-NEXT: v_and_b32_e32 v10, v10, v12
+; GFX6-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX6-NEXT: v_or_b32_e32 v9, v9, v10
; GFX6-NEXT: s_bfe_u32 s4, 1, 0x100000
; GFX6-NEXT: v_bfe_u32 v10, v4, 1, 15
; GFX9-LABEL: v_fshr_v4i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s4, 0xf000f
-; GFX9-NEXT: v_and_b32_e32 v6, s4, v4
+; GFX9-NEXT: v_and_b32_e32 v6, 0xf000f, v4
; GFX9-NEXT: v_xor_b32_e32 v4, -1, v4
-; GFX9-NEXT: v_and_b32_e32 v4, s4, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xf000f, v4
; GFX9-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_lshlrev_b16 v0, v4, v0
; GFX9-NEXT: v_pk_lshrrev_b16 v2, v6, v2
; GFX9-NEXT: v_xor_b32_e32 v4, -1, v5
; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX9-NEXT: v_and_b32_e32 v2, s4, v5
-; GFX9-NEXT: v_and_b32_e32 v4, s4, v4
+; GFX9-NEXT: v_and_b32_e32 v2, 0xf000f, v5
+; GFX9-NEXT: v_and_b32_e32 v4, 0xf000f, v4
; GFX9-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_lshlrev_b16 v1, v4, v1
; GFX9-NEXT: v_pk_lshrrev_b16 v2, v2, v3
; GFX6-LABEL: v_fshr_i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_movk_i32 s4, 0x7f
-; GFX6-NEXT: v_and_b32_e32 v14, s4, v8
+; GFX6-NEXT: v_and_b32_e32 v14, 0x7f, v8
; GFX6-NEXT: v_xor_b32_e32 v8, -1, v8
; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
-; GFX6-NEXT: v_and_b32_e32 v15, s4, v8
+; GFX6-NEXT: v_and_b32_e32 v15, 0x7f, v8
; GFX6-NEXT: v_lshl_b64 v[8:9], v[0:1], 1
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 31, v1
; GFX6-NEXT: v_or_b32_e32 v2, v2, v0
; GFX8-LABEL: v_fshr_i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s4, 0x7f
-; GFX8-NEXT: v_and_b32_e32 v14, s4, v8
+; GFX8-NEXT: v_and_b32_e32 v14, 0x7f, v8
; GFX8-NEXT: v_xor_b32_e32 v8, -1, v8
; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX8-NEXT: v_and_b32_e32 v15, s4, v8
+; GFX8-NEXT: v_and_b32_e32 v15, 0x7f, v8
; GFX8-NEXT: v_lshlrev_b64 v[8:9], 1, v[0:1]
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 31, v1
; GFX8-NEXT: v_or_b32_e32 v2, v2, v0
; GFX9-LABEL: v_fshr_i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_movk_i32 s4, 0x7f
-; GFX9-NEXT: v_and_b32_e32 v14, s4, v8
+; GFX9-NEXT: v_and_b32_e32 v14, 0x7f, v8
; GFX9-NEXT: v_xor_b32_e32 v8, -1, v8
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX9-NEXT: v_and_b32_e32 v15, s4, v8
+; GFX9-NEXT: v_and_b32_e32 v15, 0x7f, v8
; GFX9-NEXT: v_lshlrev_b64 v[8:9], 1, v[0:1]
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 31, v1
; GFX9-NEXT: v_or_b32_e32 v2, v2, v0
define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, i128 %amt) {
; GFX6-LABEL: v_fshr_i128_ssv:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_movk_i32 s8, 0x7f
-; GFX6-NEXT: v_and_b32_e32 v6, s8, v0
+; GFX6-NEXT: v_and_b32_e32 v6, 0x7f, v0
; GFX6-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX6-NEXT: s_mov_b32 s9, 0
-; GFX6-NEXT: v_and_b32_e32 v7, s8, v0
+; GFX6-NEXT: v_and_b32_e32 v7, 0x7f, v0
; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX6-NEXT: s_lshr_b32 s8, s1, 31
; GFX6-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
;
; GFX8-LABEL: v_fshr_i128_ssv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_movk_i32 s8, 0x7f
-; GFX8-NEXT: v_and_b32_e32 v6, s8, v0
+; GFX8-NEXT: v_and_b32_e32 v6, 0x7f, v0
; GFX8-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX8-NEXT: s_mov_b32 s9, 0
-; GFX8-NEXT: v_and_b32_e32 v7, s8, v0
+; GFX8-NEXT: v_and_b32_e32 v7, 0x7f, v0
; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX8-NEXT: s_lshr_b32 s8, s1, 31
; GFX8-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
;
; GFX9-LABEL: v_fshr_i128_ssv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_movk_i32 s8, 0x7f
-; GFX9-NEXT: v_and_b32_e32 v6, s8, v0
+; GFX9-NEXT: v_and_b32_e32 v6, 0x7f, v0
; GFX9-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX9-NEXT: s_mov_b32 s9, 0
-; GFX9-NEXT: v_and_b32_e32 v7, s8, v0
+; GFX9-NEXT: v_and_b32_e32 v7, 0x7f, v0
; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX9-NEXT: s_lshr_b32 s8, s1, 31
; GFX9-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
; GFX6-LABEL: v_fshr_v2i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_movk_i32 s6, 0x7f
; GFX6-NEXT: v_xor_b32_e32 v17, -1, v16
; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
-; GFX6-NEXT: v_and_b32_e32 v23, s6, v17
+; GFX6-NEXT: v_and_b32_e32 v23, 0x7f, v17
; GFX6-NEXT: v_lshrrev_b32_e32 v17, 31, v1
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GFX6-NEXT: v_or_b32_e32 v2, v2, v17
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, 64, v23
; GFX6-NEXT: v_lshr_b64 v[17:18], v[0:1], v17
; GFX6-NEXT: v_lshl_b64 v[21:22], v[2:3], v23
-; GFX6-NEXT: v_and_b32_e32 v24, s6, v16
+; GFX6-NEXT: v_and_b32_e32 v24, 0x7f, v16
; GFX6-NEXT: v_sub_i32_e32 v16, vcc, 64, v24
; GFX6-NEXT: v_or_b32_e32 v21, v17, v21
; GFX6-NEXT: v_or_b32_e32 v22, v18, v22
; GFX6-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
; GFX6-NEXT: v_or_b32_e32 v1, v18, v3
; GFX6-NEXT: v_or_b32_e32 v3, v16, v9
-; GFX6-NEXT: v_and_b32_e32 v17, s6, v8
+; GFX6-NEXT: v_and_b32_e32 v17, 0x7f, v8
; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], 1
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 31, v5
; GFX6-NEXT: v_or_b32_e32 v6, v6, v4
; GFX6-NEXT: v_lshl_b64 v[4:5], v[8:9], v17
; GFX6-NEXT: v_lshl_b64 v[8:9], v[8:9], v18
; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17
-; GFX6-NEXT: v_and_b32_e32 v16, s6, v20
+; GFX6-NEXT: v_and_b32_e32 v16, 0x7f, v20
; GFX6-NEXT: v_cndmask_b32_e32 v18, 0, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v19, 0, v5, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v10, vcc
; GFX8-LABEL: v_fshr_v2i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s6, 0x7f
; GFX8-NEXT: v_xor_b32_e32 v17, -1, v16
; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX8-NEXT: v_and_b32_e32 v23, s6, v17
+; GFX8-NEXT: v_and_b32_e32 v23, 0x7f, v17
; GFX8-NEXT: v_lshrrev_b32_e32 v17, 31, v1
; GFX8-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX8-NEXT: v_or_b32_e32 v2, v2, v17
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, 64, v23
; GFX8-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1]
; GFX8-NEXT: v_lshlrev_b64 v[21:22], v23, v[2:3]
-; GFX8-NEXT: v_and_b32_e32 v24, s6, v16
+; GFX8-NEXT: v_and_b32_e32 v24, 0x7f, v16
; GFX8-NEXT: v_sub_u32_e32 v16, vcc, 64, v24
; GFX8-NEXT: v_or_b32_e32 v21, v17, v21
; GFX8-NEXT: v_or_b32_e32 v22, v18, v22
; GFX8-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
; GFX8-NEXT: v_or_b32_e32 v1, v18, v3
; GFX8-NEXT: v_or_b32_e32 v3, v16, v9
-; GFX8-NEXT: v_and_b32_e32 v17, s6, v8
+; GFX8-NEXT: v_and_b32_e32 v17, 0x7f, v8
; GFX8-NEXT: v_lshlrev_b64 v[8:9], 1, v[4:5]
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 31, v5
; GFX8-NEXT: v_or_b32_e32 v6, v6, v4
; GFX8-NEXT: v_lshlrev_b64 v[4:5], v17, v[8:9]
; GFX8-NEXT: v_lshlrev_b64 v[8:9], v18, v[8:9]
; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17
-; GFX8-NEXT: v_and_b32_e32 v16, s6, v20
+; GFX8-NEXT: v_and_b32_e32 v16, 0x7f, v20
; GFX8-NEXT: v_cndmask_b32_e32 v18, 0, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v19, 0, v5, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v10, vcc
; GFX9-LABEL: v_fshr_v2i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_movk_i32 s6, 0x7f
; GFX9-NEXT: v_xor_b32_e32 v17, -1, v16
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX9-NEXT: v_and_b32_e32 v23, s6, v17
+; GFX9-NEXT: v_and_b32_e32 v23, 0x7f, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 31, v1
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX9-NEXT: v_or_b32_e32 v2, v2, v17
; GFX9-NEXT: v_sub_u32_e32 v17, 64, v23
; GFX9-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1]
; GFX9-NEXT: v_lshlrev_b64 v[21:22], v23, v[2:3]
-; GFX9-NEXT: v_and_b32_e32 v24, s6, v16
+; GFX9-NEXT: v_and_b32_e32 v24, 0x7f, v16
; GFX9-NEXT: v_sub_u32_e32 v16, 64, v24
; GFX9-NEXT: v_or_b32_e32 v21, v17, v21
; GFX9-NEXT: v_or_b32_e32 v22, v18, v22
; GFX9-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
; GFX9-NEXT: v_or_b32_e32 v1, v18, v3
; GFX9-NEXT: v_or_b32_e32 v3, v16, v9
-; GFX9-NEXT: v_and_b32_e32 v17, s6, v8
+; GFX9-NEXT: v_and_b32_e32 v17, 0x7f, v8
; GFX9-NEXT: v_lshlrev_b64 v[8:9], 1, v[4:5]
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v5
; GFX9-NEXT: v_or_b32_e32 v6, v6, v4
; GFX9-NEXT: v_lshlrev_b64 v[4:5], v17, v[8:9]
; GFX9-NEXT: v_lshlrev_b64 v[8:9], v18, v[8:9]
; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17
-; GFX9-NEXT: v_and_b32_e32 v16, s6, v20
+; GFX9-NEXT: v_and_b32_e32 v16, 0x7f, v20
; GFX9-NEXT: v_cndmask_b32_e32 v18, 0, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v19, 0, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v10, vcc
; The offset to the dynamic shared memory array should be aligned on the
; maximal one.
; CHECK-LABEL: {{^}}dynamic_shared_array_4:
-; CHECK: v_mov_b32_e32 [[DYNLDS:v[0-9]+]], 0x48
; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
-; CHECK: v_add_u32_e32 {{v[0-9]+}}, [[DYNLDS]], [[IDX]]
+; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0x48, [[IDX]]
define amdgpu_kernel void @dynamic_shared_array_4(i32 %idx) {
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%vidx = add i32 %tid.x, %idx
; Honor the explicit alignment from the specified variable.
; CHECK-LABEL: {{^}}dynamic_shared_array_5:
-; CHECK: v_mov_b32_e32 [[DYNLDS:v[0-9]+]], 0x44
; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
-; CHECK: v_add_u32_e32 {{v[0-9]+}}, [[DYNLDS]], [[IDX]]
+; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0x44, [[IDX]]
define amdgpu_kernel void @dynamic_shared_array_5(i32 %idx) {
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%vidx = add i32 %tid.x, %idx
; Honor the explicit alignment from the specified variable.
; CHECK-LABEL: {{^}}dynamic_shared_array_6:
-; CHECK: v_mov_b32_e32 [[DYNLDS:v[0-9]+]], 0x50
; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
-; CHECK: v_add_u32_e32 {{v[0-9]+}}, [[DYNLDS]], [[IDX]]
+; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0x50, [[IDX]]
define amdgpu_kernel void @dynamic_shared_array_6(i32 %idx) {
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%vidx = add i32 %tid.x, %idx
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dword s0, s[2:3], 0x0
; GFX7-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX7-NEXT: s_mov_b32 s1, 0xffff
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
-; GFX7-NEXT: v_and_b32_e32 v0, s1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v2, v1, v0
-; GFX7-NEXT: v_lshl_b32_e32 v0, s1, v1
+; GFX7-NEXT: v_lshl_b32_e32 v0, 0xffff, v1
; GFX7-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_and_b32_e32 v3, s0, v0
; GFX7-LABEL: insertelement_v_v2i16_v_v:
; GFX7: ; %bb.0:
; GFX7-NEXT: flat_load_dword v0, v[0:1]
-; GFX7-NEXT: s_mov_b32 s0, 0xffff
; GFX7-NEXT: v_and_b32_e32 v1, 1, v3
-; GFX7-NEXT: v_and_b32_e32 v2, s0, v2
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX7-NEXT: v_lshlrev_b32_e32 v2, v1, v2
-; GFX7-NEXT: v_lshl_b32_e32 v1, s0, v1
+; GFX7-NEXT: v_lshl_b32_e32 v1, 0xffff, v1
; GFX7-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_and_b32_e32 v3, v0, v1
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 1, v1
; GFX7-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX7-NEXT: s_mov_b32 s2, 0xffff
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
-; GFX7-NEXT: v_and_b32_e32 v0, s2, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v3, s0
; GFX7-NEXT: v_mov_b32_e32 v4, s1
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v0, v1, v0
-; GFX7-NEXT: v_lshl_b32_e32 v1, s2, v1
+; GFX7-NEXT: v_lshl_b32_e32 v1, 0xffff, v1
; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX7-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX7-NEXT: v_and_b32_e32 v1, v3, v1
; GFX7-LABEL: insertelement_v_v4i16_v_v:
; GFX7: ; %bb.0:
; GFX7-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX7-NEXT: s_mov_b32 s0, 0xffff
; GFX7-NEXT: v_lshrrev_b32_e32 v6, 1, v3
; GFX7-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX7-NEXT: v_and_b32_e32 v2, s0, v2
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 4, v3
; GFX7-NEXT: v_lshlrev_b32_e32 v2, v3, v2
-; GFX7-NEXT: v_lshl_b32_e32 v3, s0, v3
+; GFX7-NEXT: v_lshl_b32_e32 v3, 0xffff, v3
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
; GFX7-NEXT: v_xor_b32_e32 v3, -1, v3
; GFX7-NEXT: v_mov_b32_e32 v4, 0
; GFX7-NEXT: v_lshrrev_b32_e32 v4, 1, v1
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
; GFX7-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX7-NEXT: s_mov_b32 s8, 0xffff
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v4
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: v_mov_b32_e32 v5, s6
; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
-; GFX7-NEXT: v_and_b32_e32 v0, s8, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_mov_b32_e32 v6, s7
; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v0, v1, v0
-; GFX7-NEXT: v_lshl_b32_e32 v1, s8, v1
+; GFX7-NEXT: v_lshl_b32_e32 v1, 0xffff, v1
; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[2:3]
; GFX7-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX7-NEXT: v_and_b32_e32 v1, v2, v1
; GFX7-NEXT: s_mov_b32 s11, 0xf000
; GFX7-NEXT: s_mov_b64 s[8:9], 0
; GFX7-NEXT: buffer_load_dwordx4 v[4:7], v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_mov_b32 s0, 0xffff
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 1, v3
; GFX7-NEXT: v_and_b32_e32 v1, 1, v3
-; GFX7-NEXT: v_and_b32_e32 v2, s0, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, v1, v2
-; GFX7-NEXT: v_lshl_b32_e32 v1, s0, v1
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, v1, v2
+; GFX7-NEXT: v_lshl_b32_e32 v1, 0xffff, v1
; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
; GFX7-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[4:5]
; GFX7-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v8
; GFX7-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX7-NEXT: s_mov_b32 s20, 0xffff
; GFX7-NEXT: v_mov_b32_e32 v9, s18
; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v7, s[6:7]
; GFX7-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v8
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
-; GFX7-NEXT: v_and_b32_e32 v0, s20, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_mov_b32_e32 v10, s19
; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v9, s[8:9]
; GFX7-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v8
; GFX7-NEXT: v_lshlrev_b32_e32 v0, v1, v0
-; GFX7-NEXT: v_lshl_b32_e32 v1, s20, v1
+; GFX7-NEXT: v_lshl_b32_e32 v1, 0xffff, v1
; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v10, s[10:11]
; GFX7-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX7-NEXT: v_and_b32_e32 v1, v2, v1
; GFX7-NEXT: s_mov_b64 s[16:17], 0
; GFX7-NEXT: buffer_load_dwordx4 v[4:7], v[0:1], s[16:19], 0 addr64
; GFX7-NEXT: buffer_load_dwordx4 v[8:11], v[0:1], s[16:19], 0 addr64 offset:16
-; GFX7-NEXT: s_mov_b32 s0, 0xffff
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 1, v3
-; GFX7-NEXT: v_and_b32_e32 v1, 1, v3
-; GFX7-NEXT: v_and_b32_e32 v2, s0, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, v1, v2
-; GFX7-NEXT: v_lshl_b32_e32 v1, s0, v1
+; GFX7-NEXT: v_and_b32_e32 v1, 1, v3
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0
; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v0
; GFX7-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v0
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX7-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, v1, v2
+; GFX7-NEXT: v_lshl_b32_e32 v1, 0xffff, v1
; GFX7-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v0
; GFX7-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX7-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
+; GFX7-NEXT: v_mov_b32_e32 v1, s4
; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s5, 0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0xff
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v3, 8, v0
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s5, 1
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX7-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX7-NEXT: v_and_b32_e32 v1, v2, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0xff
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v3, 8, v0
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s3, 1
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX7-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX7-NEXT: v_and_b32_e32 v1, v2, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-NEXT: buffer_store_short v0, off, s[4:7], 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_load_ushort v1, off, s[0:3], 0
; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s4, 0
-; GFX7-NEXT: v_mov_b32_e32 v2, 0xff
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 8, v1
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
-; GFX7-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX7-NEXT: v_and_b32_e32 v1, v1, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_load_ushort v1, off, s[0:3], 0
-; GFX7-NEXT: v_mov_b32_e32 v3, s4
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX7-NEXT: v_mov_b32_e32 v2, 0xff
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 8, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc
-; GFX7-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX7-NEXT: v_and_b32_e32 v1, v1, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_load_ushort v2, off, s[0:3], 0
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX7-NEXT: v_mov_b32_e32 v3, 0xff
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 8, v2
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 8, v2
; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; GFX7-NEXT: v_and_b32_e32 v0, v0, v3
-; GFX7-NEXT: v_and_b32_e32 v1, v2, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: v_mov_b32_e32 v3, s2
+; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
-; GFX7-NEXT: v_mov_b32_e32 v1, 0xff
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 8, v0
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 8, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
-; GFX7-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX7-NEXT: v_and_b32_e32 v1, v2, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-NEXT: buffer_store_short v0, off, s[4:7], 0
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64
; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0xff
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v3, 8, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX7-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX7-NEXT: v_and_b32_e32 v1, v2, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-NEXT: buffer_store_short v0, off, s[4:7], 0
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[0:3], 0 addr64
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
-; GFX7-NEXT: v_mov_b32_e32 v1, 0xff
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 8, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX7-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX7-NEXT: v_and_b32_e32 v1, v2, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX9-LABEL: insertelement_s_v4i8_v_s:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-NEXT: s_movk_i32 s5, 0xff
-; GFX9-NEXT: v_and_b32_e32 v0, s5, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX9-NEXT: s_mov_b32 s1, 8
; GFX9-NEXT: s_mov_b32 s2, 16
+; GFX9-NEXT: s_movk_i32 s5, 0xff
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_bfe_u32 s7, s0, 0x80008
; GFX9-NEXT: s_lshr_b32 s3, s0, 24
; GFX7-LABEL: insertelement_s_v4i8_v_s:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX7-NEXT: s_movk_i32 s2, 0xff
-; GFX7-NEXT: v_and_b32_e32 v0, s2, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_bfe_u32 s5, s0, 0x80008
+; GFX7-NEXT: s_bfe_u32 s3, s0, 0x80008
; GFX7-NEXT: s_lshr_b32 s1, s0, 24
-; GFX7-NEXT: s_and_b32 s3, s0, 0xff
-; GFX7-NEXT: s_lshl_b32 s5, s5, 8
+; GFX7-NEXT: s_and_b32 s2, s0, 0xff
+; GFX7-NEXT: s_lshl_b32 s3, s3, 8
; GFX7-NEXT: s_bfe_u32 s0, s0, 0x80010
-; GFX7-NEXT: s_or_b32 s3, s3, s5
+; GFX7-NEXT: s_or_b32 s2, s2, s3
; GFX7-NEXT: s_lshl_b32 s0, s0, 16
-; GFX7-NEXT: s_or_b32 s0, s3, s0
+; GFX7-NEXT: s_or_b32 s0, s2, s0
; GFX7-NEXT: s_lshl_b32 s1, s1, 24
; GFX7-NEXT: s_or_b32 s0, s0, s1
; GFX7-NEXT: s_and_b32 s1, s4, 3
; GFX7-NEXT: v_or_b32_e32 v0, s0, v0
; GFX7-NEXT: v_bfe_u32 v3, v0, 8, 8
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v2, s2, v0
+; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
; GFX7-NEXT: v_or_b32_e32 v2, v2, v3
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dword s0, s[2:3], 0x0
; GFX7-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX7-NEXT: s_movk_i32 s2, 0xff
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_bfe_u32 s5, s0, 0x80008
+; GFX7-NEXT: s_bfe_u32 s3, s0, 0x80008
; GFX7-NEXT: s_lshr_b32 s1, s0, 24
-; GFX7-NEXT: s_and_b32 s3, s0, 0xff
-; GFX7-NEXT: s_lshl_b32 s5, s5, 8
+; GFX7-NEXT: s_and_b32 s2, s0, 0xff
+; GFX7-NEXT: s_lshl_b32 s3, s3, 8
; GFX7-NEXT: s_bfe_u32 s0, s0, 0x80010
-; GFX7-NEXT: s_or_b32 s3, s3, s5
+; GFX7-NEXT: s_or_b32 s2, s2, s3
; GFX7-NEXT: s_lshl_b32 s0, s0, 16
-; GFX7-NEXT: s_or_b32 s0, s3, s0
+; GFX7-NEXT: s_or_b32 s0, s2, s0
; GFX7-NEXT: s_lshl_b32 s1, s1, 24
; GFX7-NEXT: s_or_b32 s0, s0, s1
; GFX7-NEXT: s_and_b32 s1, s4, 0xff
; GFX7-NEXT: v_lshl_b32_e32 v1, s1, v0
-; GFX7-NEXT: v_lshl_b32_e32 v0, s2, v0
+; GFX7-NEXT: v_lshl_b32_e32 v0, 0xff, v0
; GFX7-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX7-NEXT: v_and_b32_e32 v0, s0, v0
; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-NEXT: v_bfe_u32 v3, v0, 8, 8
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v2, s2, v0
+; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
; GFX7-NEXT: v_or_b32_e32 v2, v2, v3
; GFX7-LABEL: insertelement_s_v4i8_v_v:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX7-NEXT: s_movk_i32 s2, 0xff
; GFX7-NEXT: v_and_b32_e32 v1, 3, v1
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v1
-; GFX7-NEXT: v_and_b32_e32 v0, s2, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_bfe_u32 s4, s0, 0x80008
+; GFX7-NEXT: s_bfe_u32 s3, s0, 0x80008
; GFX7-NEXT: s_lshr_b32 s1, s0, 24
-; GFX7-NEXT: s_and_b32 s3, s0, 0xff
-; GFX7-NEXT: s_lshl_b32 s4, s4, 8
+; GFX7-NEXT: s_and_b32 s2, s0, 0xff
+; GFX7-NEXT: s_lshl_b32 s3, s3, 8
; GFX7-NEXT: s_bfe_u32 s0, s0, 0x80010
-; GFX7-NEXT: s_or_b32 s3, s3, s4
+; GFX7-NEXT: s_or_b32 s2, s2, s3
; GFX7-NEXT: s_lshl_b32 s0, s0, 16
-; GFX7-NEXT: s_or_b32 s0, s3, s0
+; GFX7-NEXT: s_or_b32 s0, s2, s0
; GFX7-NEXT: s_lshl_b32 s1, s1, 24
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, v1, v0
-; GFX7-NEXT: v_lshl_b32_e32 v1, s2, v1
+; GFX7-NEXT: v_lshl_b32_e32 v1, 0xff, v1
; GFX7-NEXT: s_or_b32 s0, s0, s1
; GFX7-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX7-NEXT: v_and_b32_e32 v1, s0, v1
; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
; GFX7-NEXT: v_bfe_u32 v3, v0, 8, 8
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v2, s2, v0
+; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
; GFX7-NEXT: v_or_b32_e32 v2, v2, v3
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: v_and_b32_e32 v2, 3, v2
-; GFX7-NEXT: v_mov_b32_e32 v1, 0xff
+; GFX7-NEXT: v_and_b32_e32 v1, 3, v2
; GFX7-NEXT: s_and_b32 s0, s2, 0xff
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, 3, v2
-; GFX7-NEXT: v_lshl_b32_e32 v3, s0, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, v2, v1
-; GFX7-NEXT: v_xor_b32_e32 v2, -1, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v1
+; GFX7-NEXT: v_lshl_b32_e32 v2, s0, v1
+; GFX7-NEXT: v_lshl_b32_e32 v1, 0xff, v1
+; GFX7-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v6, v0, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v5, 0xff, v0
+; GFX7-NEXT: v_bfe_u32 v5, v0, 8, 8
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 24, v0
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX7-NEXT: v_or_b32_e32 v5, v5, v6
-; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; GFX7-NEXT: v_or_b32_e32 v0, v5, v0
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX7-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX7-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; GFX7-NEXT: v_or_b32_e32 v0, v4, v0
; GFX7-NEXT: v_or_b32_e32 v0, v0, v3
+; GFX7-NEXT: v_and_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
; GFX7-NEXT: v_bfe_u32 v3, v0, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v1, v0, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v0
+; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX7-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
-; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX7-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7-NEXT: s_endpgm
;
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_movk_i32 s0, 0xff
-; GFX7-NEXT: s_and_b32 s1, s2, 3
-; GFX7-NEXT: v_and_b32_e32 v1, s0, v2
-; GFX7-NEXT: s_lshl_b32 s1, s1, 3
-; GFX7-NEXT: v_lshlrev_b32_e32 v1, s1, v1
-; GFX7-NEXT: s_lshl_b32 s1, 0xff, s1
-; GFX7-NEXT: s_not_b32 s1, s1
+; GFX7-NEXT: s_and_b32 s0, s2, 3
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX7-NEXT: s_lshl_b32 s0, s0, 3
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, s0, v1
+; GFX7-NEXT: s_lshl_b32 s0, 0xff, s0
+; GFX7-NEXT: s_not_b32 s0, s0
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_bfe_u32 v4, v0, 8, 8
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v3, s0, v0
+; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
; GFX7-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX7-NEXT: v_or_b32_e32 v0, v3, v0
; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX7-NEXT: v_and_b32_e32 v0, s1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, s0, v0
; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-NEXT: v_bfe_u32 v3, v0, 8, 8
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v0
; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
-; GFX7-NEXT: s_movk_i32 s2, 0xff
-; GFX7-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX7-NEXT: v_mov_b32_e32 v1, 0xff
-; GFX7-NEXT: v_and_b32_e32 v2, s2, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v3, 3, v3
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, v3, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v3, v3, v1
-; GFX7-NEXT: v_xor_b32_e32 v3, -1, v3
+; GFX7-NEXT: v_and_b32_e32 v1, 3, v3
+; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, v1, v2
+; GFX7-NEXT: v_lshl_b32_e32 v1, 0xff, v1
+; GFX7-NEXT: v_xor_b32_e32 v1, -1, v1
+; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v6, v0, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v5, s2, v0
+; GFX7-NEXT: v_bfe_u32 v5, v0, 8, 8
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 24, v0
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX7-NEXT: v_or_b32_e32 v5, v5, v6
-; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; GFX7-NEXT: v_or_b32_e32 v0, v5, v0
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX7-NEXT: v_and_b32_e32 v0, v0, v3
+; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX7-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; GFX7-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v3
+; GFX7-NEXT: v_and_b32_e32 v0, v0, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
; GFX7-NEXT: v_bfe_u32 v3, v0, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v1, v0, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v0
+; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX7-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
-; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX7-NEXT: s_mov_b32 s2, -1
+; GFX7-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm
;
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_movk_i32 s0, 0xff
-; GFX7-NEXT: s_lshr_b32 s1, s3, 2
-; GFX7-NEXT: s_and_b32 s3, s3, 3
+; GFX7-NEXT: s_and_b32 s1, s3, 3
+; GFX7-NEXT: s_lshr_b32 s0, s3, 2
; GFX7-NEXT: s_and_b32 s2, s2, 0xff
-; GFX7-NEXT: s_lshl_b32 s3, s3, 3
-; GFX7-NEXT: s_lshl_b32 s2, s2, s3
-; GFX7-NEXT: s_lshl_b32 s3, 0xff, s3
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s1, 1
-; GFX7-NEXT: s_not_b32 s3, s3
-; GFX7-NEXT: v_mov_b32_e32 v2, 0xff
+; GFX7-NEXT: s_lshl_b32 s1, s1, 3
+; GFX7-NEXT: s_lshl_b32 s2, s2, s1
+; GFX7-NEXT: s_lshl_b32 s1, 0xff, s1
+; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
+; GFX7-NEXT: s_not_b32 s1, s1
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v6, v0, 8, 8
-; GFX7-NEXT: v_bfe_u32 v8, v1, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v1
-; GFX7-NEXT: v_and_b32_e32 v5, s0, v0
+; GFX7-NEXT: v_bfe_u32 v5, v0, 8, 8
+; GFX7-NEXT: v_bfe_u32 v7, v1, 8, 8
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 24, v1
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v7, s0, v1
+; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v1
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v6, 8, v6
-; GFX7-NEXT: v_lshlrev_b32_e32 v8, 8, v8
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v7
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_or_b32_e32 v5, v5, v6
-; GFX7-NEXT: v_or_b32_e32 v6, v7, v8
+; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX7-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; GFX7-NEXT: v_or_b32_e32 v0, v5, v0
-; GFX7-NEXT: v_or_b32_e32 v1, v6, v1
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v3
-; GFX7-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX7-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
-; GFX7-NEXT: v_and_b32_e32 v3, s3, v3
-; GFX7-NEXT: v_or_b32_e32 v3, s2, v3
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], s1, 0
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX7-NEXT: v_bfe_u32 v6, v0, 8, 8
+; GFX7-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX7-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
+; GFX7-NEXT: v_and_b32_e32 v2, s1, v2
+; GFX7-NEXT: v_or_b32_e32 v2, s2, v2
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, 0
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX7-NEXT: v_bfe_u32 v5, v0, 8, 8
; GFX7-NEXT: v_bfe_u32 v7, v1, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v1
-; GFX7-NEXT: v_and_b32_e32 v5, v0, v2
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 24, v1
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v2, v1, v2
+; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v1
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v7
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_or_b32_e32 v5, v5, v6
-; GFX7-NEXT: v_or_b32_e32 v2, v2, v7
+; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX7-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; GFX7-NEXT: v_or_b32_e32 v0, v5, v0
-; GFX7-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v3
-; GFX7-NEXT: v_or_b32_e32 v1, v1, v4
+; GFX7-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX7-NEXT: v_or_b32_e32 v1, v1, v3
; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX7-NEXT: s_endpgm
;
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX7-NEXT: v_mov_b32_e32 v2, 0xff
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_bfe_u32 s6, s0, 0x80008
; GFX7-NEXT: s_lshr_b32 s2, s0, 24
; GFX7-NEXT: v_lshlrev_b32_e32 v0, s4, v0
; GFX7-NEXT: s_lshl_b32 s4, 0xff, s4
; GFX7-NEXT: s_andn2_b32 s3, s3, s4
-; GFX7-NEXT: v_or_b32_e32 v3, s3, v0
+; GFX7-NEXT: v_or_b32_e32 v2, s3, v0
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
-; GFX7-NEXT: v_bfe_u32 v6, v0, 8, 8
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX7-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v5, v0, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; GFX7-NEXT: v_bfe_u32 v5, v0, 8, 8
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v0
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX7-NEXT: v_or_b32_e32 v0, v5, v0
-; GFX7-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v3
-; GFX7-NEXT: v_bfe_u32 v3, v1, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v1
-; GFX7-NEXT: v_and_b32_e32 v2, v1, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX7-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; GFX7-NEXT: v_bfe_u32 v4, v1, 8, 8
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 24, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX7-NEXT: v_or_b32_e32 v2, v2, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX7-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v4
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: v_or_b32_e32 v1, v1, v2
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 2, v0
; GFX7-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX7-NEXT: s_movk_i32 s5, 0xff
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_bfe_u32 s7, s0, 0x80008
+; GFX7-NEXT: s_bfe_u32 s6, s0, 0x80008
; GFX7-NEXT: s_lshr_b32 s2, s0, 24
-; GFX7-NEXT: s_and_b32 s6, s0, 0xff
-; GFX7-NEXT: s_lshl_b32 s7, s7, 8
+; GFX7-NEXT: s_and_b32 s5, s0, 0xff
+; GFX7-NEXT: s_lshl_b32 s6, s6, 8
; GFX7-NEXT: s_bfe_u32 s0, s0, 0x80010
-; GFX7-NEXT: s_or_b32 s6, s6, s7
+; GFX7-NEXT: s_or_b32 s5, s5, s6
; GFX7-NEXT: s_lshl_b32 s0, s0, 16
-; GFX7-NEXT: s_or_b32 s0, s6, s0
+; GFX7-NEXT: s_or_b32 s0, s5, s0
; GFX7-NEXT: s_lshl_b32 s2, s2, 24
-; GFX7-NEXT: s_bfe_u32 s6, s1, 0x80008
+; GFX7-NEXT: s_bfe_u32 s5, s1, 0x80008
; GFX7-NEXT: s_lshr_b32 s3, s1, 24
; GFX7-NEXT: s_or_b32 s0, s0, s2
; GFX7-NEXT: s_and_b32 s2, s1, 0xff
-; GFX7-NEXT: s_lshl_b32 s6, s6, 8
+; GFX7-NEXT: s_lshl_b32 s5, s5, 8
; GFX7-NEXT: s_bfe_u32 s1, s1, 0x80010
-; GFX7-NEXT: s_or_b32 s2, s2, s6
+; GFX7-NEXT: s_or_b32 s2, s2, s5
; GFX7-NEXT: s_lshl_b32 s1, s1, 16
; GFX7-NEXT: s_or_b32 s1, s2, s1
; GFX7-NEXT: s_lshl_b32 s2, s3, 24
; GFX7-NEXT: s_or_b32 s1, s1, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: v_mov_b32_e32 v3, s1
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX7-NEXT: s_and_b32 s2, s4, 0xff
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX7-NEXT: v_lshl_b32_e32 v3, s2, v0
-; GFX7-NEXT: v_lshl_b32_e32 v0, s5, v0
+; GFX7-NEXT: v_lshl_b32_e32 v0, 0xff, v0
; GFX7-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX7-NEXT: v_and_b32_e32 v0, v1, v0
; GFX7-NEXT: v_or_b32_e32 v3, v0, v3
; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
; GFX7-NEXT: v_bfe_u32 v5, v0, 8, 8
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v4, s5, v0
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX7-LABEL: insertelement_s_v8i8_v_v:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX7-NEXT: s_movk_i32 s4, 0xff
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 2, v1
; GFX7-NEXT: v_and_b32_e32 v1, 3, v1
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_bfe_u32 s6, s0, 0x80008
+; GFX7-NEXT: s_bfe_u32 s5, s0, 0x80008
; GFX7-NEXT: s_lshr_b32 s2, s0, 24
-; GFX7-NEXT: s_and_b32 s5, s0, 0xff
-; GFX7-NEXT: s_lshl_b32 s6, s6, 8
+; GFX7-NEXT: s_and_b32 s4, s0, 0xff
+; GFX7-NEXT: s_lshl_b32 s5, s5, 8
; GFX7-NEXT: s_bfe_u32 s0, s0, 0x80010
-; GFX7-NEXT: s_or_b32 s5, s5, s6
+; GFX7-NEXT: s_or_b32 s4, s4, s5
; GFX7-NEXT: s_lshl_b32 s0, s0, 16
-; GFX7-NEXT: s_or_b32 s0, s5, s0
+; GFX7-NEXT: s_or_b32 s0, s4, s0
; GFX7-NEXT: s_lshl_b32 s2, s2, 24
-; GFX7-NEXT: s_bfe_u32 s5, s1, 0x80008
+; GFX7-NEXT: s_bfe_u32 s4, s1, 0x80008
; GFX7-NEXT: s_lshr_b32 s3, s1, 24
; GFX7-NEXT: s_or_b32 s0, s0, s2
; GFX7-NEXT: s_and_b32 s2, s1, 0xff
-; GFX7-NEXT: s_lshl_b32 s5, s5, 8
+; GFX7-NEXT: s_lshl_b32 s4, s4, 8
; GFX7-NEXT: s_bfe_u32 s1, s1, 0x80010
-; GFX7-NEXT: s_or_b32 s2, s2, s5
+; GFX7-NEXT: s_or_b32 s2, s2, s4
; GFX7-NEXT: s_lshl_b32 s1, s1, 16
; GFX7-NEXT: s_or_b32 s1, s2, s1
; GFX7-NEXT: s_lshl_b32 s2, s3, 24
; GFX7-NEXT: s_or_b32 s1, s1, s2
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
; GFX7-NEXT: v_mov_b32_e32 v3, s0
; GFX7-NEXT: v_mov_b32_e32 v4, s1
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v0, v1, v0
-; GFX7-NEXT: v_lshl_b32_e32 v1, s4, v1
+; GFX7-NEXT: v_lshl_b32_e32 v1, 0xff, v1
; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX7-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX7-NEXT: v_and_b32_e32 v1, v3, v1
; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
; GFX7-NEXT: v_bfe_u32 v5, v0, 8, 8
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v4, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_movk_i32 s0, 0xff
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 2, v2
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 2, v2
; GFX7-NEXT: v_and_b32_e32 v2, 3, v2
-; GFX7-NEXT: v_mov_b32_e32 v3, 0xff
-; GFX7-NEXT: s_and_b32 s1, s2, 0xff
+; GFX7-NEXT: s_and_b32 s0, s2, 0xff
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 3, v2
-; GFX7-NEXT: v_lshl_b32_e32 v5, s1, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, v2, v3
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
+; GFX7-NEXT: v_lshl_b32_e32 v4, s0, v2
+; GFX7-NEXT: v_lshl_b32_e32 v2, 0xff, v2
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
; GFX7-NEXT: v_xor_b32_e32 v2, -1, v2
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v9, v0, 8, 8
-; GFX7-NEXT: v_bfe_u32 v11, v1, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v1
-; GFX7-NEXT: v_and_b32_e32 v8, s0, v0
+; GFX7-NEXT: v_bfe_u32 v8, v0, 8, 8
+; GFX7-NEXT: v_bfe_u32 v10, v1, 8, 8
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v1
+; GFX7-NEXT: v_and_b32_e32 v7, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v10, s0, v1
+; GFX7-NEXT: v_and_b32_e32 v9, 0xff, v1
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; GFX7-NEXT: v_lshlrev_b32_e32 v11, 8, v11
+; GFX7-NEXT: v_lshlrev_b32_e32 v8, 8, v8
+; GFX7-NEXT: v_lshlrev_b32_e32 v10, 8, v10
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX7-NEXT: v_or_b32_e32 v9, v10, v11
+; GFX7-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX7-NEXT: v_or_b32_e32 v8, v9, v10
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 24, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v6, 24, v6
-; GFX7-NEXT: v_lshlrev_b32_e32 v7, 24, v7
-; GFX7-NEXT: v_or_b32_e32 v0, v8, v0
-; GFX7-NEXT: v_or_b32_e32 v1, v9, v1
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v6
-; GFX7-NEXT: v_or_b32_e32 v1, v1, v7
-; GFX7-NEXT: v_cndmask_b32_e32 v6, v0, v1, vcc
-; GFX7-NEXT: v_and_b32_e32 v2, v6, v2
-; GFX7-NEXT: v_or_b32_e32 v2, v2, v5
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
+; GFX7-NEXT: v_or_b32_e32 v0, v7, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v8, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v5
+; GFX7-NEXT: v_or_b32_e32 v1, v1, v6
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
+; GFX7-NEXT: v_and_b32_e32 v2, v5, v2
+; GFX7-NEXT: v_or_b32_e32 v2, v2, v4
; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX7-NEXT: v_bfe_u32 v6, v0, 8, 8
+; GFX7-NEXT: v_bfe_u32 v5, v0, 8, 8
; GFX7-NEXT: v_bfe_u32 v7, v1, 8, 8
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v1
-; GFX7-NEXT: v_and_b32_e32 v5, v0, v3
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 24, v1
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v3, v1, v3
+; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v1
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v7
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_or_b32_e32 v5, v5, v6
-; GFX7-NEXT: v_or_b32_e32 v3, v3, v7
+; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX7-NEXT: v_or_b32_e32 v5, v6, v7
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; GFX7-NEXT: v_or_b32_e32 v0, v5, v0
-; GFX7-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; GFX7-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v5, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX7-NEXT: v_or_b32_e32 v1, v1, v4
+; GFX7-NEXT: v_or_b32_e32 v1, v1, v3
; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX7-NEXT: s_endpgm
;
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_movk_i32 s0, 0xff
-; GFX7-NEXT: v_mov_b32_e32 v3, 0xff
-; GFX7-NEXT: s_lshr_b32 s1, s2, 2
-; GFX7-NEXT: s_and_b32 s2, s2, 3
-; GFX7-NEXT: v_and_b32_e32 v2, v2, v3
-; GFX7-NEXT: s_lshl_b32 s2, s2, 3
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, s2, v2
-; GFX7-NEXT: s_lshl_b32 s2, 0xff, s2
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s1, 1
-; GFX7-NEXT: s_not_b32 s2, s2
+; GFX7-NEXT: s_and_b32 s1, s2, 3
+; GFX7-NEXT: s_lshr_b32 s0, s2, 2
+; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX7-NEXT: s_lshl_b32 s1, s1, 3
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, s1, v2
+; GFX7-NEXT: s_lshl_b32 s1, 0xff, s1
+; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
+; GFX7-NEXT: s_not_b32 s1, s1
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v7, v0, 8, 8
-; GFX7-NEXT: v_bfe_u32 v9, v1, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v1
-; GFX7-NEXT: v_and_b32_e32 v6, s0, v0
+; GFX7-NEXT: v_bfe_u32 v6, v0, 8, 8
+; GFX7-NEXT: v_bfe_u32 v8, v1, 8, 8
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 24, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v1
+; GFX7-NEXT: v_and_b32_e32 v5, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v8, s0, v1
+; GFX7-NEXT: v_and_b32_e32 v7, 0xff, v1
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v7
-; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; GFX7-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; GFX7-NEXT: v_lshlrev_b32_e32 v8, 8, v8
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_or_b32_e32 v6, v6, v7
-; GFX7-NEXT: v_or_b32_e32 v7, v8, v9
+; GFX7-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX7-NEXT: v_or_b32_e32 v6, v7, v8
+; GFX7-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; GFX7-NEXT: v_lshlrev_b32_e32 v5, 24, v5
-; GFX7-NEXT: v_or_b32_e32 v0, v6, v0
-; GFX7-NEXT: v_or_b32_e32 v1, v7, v1
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX7-NEXT: v_or_b32_e32 v1, v1, v5
-; GFX7-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc
-; GFX7-NEXT: v_and_b32_e32 v4, s2, v4
-; GFX7-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], s1, 0
+; GFX7-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v6, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v3
+; GFX7-NEXT: v_or_b32_e32 v1, v1, v4
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
+; GFX7-NEXT: v_and_b32_e32 v3, s1, v3
+; GFX7-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, 0
; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX7-NEXT: v_bfe_u32 v6, v0, 8, 8
+; GFX7-NEXT: v_bfe_u32 v5, v0, 8, 8
; GFX7-NEXT: v_bfe_u32 v7, v1, 8, 8
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v1
-; GFX7-NEXT: v_and_b32_e32 v5, v0, v3
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 24, v1
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v3, v1, v3
+; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v1
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v7
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_or_b32_e32 v5, v5, v6
-; GFX7-NEXT: v_or_b32_e32 v3, v3, v7
+; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX7-NEXT: v_or_b32_e32 v5, v6, v7
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; GFX7-NEXT: v_or_b32_e32 v0, v5, v0
-; GFX7-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; GFX7-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v5, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX7-NEXT: v_or_b32_e32 v1, v1, v4
+; GFX7-NEXT: v_or_b32_e32 v1, v1, v3
; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX7-NEXT: s_endpgm
;
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_movk_i32 s0, 0xff
-; GFX7-NEXT: v_mov_b32_e32 v4, 0xff
-; GFX7-NEXT: v_lshrrev_b32_e32 v5, 2, v3
+; GFX7-NEXT: v_lshrrev_b32_e32 v4, 2, v3
; GFX7-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX7-NEXT: v_and_b32_e32 v2, v2, v4
+; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 3, v3
; GFX7-NEXT: v_lshlrev_b32_e32 v2, v3, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v3, v3, v4
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
+; GFX7-NEXT: v_lshl_b32_e32 v3, 0xff, v3
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
; GFX7-NEXT: v_xor_b32_e32 v3, -1, v3
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v9, v0, 8, 8
-; GFX7-NEXT: v_bfe_u32 v11, v1, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v1
-; GFX7-NEXT: v_and_b32_e32 v8, s0, v0
+; GFX7-NEXT: v_bfe_u32 v8, v0, 8, 8
+; GFX7-NEXT: v_bfe_u32 v10, v1, 8, 8
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v1
+; GFX7-NEXT: v_and_b32_e32 v7, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v10, s0, v1
+; GFX7-NEXT: v_and_b32_e32 v9, 0xff, v1
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; GFX7-NEXT: v_lshlrev_b32_e32 v11, 8, v11
+; GFX7-NEXT: v_lshlrev_b32_e32 v8, 8, v8
+; GFX7-NEXT: v_lshlrev_b32_e32 v10, 8, v10
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX7-NEXT: v_or_b32_e32 v9, v10, v11
+; GFX7-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX7-NEXT: v_or_b32_e32 v8, v9, v10
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 24, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v6, 24, v6
-; GFX7-NEXT: v_lshlrev_b32_e32 v7, 24, v7
-; GFX7-NEXT: v_or_b32_e32 v0, v8, v0
-; GFX7-NEXT: v_or_b32_e32 v1, v9, v1
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v6
-; GFX7-NEXT: v_or_b32_e32 v1, v1, v7
-; GFX7-NEXT: v_cndmask_b32_e32 v6, v0, v1, vcc
-; GFX7-NEXT: v_and_b32_e32 v3, v6, v3
+; GFX7-NEXT: v_or_b32_e32 v0, v7, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v8, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v5
+; GFX7-NEXT: v_or_b32_e32 v1, v1, v6
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
+; GFX7-NEXT: v_and_b32_e32 v3, v5, v3
; GFX7-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v5
; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX7-NEXT: v_bfe_u32 v6, v0, 8, 8
+; GFX7-NEXT: v_bfe_u32 v5, v0, 8, 8
; GFX7-NEXT: v_bfe_u32 v7, v1, 8, 8
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 24, v1
-; GFX7-NEXT: v_and_b32_e32 v5, v0, v4
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v4, v1, v4
+; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v1
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v7
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_or_b32_e32 v5, v5, v6
-; GFX7-NEXT: v_or_b32_e32 v4, v4, v7
+; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX7-NEXT: v_or_b32_e32 v5, v6, v7
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX7-NEXT: v_or_b32_e32 v0, v5, v0
-; GFX7-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v5, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
; GFX7-NEXT: v_or_b32_e32 v1, v1, v3
; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX7-NEXT: s_mov_b32 s11, 0xf000
; GFX7-NEXT: s_mov_b64 s[8:9], 0
; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_movk_i32 s0, 0xff
-; GFX7-NEXT: v_mov_b32_e32 v4, 0xff
-; GFX7-NEXT: s_and_b32 s1, s3, 3
+; GFX7-NEXT: s_and_b32 s0, s3, 3
; GFX7-NEXT: s_lshr_b32 s4, s3, 2
-; GFX7-NEXT: s_and_b32 s2, s2, 0xff
-; GFX7-NEXT: s_lshl_b32 s1, s1, 3
-; GFX7-NEXT: s_lshl_b32 s5, s2, s1
-; GFX7-NEXT: s_lshl_b32 s1, 0xff, s1
+; GFX7-NEXT: s_and_b32 s1, s2, 0xff
+; GFX7-NEXT: s_lshl_b32 s0, s0, 3
+; GFX7-NEXT: s_lshl_b32 s5, s1, s0
+; GFX7-NEXT: s_lshl_b32 s0, 0xff, s0
; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
-; GFX7-NEXT: s_not_b32 s6, s1
+; GFX7-NEXT: s_not_b32 s6, s0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, 2
; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, 3
; GFX7-NEXT: s_mov_b32 s10, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v10, v0, 8, 8
-; GFX7-NEXT: v_bfe_u32 v12, v1, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v1
-; GFX7-NEXT: v_and_b32_e32 v9, s0, v0
+; GFX7-NEXT: v_bfe_u32 v9, v0, 8, 8
+; GFX7-NEXT: v_bfe_u32 v11, v1, 8, 8
+; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v1
+; GFX7-NEXT: v_and_b32_e32 v8, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v11, s0, v1
+; GFX7-NEXT: v_and_b32_e32 v10, 0xff, v1
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_bfe_u32 v14, v2, 8, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v10, 8, v10
-; GFX7-NEXT: v_lshlrev_b32_e32 v12, 8, v12
-; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v2
-; GFX7-NEXT: v_and_b32_e32 v13, v2, v4
+; GFX7-NEXT: v_bfe_u32 v13, v2, 8, 8
+; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; GFX7-NEXT: v_lshlrev_b32_e32 v11, 8, v11
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v2
+; GFX7-NEXT: v_and_b32_e32 v12, 0xff, v2
; GFX7-NEXT: v_bfe_u32 v2, v2, 16, 8
-; GFX7-NEXT: v_bfe_u32 v16, v3, 8, 8
+; GFX7-NEXT: v_bfe_u32 v15, v3, 8, 8
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_lshlrev_b32_e32 v14, 8, v14
-; GFX7-NEXT: v_or_b32_e32 v9, v9, v10
-; GFX7-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v3
-; GFX7-NEXT: v_and_b32_e32 v15, v3, v4
+; GFX7-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; GFX7-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX7-NEXT: v_or_b32_e32 v9, v10, v11
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v3
+; GFX7-NEXT: v_and_b32_e32 v14, 0xff, v3
; GFX7-NEXT: v_bfe_u32 v3, v3, 16, 8
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 24, v5
-; GFX7-NEXT: v_lshlrev_b32_e32 v6, 24, v6
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v16, 8, v16
-; GFX7-NEXT: v_or_b32_e32 v11, v13, v14
-; GFX7-NEXT: v_or_b32_e32 v0, v9, v0
-; GFX7-NEXT: v_or_b32_e32 v1, v10, v1
-; GFX7-NEXT: v_lshlrev_b32_e32 v7, 24, v7
+; GFX7-NEXT: v_lshlrev_b32_e32 v15, 8, v15
+; GFX7-NEXT: v_or_b32_e32 v10, v12, v13
+; GFX7-NEXT: v_or_b32_e32 v0, v8, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v9, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v6, 24, v6
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX7-NEXT: v_or_b32_e32 v12, v15, v16
-; GFX7-NEXT: v_or_b32_e32 v2, v11, v2
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v5
-; GFX7-NEXT: v_or_b32_e32 v1, v1, v6
-; GFX7-NEXT: v_lshlrev_b32_e32 v8, 24, v8
-; GFX7-NEXT: v_or_b32_e32 v3, v12, v3
-; GFX7-NEXT: v_or_b32_e32 v2, v2, v7
-; GFX7-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, 2
-; GFX7-NEXT: v_or_b32_e32 v3, v3, v8
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v2, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v3, s[2:3]
-; GFX7-NEXT: v_and_b32_e32 v5, s6, v5
-; GFX7-NEXT: v_or_b32_e32 v5, s5, v5
+; GFX7-NEXT: v_or_b32_e32 v11, v14, v15
+; GFX7-NEXT: v_or_b32_e32 v2, v10, v2
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX7-NEXT: v_or_b32_e32 v1, v1, v5
+; GFX7-NEXT: v_lshlrev_b32_e32 v7, 24, v7
+; GFX7-NEXT: v_or_b32_e32 v3, v11, v3
+; GFX7-NEXT: v_or_b32_e32 v2, v2, v6
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc
+; GFX7-NEXT: v_or_b32_e32 v3, v3, v7
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, v2, s[0:1]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[2:3]
+; GFX7-NEXT: v_and_b32_e32 v4, s6, v4
+; GFX7-NEXT: v_or_b32_e32 v4, s5, v4
; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, 0
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
-; GFX7-NEXT: v_bfe_u32 v10, v0, 8, 8
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[2:3]
-; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v9, v0, v4
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
+; GFX7-NEXT: v_bfe_u32 v9, v0, 8, 8
+; GFX7-NEXT: v_bfe_u32 v11, v1, 8, 8
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[2:3]
+; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v1
+; GFX7-NEXT: v_and_b32_e32 v8, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_bfe_u32 v12, v1, 8, 8
-; GFX7-NEXT: v_bfe_u32 v14, v2, 8, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v10, 8, v10
-; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v2
-; GFX7-NEXT: v_and_b32_e32 v11, v1, v4
-; GFX7-NEXT: v_and_b32_e32 v13, v2, v4
+; GFX7-NEXT: v_and_b32_e32 v10, 0xff, v1
+; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX7-NEXT: v_bfe_u32 v13, v2, 8, 8
+; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; GFX7-NEXT: v_lshlrev_b32_e32 v11, 8, v11
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v2
+; GFX7-NEXT: v_and_b32_e32 v12, 0xff, v2
; GFX7-NEXT: v_bfe_u32 v2, v2, 16, 8
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX7-NEXT: v_lshlrev_b32_e32 v12, 8, v12
-; GFX7-NEXT: v_lshlrev_b32_e32 v14, 8, v14
-; GFX7-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; GFX7-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX7-NEXT: v_or_b32_e32 v9, v10, v11
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 24, v5
-; GFX7-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX7-NEXT: v_or_b32_e32 v11, v13, v14
-; GFX7-NEXT: v_or_b32_e32 v0, v9, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v5
-; GFX7-NEXT: v_or_b32_e32 v2, v11, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v5, 24, v7
-; GFX7-NEXT: v_or_b32_e32 v2, v2, v5
+; GFX7-NEXT: v_or_b32_e32 v10, v12, v13
+; GFX7-NEXT: v_or_b32_e32 v0, v8, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v9, v1
+; GFX7-NEXT: v_or_b32_e32 v2, v10, v2
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX7-NEXT: v_or_b32_e32 v1, v1, v5
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v6
; GFX7-NEXT: v_bfe_u32 v5, v3, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v1
-; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v3
-; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v4, v3, v4
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v3
+; GFX7-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v3
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_bfe_u32 v3, v3, 16, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX7-NEXT: v_lshlrev_b32_e32 v6, 24, v6
-; GFX7-NEXT: v_or_b32_e32 v1, v10, v1
; GFX7-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v8
-; GFX7-NEXT: v_or_b32_e32 v1, v1, v6
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v7
; GFX7-NEXT: v_or_b32_e32 v3, v3, v4
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; GFX7-NEXT: s_endpgm
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX7-NEXT: v_mov_b32_e32 v4, 0xff
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_bfe_u32 s10, s0, 0x80008
; GFX7-NEXT: s_lshr_b32 s5, s0, 24
; GFX7-NEXT: v_lshlrev_b32_e32 v0, s4, v0
; GFX7-NEXT: s_lshl_b32 s4, 0xff, s4
; GFX7-NEXT: s_andn2_b32 s4, s6, s4
-; GFX7-NEXT: v_or_b32_e32 v5, s4, v0
+; GFX7-NEXT: v_or_b32_e32 v4, s4, v0
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s5, 1
; GFX7-NEXT: v_mov_b32_e32 v2, s2
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s5, 2
; GFX7-NEXT: v_mov_b32_e32 v3, s3
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s5, 3
-; GFX7-NEXT: v_bfe_u32 v10, v0, 8, 8
-; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v9, v0, v4
-; GFX7-NEXT: v_lshlrev_b32_e32 v10, 8, v10
+; GFX7-NEXT: v_bfe_u32 v9, v0, 8, 8
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v0
+; GFX7-NEXT: v_and_b32_e32 v8, 0xff, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX7-NEXT: v_or_b32_e32 v8, v8, v9
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX7-NEXT: v_or_b32_e32 v0, v9, v0
-; GFX7-NEXT: v_lshlrev_b32_e32 v5, 24, v5
-; GFX7-NEXT: v_bfe_u32 v9, v1, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v1
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v5
-; GFX7-NEXT: v_and_b32_e32 v5, v1, v4
-; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; GFX7-NEXT: v_or_b32_e32 v0, v8, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v4
+; GFX7-NEXT: v_bfe_u32 v8, v1, 8, 8
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v8, 8, v8
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_or_b32_e32 v5, v5, v9
+; GFX7-NEXT: v_or_b32_e32 v4, v4, v8
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_or_b32_e32 v1, v5, v1
-; GFX7-NEXT: v_lshlrev_b32_e32 v5, 24, v6
-; GFX7-NEXT: v_bfe_u32 v6, v2, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v2
-; GFX7-NEXT: v_or_b32_e32 v1, v1, v5
-; GFX7-NEXT: v_and_b32_e32 v5, v2, v4
-; GFX7-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; GFX7-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v5
+; GFX7-NEXT: v_bfe_u32 v5, v2, 8, 8
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v2
+; GFX7-NEXT: v_or_b32_e32 v1, v1, v4
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_bfe_u32 v2, v2, 16, 8
-; GFX7-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX7-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v5, 24, v7
-; GFX7-NEXT: v_or_b32_e32 v2, v2, v5
+; GFX7-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v6
; GFX7-NEXT: v_bfe_u32 v5, v3, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v3
-; GFX7-NEXT: v_and_b32_e32 v4, v3, v4
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v3
+; GFX7-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v3
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_bfe_u32 v3, v3, 16, 8
; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX7-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v8
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v7
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: v_or_b32_e32 v3, v3, v4
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[2:3]
; GFX7-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX7-NEXT: v_and_b32_e32 v0, v1, v0
-; GFX7-NEXT: v_or_b32_e32 v6, v0, v2
+; GFX7-NEXT: v_or_b32_e32 v5, v0, v2
; GFX7-NEXT: v_mov_b32_e32 v0, s8
; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
-; GFX7-NEXT: v_mov_b32_e32 v5, 0xff
-; GFX7-NEXT: v_bfe_u32 v10, v0, 8, 8
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[4:5]
+; GFX7-NEXT: v_bfe_u32 v9, v0, 8, 8
; GFX7-NEXT: v_mov_b32_e32 v1, s9
; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v9, v0, v5
-; GFX7-NEXT: v_lshlrev_b32_e32 v10, 8, v10
+; GFX7-NEXT: v_and_b32_e32 v8, 0xff, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX7-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX7-NEXT: v_or_b32_e32 v8, v8, v9
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_mov_b32_e32 v2, s10
; GFX7-NEXT: v_mov_b32_e32 v3, s11
-; GFX7-NEXT: v_or_b32_e32 v0, v9, v0
+; GFX7-NEXT: v_or_b32_e32 v0, v8, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; GFX7-NEXT: v_bfe_u32 v9, v1, 8, 8
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[2:3]
-; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v1
+; GFX7-NEXT: v_bfe_u32 v8, v1, 8, 8
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[2:3]
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX7-NEXT: v_and_b32_e32 v4, v1, v5
-; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v8, 8, v8
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_or_b32_e32 v4, v4, v9
+; GFX7-NEXT: v_or_b32_e32 v4, v4, v8
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX7-NEXT: v_or_b32_e32 v1, v4, v1
-; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v6
-; GFX7-NEXT: v_bfe_u32 v6, v2, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v5
+; GFX7-NEXT: v_bfe_u32 v5, v2, 8, 8
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v2
; GFX7-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX7-NEXT: v_and_b32_e32 v4, v2, v5
-; GFX7-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_bfe_u32 v2, v2, 16, 8
-; GFX7-NEXT: v_or_b32_e32 v4, v4, v6
+; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX7-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v7
-; GFX7-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX7-NEXT: v_and_b32_e32 v4, v3, v5
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v6
; GFX7-NEXT: v_bfe_u32 v5, v3, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v3
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v3
+; GFX7-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v3
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_bfe_u32 v3, v3, 16, 8
; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX7-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v8
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v7
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: v_or_b32_e32 v3, v3, v4
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
; GFX7-NEXT: v_lshrrev_b32_e32 v4, 2, v1
-; GFX7-NEXT: s_movk_i32 s8, 0xff
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
; GFX7-NEXT: v_and_b32_e32 v1, 3, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_bfe_u32 s10, s0, 0x80008
+; GFX7-NEXT: s_bfe_u32 s9, s0, 0x80008
; GFX7-NEXT: s_lshr_b32 s4, s0, 24
-; GFX7-NEXT: s_and_b32 s9, s0, 0xff
-; GFX7-NEXT: s_lshl_b32 s10, s10, 8
+; GFX7-NEXT: s_and_b32 s8, s0, 0xff
+; GFX7-NEXT: s_lshl_b32 s9, s9, 8
; GFX7-NEXT: s_bfe_u32 s0, s0, 0x80010
-; GFX7-NEXT: s_or_b32 s9, s9, s10
+; GFX7-NEXT: s_or_b32 s8, s8, s9
; GFX7-NEXT: s_lshl_b32 s0, s0, 16
-; GFX7-NEXT: s_or_b32 s0, s9, s0
+; GFX7-NEXT: s_or_b32 s0, s8, s0
; GFX7-NEXT: s_lshl_b32 s4, s4, 24
-; GFX7-NEXT: s_bfe_u32 s9, s1, 0x80008
+; GFX7-NEXT: s_bfe_u32 s8, s1, 0x80008
; GFX7-NEXT: s_lshr_b32 s5, s1, 24
; GFX7-NEXT: s_or_b32 s4, s0, s4
; GFX7-NEXT: s_and_b32 s0, s1, 0xff
-; GFX7-NEXT: s_lshl_b32 s9, s9, 8
+; GFX7-NEXT: s_lshl_b32 s8, s8, 8
; GFX7-NEXT: s_bfe_u32 s1, s1, 0x80010
-; GFX7-NEXT: s_or_b32 s0, s0, s9
+; GFX7-NEXT: s_or_b32 s0, s0, s8
; GFX7-NEXT: s_lshl_b32 s1, s1, 16
; GFX7-NEXT: s_or_b32 s0, s0, s1
; GFX7-NEXT: s_lshl_b32 s1, s5, 24
; GFX7-NEXT: v_mov_b32_e32 v5, s6
; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v4
-; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v1
-; GFX7-NEXT: v_and_b32_e32 v0, s8, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-NEXT: v_mov_b32_e32 v6, s7
; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v0, v1, v0
-; GFX7-NEXT: v_lshl_b32_e32 v1, s8, v1
+; GFX7-NEXT: v_lshl_b32_e32 v1, 0xff, v1
; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[2:3]
; GFX7-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX7-NEXT: v_and_b32_e32 v1, v2, v1
-; GFX7-NEXT: v_or_b32_e32 v6, v1, v0
+; GFX7-NEXT: v_or_b32_e32 v5, v1, v0
; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: v_mov_b32_e32 v2, s6
; GFX7-NEXT: v_mov_b32_e32 v3, s7
; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
-; GFX7-NEXT: v_mov_b32_e32 v5, 0xff
-; GFX7-NEXT: v_bfe_u32 v10, v0, 8, 8
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[4:5]
+; GFX7-NEXT: v_bfe_u32 v9, v0, 8, 8
; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v9, v0, v5
-; GFX7-NEXT: v_lshlrev_b32_e32 v10, 8, v10
+; GFX7-NEXT: v_and_b32_e32 v8, 0xff, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX7-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX7-NEXT: v_or_b32_e32 v8, v8, v9
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX7-NEXT: v_or_b32_e32 v0, v9, v0
+; GFX7-NEXT: v_or_b32_e32 v0, v8, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; GFX7-NEXT: v_bfe_u32 v9, v1, 8, 8
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[2:3]
-; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v1
+; GFX7-NEXT: v_bfe_u32 v8, v1, 8, 8
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[2:3]
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX7-NEXT: v_and_b32_e32 v4, v1, v5
-; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v8, 8, v8
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_or_b32_e32 v4, v4, v9
+; GFX7-NEXT: v_or_b32_e32 v4, v4, v8
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX7-NEXT: v_or_b32_e32 v1, v4, v1
-; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v6
-; GFX7-NEXT: v_bfe_u32 v6, v2, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v5
+; GFX7-NEXT: v_bfe_u32 v5, v2, 8, 8
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v2
; GFX7-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX7-NEXT: v_and_b32_e32 v4, v2, v5
-; GFX7-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_bfe_u32 v2, v2, 16, 8
-; GFX7-NEXT: v_or_b32_e32 v4, v4, v6
+; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX7-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v7
-; GFX7-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX7-NEXT: v_and_b32_e32 v4, v3, v5
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v6
; GFX7-NEXT: v_bfe_u32 v5, v3, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v3
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v3
+; GFX7-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v3
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_bfe_u32 v3, v3, 16, 8
; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX7-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v8
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v7
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: v_or_b32_e32 v3, v3, v4
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s11, 0xf000
; GFX7-NEXT: s_mov_b64 s[8:9], 0
; GFX7-NEXT: buffer_load_dwordx4 v[3:6], v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_movk_i32 s0, 0xff
-; GFX7-NEXT: v_mov_b32_e32 v7, 0xff
-; GFX7-NEXT: v_lshrrev_b32_e32 v18, 2, v2
+; GFX7-NEXT: v_lshrrev_b32_e32 v17, 2, v2
; GFX7-NEXT: v_and_b32_e32 v2, 3, v2
+; GFX7-NEXT: s_and_b32 s0, s2, 0xff
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 3, v2
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v18
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v17
+; GFX7-NEXT: v_lshl_b32_e32 v18, s0, v2
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v17
+; GFX7-NEXT: v_lshl_b32_e32 v2, 0xff, v2
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v17
+; GFX7-NEXT: v_xor_b32_e32 v2, -1, v2
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v17
; GFX7-NEXT: s_mov_b32 s10, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v11, v3, 8, 8
-; GFX7-NEXT: v_bfe_u32 v13, v4, 8, 8
+; GFX7-NEXT: v_bfe_u32 v10, v3, 8, 8
+; GFX7-NEXT: v_bfe_u32 v12, v4, 8, 8
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v3
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v4
-; GFX7-NEXT: v_and_b32_e32 v10, s0, v3
+; GFX7-NEXT: v_and_b32_e32 v9, 0xff, v3
; GFX7-NEXT: v_bfe_u32 v3, v3, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v12, s0, v4
+; GFX7-NEXT: v_and_b32_e32 v11, 0xff, v4
; GFX7-NEXT: v_bfe_u32 v4, v4, 16, 8
-; GFX7-NEXT: v_bfe_u32 v15, v5, 8, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v11, 8, v11
-; GFX7-NEXT: v_lshlrev_b32_e32 v13, 8, v13
-; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v5
-; GFX7-NEXT: v_and_b32_e32 v14, v5, v7
+; GFX7-NEXT: v_bfe_u32 v14, v5, 8, 8
+; GFX7-NEXT: v_lshlrev_b32_e32 v10, 8, v10
+; GFX7-NEXT: v_lshlrev_b32_e32 v12, 8, v12
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v5
+; GFX7-NEXT: v_and_b32_e32 v13, 0xff, v5
; GFX7-NEXT: v_bfe_u32 v5, v5, 16, 8
-; GFX7-NEXT: v_bfe_u32 v17, v6, 8, 8
+; GFX7-NEXT: v_bfe_u32 v16, v6, 8, 8
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX7-NEXT: v_lshlrev_b32_e32 v15, 8, v15
-; GFX7-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX7-NEXT: v_or_b32_e32 v11, v12, v13
-; GFX7-NEXT: v_lshrrev_b32_e32 v9, 24, v6
-; GFX7-NEXT: v_and_b32_e32 v16, v6, v7
+; GFX7-NEXT: v_lshlrev_b32_e32 v14, 8, v14
+; GFX7-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX7-NEXT: v_or_b32_e32 v10, v11, v12
+; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v6
+; GFX7-NEXT: v_and_b32_e32 v15, 0xff, v6
; GFX7-NEXT: v_bfe_u32 v6, v6, 16, 8
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX7-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; GFX7-NEXT: v_or_b32_e32 v12, v14, v15
-; GFX7-NEXT: v_or_b32_e32 v3, v10, v3
-; GFX7-NEXT: v_or_b32_e32 v4, v11, v4
-; GFX7-NEXT: s_and_b32 s0, s2, 0xff
-; GFX7-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; GFX7-NEXT: v_lshlrev_b32_e32 v16, 8, v16
+; GFX7-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX7-NEXT: v_or_b32_e32 v3, v9, v3
+; GFX7-NEXT: v_or_b32_e32 v4, v10, v4
+; GFX7-NEXT: v_lshlrev_b32_e32 v7, 24, v7
; GFX7-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX7-NEXT: v_or_b32_e32 v13, v16, v17
-; GFX7-NEXT: v_or_b32_e32 v5, v12, v5
+; GFX7-NEXT: v_or_b32_e32 v12, v15, v16
+; GFX7-NEXT: v_or_b32_e32 v5, v11, v5
; GFX7-NEXT: v_or_b32_e32 v0, v3, v0
; GFX7-NEXT: v_or_b32_e32 v1, v4, v1
-; GFX7-NEXT: v_lshl_b32_e32 v19, s0, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v9, 24, v9
-; GFX7-NEXT: v_or_b32_e32 v6, v13, v6
-; GFX7-NEXT: v_or_b32_e32 v3, v5, v8
+; GFX7-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; GFX7-NEXT: v_or_b32_e32 v6, v12, v6
+; GFX7-NEXT: v_or_b32_e32 v3, v5, v7
; GFX7-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v18
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, v2, v7
-; GFX7-NEXT: v_or_b32_e32 v4, v6, v9
+; GFX7-NEXT: v_or_b32_e32 v4, v6, v8
; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v3, s[0:1]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v18
-; GFX7-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v4, s[2:3]
; GFX7-NEXT: v_and_b32_e32 v2, v5, v2
-; GFX7-NEXT: v_or_b32_e32 v2, v2, v19
+; GFX7-NEXT: v_or_b32_e32 v2, v2, v18
; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX7-NEXT: v_bfe_u32 v10, v0, 8, 8
; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v2, s[0:1]
+; GFX7-NEXT: v_bfe_u32 v9, v0, 8, 8
+; GFX7-NEXT: v_bfe_u32 v11, v1, 8, 8
; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, v2, s[2:3]
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v9, v0, v7
-; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_bfe_u32 v12, v1, 8, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v10, 8, v10
; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v1
-; GFX7-NEXT: v_and_b32_e32 v11, v1, v7
+; GFX7-NEXT: v_and_b32_e32 v8, 0xff, v0
+; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
+; GFX7-NEXT: v_and_b32_e32 v10, 0xff, v1
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_bfe_u32 v14, v3, 8, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX7-NEXT: v_lshlrev_b32_e32 v12, 8, v12
-; GFX7-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX7-NEXT: v_bfe_u32 v13, v3, 8, 8
+; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; GFX7-NEXT: v_lshlrev_b32_e32 v11, 8, v11
; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v3
-; GFX7-NEXT: v_and_b32_e32 v13, v3, v7
+; GFX7-NEXT: v_and_b32_e32 v12, 0xff, v3
; GFX7-NEXT: v_bfe_u32 v3, v3, 16, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_lshlrev_b32_e32 v14, 8, v14
-; GFX7-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX7-NEXT: v_or_b32_e32 v0, v9, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; GFX7-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX7-NEXT: v_or_b32_e32 v9, v10, v11
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 24, v5
-; GFX7-NEXT: v_or_b32_e32 v11, v13, v14
-; GFX7-NEXT: v_or_b32_e32 v1, v10, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX7-NEXT: v_or_b32_e32 v10, v12, v13
+; GFX7-NEXT: v_or_b32_e32 v0, v8, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v9, v1
+; GFX7-NEXT: v_or_b32_e32 v3, v10, v3
; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX7-NEXT: v_or_b32_e32 v1, v1, v5
-; GFX7-NEXT: v_or_b32_e32 v2, v11, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v3, 24, v6
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v6
; GFX7-NEXT: v_bfe_u32 v5, v4, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v4
-; GFX7-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX7-NEXT: v_and_b32_e32 v3, v4, v7
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v4
+; GFX7-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_bfe_u32 v4, v4, 16, 8
; GFX7-NEXT: v_or_b32_e32 v3, v3, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX7-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v8
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v7
; GFX7-NEXT: v_or_b32_e32 v3, v3, v4
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; GFX7-NEXT: s_endpgm
; GFX7-NEXT: s_mov_b32 s11, 0xf000
; GFX7-NEXT: s_mov_b64 s[8:9], 0
; GFX7-NEXT: buffer_load_dwordx4 v[3:6], v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_movk_i32 s0, 0xff
-; GFX7-NEXT: v_mov_b32_e32 v7, 0xff
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v2
+; GFX7-NEXT: s_and_b32 s0, s2, 3
; GFX7-NEXT: s_lshr_b32 s4, s2, 2
-; GFX7-NEXT: v_and_b32_e32 v2, v2, v7
+; GFX7-NEXT: s_lshl_b32 s0, s0, 3
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, s0, v0
+; GFX7-NEXT: s_lshl_b32 s0, 0xff, s0
; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
+; GFX7-NEXT: s_not_b32 s5, s0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, 2
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, 3
; GFX7-NEXT: s_mov_b32 s10, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v11, v3, 8, 8
-; GFX7-NEXT: v_bfe_u32 v13, v4, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v3
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v4
-; GFX7-NEXT: v_and_b32_e32 v10, s0, v3
+; GFX7-NEXT: v_bfe_u32 v10, v3, 8, 8
+; GFX7-NEXT: v_bfe_u32 v12, v4, 8, 8
+; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v3
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v4
+; GFX7-NEXT: v_and_b32_e32 v9, 0xff, v3
; GFX7-NEXT: v_bfe_u32 v3, v3, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v12, s0, v4
+; GFX7-NEXT: v_and_b32_e32 v11, 0xff, v4
; GFX7-NEXT: v_bfe_u32 v4, v4, 16, 8
-; GFX7-NEXT: v_bfe_u32 v15, v5, 8, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v11, 8, v11
-; GFX7-NEXT: v_lshlrev_b32_e32 v13, 8, v13
-; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v5
-; GFX7-NEXT: v_and_b32_e32 v14, v5, v7
+; GFX7-NEXT: v_bfe_u32 v14, v5, 8, 8
+; GFX7-NEXT: v_lshlrev_b32_e32 v10, 8, v10
+; GFX7-NEXT: v_lshlrev_b32_e32 v12, 8, v12
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v5
+; GFX7-NEXT: v_and_b32_e32 v13, 0xff, v5
; GFX7-NEXT: v_bfe_u32 v5, v5, 16, 8
-; GFX7-NEXT: v_bfe_u32 v17, v6, 8, 8
-; GFX7-NEXT: s_and_b32 s0, s2, 3
+; GFX7-NEXT: v_bfe_u32 v16, v6, 8, 8
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX7-NEXT: v_lshlrev_b32_e32 v15, 8, v15
-; GFX7-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX7-NEXT: v_or_b32_e32 v11, v12, v13
-; GFX7-NEXT: v_lshrrev_b32_e32 v9, 24, v6
-; GFX7-NEXT: v_and_b32_e32 v16, v6, v7
+; GFX7-NEXT: v_lshlrev_b32_e32 v14, 8, v14
+; GFX7-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX7-NEXT: v_or_b32_e32 v10, v11, v12
+; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v6
+; GFX7-NEXT: v_and_b32_e32 v15, 0xff, v6
; GFX7-NEXT: v_bfe_u32 v6, v6, 16, 8
-; GFX7-NEXT: s_lshl_b32 s0, s0, 3
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX7-NEXT: v_lshlrev_b32_e32 v17, 8, v17
-; GFX7-NEXT: v_or_b32_e32 v12, v14, v15
-; GFX7-NEXT: v_or_b32_e32 v3, v10, v3
-; GFX7-NEXT: v_or_b32_e32 v4, v11, v4
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, s0, v2
-; GFX7-NEXT: s_lshl_b32 s0, 0xff, s0
-; GFX7-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; GFX7-NEXT: v_lshlrev_b32_e32 v16, 8, v16
+; GFX7-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX7-NEXT: v_or_b32_e32 v3, v9, v3
+; GFX7-NEXT: v_or_b32_e32 v4, v10, v4
+; GFX7-NEXT: v_lshlrev_b32_e32 v7, 24, v7
; GFX7-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX7-NEXT: v_or_b32_e32 v13, v16, v17
-; GFX7-NEXT: v_or_b32_e32 v5, v12, v5
-; GFX7-NEXT: v_or_b32_e32 v0, v3, v0
-; GFX7-NEXT: v_or_b32_e32 v1, v4, v1
-; GFX7-NEXT: s_not_b32 s5, s0
-; GFX7-NEXT: v_lshlrev_b32_e32 v9, 24, v9
-; GFX7-NEXT: v_or_b32_e32 v6, v13, v6
-; GFX7-NEXT: v_or_b32_e32 v3, v5, v8
-; GFX7-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, 2
-; GFX7-NEXT: v_or_b32_e32 v4, v6, v9
+; GFX7-NEXT: v_or_b32_e32 v12, v15, v16
+; GFX7-NEXT: v_or_b32_e32 v5, v11, v5
+; GFX7-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX7-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; GFX7-NEXT: v_or_b32_e32 v6, v12, v6
+; GFX7-NEXT: v_or_b32_e32 v3, v5, v7
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v1, v2, vcc
+; GFX7-NEXT: v_or_b32_e32 v4, v6, v8
; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v3, s[0:1]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, 3
; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v4, s[2:3]
; GFX7-NEXT: v_and_b32_e32 v5, s5, v5
-; GFX7-NEXT: v_or_b32_e32 v2, v5, v2
+; GFX7-NEXT: v_or_b32_e32 v0, v5, v0
; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, 0
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX7-NEXT: v_bfe_u32 v10, v0, 8, 8
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v2, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, v2, s[2:3]
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v9, v0, v7
-; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_bfe_u32 v12, v1, 8, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v10, 8, v10
-; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v1
-; GFX7-NEXT: v_and_b32_e32 v11, v1, v7
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v0, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v0, s[0:1]
+; GFX7-NEXT: v_bfe_u32 v9, v1, 8, 8
+; GFX7-NEXT: v_bfe_u32 v11, v2, 8, 8
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, v0, s[2:3]
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v2
+; GFX7-NEXT: v_and_b32_e32 v8, 0xff, v1
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_bfe_u32 v14, v3, 8, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX7-NEXT: v_lshlrev_b32_e32 v12, 8, v12
-; GFX7-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX7-NEXT: v_and_b32_e32 v10, 0xff, v2
+; GFX7-NEXT: v_bfe_u32 v2, v2, 16, 8
+; GFX7-NEXT: v_bfe_u32 v13, v3, 8, 8
+; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; GFX7-NEXT: v_lshlrev_b32_e32 v11, 8, v11
; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v3
-; GFX7-NEXT: v_and_b32_e32 v13, v3, v7
+; GFX7-NEXT: v_and_b32_e32 v12, 0xff, v3
; GFX7-NEXT: v_bfe_u32 v3, v3, 16, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_lshlrev_b32_e32 v14, 8, v14
-; GFX7-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX7-NEXT: v_or_b32_e32 v0, v9, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; GFX7-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX7-NEXT: v_or_b32_e32 v9, v10, v11
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 24, v5
-; GFX7-NEXT: v_or_b32_e32 v11, v13, v14
-; GFX7-NEXT: v_or_b32_e32 v1, v10, v1
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX7-NEXT: v_or_b32_e32 v1, v1, v5
-; GFX7-NEXT: v_or_b32_e32 v2, v11, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v3, 24, v6
+; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX7-NEXT: v_or_b32_e32 v10, v12, v13
+; GFX7-NEXT: v_or_b32_e32 v1, v8, v1
+; GFX7-NEXT: v_or_b32_e32 v2, v9, v2
+; GFX7-NEXT: v_or_b32_e32 v3, v10, v3
+; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v2, v5
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v6
; GFX7-NEXT: v_bfe_u32 v5, v4, 8, 8
-; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v4
-; GFX7-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX7-NEXT: v_and_b32_e32 v3, v4, v7
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v4
+; GFX7-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_bfe_u32 v4, v4, 16, 8
; GFX7-NEXT: v_or_b32_e32 v3, v3, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX7-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v8
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 24, v7
; GFX7-NEXT: v_or_b32_e32 v3, v3, v4
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; GFX7-NEXT: s_endpgm
; GFX7-NEXT: s_mov_b32 s11, 0xf000
; GFX7-NEXT: s_mov_b64 s[8:9], 0
; GFX7-NEXT: buffer_load_dwordx4 v[4:7], v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_movk_i32 s0, 0xff
-; GFX7-NEXT: v_mov_b32_e32 v8, 0xff
-; GFX7-NEXT: v_lshrrev_b32_e32 v19, 2, v3
+; GFX7-NEXT: v_lshrrev_b32_e32 v18, 2, v3
; GFX7-NEXT: v_and_b32_e32 v3, 3, v3
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v19
-; GFX7-NEXT: v_and_b32_e32 v2, v2, v8
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v18
+; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 3, v3
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v18
; GFX7-NEXT: v_lshlrev_b32_e32 v2, v3, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v3, v3, v8
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v19
+; GFX7-NEXT: v_lshl_b32_e32 v3, 0xff, v3
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v18
; GFX7-NEXT: v_xor_b32_e32 v3, -1, v3
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v19
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18
; GFX7-NEXT: s_mov_b32 s10, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v12, v4, 8, 8
-; GFX7-NEXT: v_bfe_u32 v14, v5, 8, 8
+; GFX7-NEXT: v_bfe_u32 v11, v4, 8, 8
+; GFX7-NEXT: v_bfe_u32 v13, v5, 8, 8
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v4
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v5
-; GFX7-NEXT: v_and_b32_e32 v11, s0, v4
+; GFX7-NEXT: v_and_b32_e32 v10, 0xff, v4
; GFX7-NEXT: v_bfe_u32 v4, v4, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v13, s0, v5
+; GFX7-NEXT: v_and_b32_e32 v12, 0xff, v5
; GFX7-NEXT: v_bfe_u32 v5, v5, 16, 8
-; GFX7-NEXT: v_bfe_u32 v16, v6, 8, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v12, 8, v12
-; GFX7-NEXT: v_lshlrev_b32_e32 v14, 8, v14
-; GFX7-NEXT: v_lshrrev_b32_e32 v9, 24, v6
-; GFX7-NEXT: v_and_b32_e32 v15, v6, v8
+; GFX7-NEXT: v_bfe_u32 v15, v6, 8, 8
+; GFX7-NEXT: v_lshlrev_b32_e32 v11, 8, v11
+; GFX7-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v6
+; GFX7-NEXT: v_and_b32_e32 v14, 0xff, v6
; GFX7-NEXT: v_bfe_u32 v6, v6, 16, 8
-; GFX7-NEXT: v_bfe_u32 v18, v7, 8, 8
+; GFX7-NEXT: v_bfe_u32 v17, v7, 8, 8
; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX7-NEXT: v_lshlrev_b32_e32 v16, 8, v16
-; GFX7-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX7-NEXT: v_or_b32_e32 v12, v13, v14
-; GFX7-NEXT: v_lshrrev_b32_e32 v10, 24, v7
-; GFX7-NEXT: v_and_b32_e32 v17, v7, v8
+; GFX7-NEXT: v_lshlrev_b32_e32 v15, 8, v15
+; GFX7-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX7-NEXT: v_or_b32_e32 v11, v12, v13
+; GFX7-NEXT: v_lshrrev_b32_e32 v9, 24, v7
+; GFX7-NEXT: v_and_b32_e32 v16, 0xff, v7
; GFX7-NEXT: v_bfe_u32 v7, v7, 16, 8
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX7-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX7-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; GFX7-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX7-NEXT: v_or_b32_e32 v4, v11, v4
-; GFX7-NEXT: v_or_b32_e32 v5, v12, v5
-; GFX7-NEXT: v_lshlrev_b32_e32 v9, 24, v9
+; GFX7-NEXT: v_lshlrev_b32_e32 v17, 8, v17
+; GFX7-NEXT: v_or_b32_e32 v12, v14, v15
+; GFX7-NEXT: v_or_b32_e32 v4, v10, v4
+; GFX7-NEXT: v_or_b32_e32 v5, v11, v5
+; GFX7-NEXT: v_lshlrev_b32_e32 v8, 24, v8
; GFX7-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX7-NEXT: v_or_b32_e32 v14, v17, v18
-; GFX7-NEXT: v_or_b32_e32 v6, v13, v6
+; GFX7-NEXT: v_or_b32_e32 v13, v16, v17
+; GFX7-NEXT: v_or_b32_e32 v6, v12, v6
; GFX7-NEXT: v_or_b32_e32 v0, v4, v0
; GFX7-NEXT: v_or_b32_e32 v1, v5, v1
-; GFX7-NEXT: v_lshlrev_b32_e32 v10, 24, v10
-; GFX7-NEXT: v_or_b32_e32 v7, v14, v7
-; GFX7-NEXT: v_or_b32_e32 v4, v6, v9
+; GFX7-NEXT: v_lshlrev_b32_e32 v9, 24, v9
+; GFX7-NEXT: v_or_b32_e32 v7, v13, v7
+; GFX7-NEXT: v_or_b32_e32 v4, v6, v8
; GFX7-NEXT: v_cndmask_b32_e32 v6, v0, v1, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v19
-; GFX7-NEXT: v_or_b32_e32 v5, v7, v10
+; GFX7-NEXT: v_or_b32_e32 v5, v7, v9
; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[0:1]
; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, v5, s[2:3]
; GFX7-NEXT: v_and_b32_e32 v3, v6, v3
; GFX7-NEXT: v_or_b32_e32 v2, v3, v2
; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX7-NEXT: v_bfe_u32 v10, v0, 8, 8
; GFX7-NEXT: v_cndmask_b32_e64 v3, v4, v2, s[0:1]
+; GFX7-NEXT: v_bfe_u32 v9, v0, 8, 8
+; GFX7-NEXT: v_bfe_u32 v11, v1, 8, 8
; GFX7-NEXT: v_cndmask_b32_e64 v4, v5, v2, s[2:3]
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v9, v0, v8
-; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_bfe_u32 v12, v1, 8, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v10, 8, v10
; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v1
-; GFX7-NEXT: v_and_b32_e32 v11, v1, v8
+; GFX7-NEXT: v_and_b32_e32 v8, 0xff, v0
+; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
+; GFX7-NEXT: v_and_b32_e32 v10, 0xff, v1
; GFX7-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX7-NEXT: v_bfe_u32 v14, v3, 8, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX7-NEXT: v_lshlrev_b32_e32 v12, 8, v12
-; GFX7-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX7-NEXT: v_bfe_u32 v13, v3, 8, 8
+; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; GFX7-NEXT: v_lshlrev_b32_e32 v11, 8, v11
; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v3
-; GFX7-NEXT: v_and_b32_e32 v13, v3, v8
+; GFX7-NEXT: v_and_b32_e32 v12, 0xff, v3
; GFX7-NEXT: v_bfe_u32 v3, v3, 16, 8
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_lshlrev_b32_e32 v14, 8, v14
-; GFX7-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX7-NEXT: v_or_b32_e32 v0, v9, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; GFX7-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX7-NEXT: v_or_b32_e32 v9, v10, v11
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 24, v5
-; GFX7-NEXT: v_or_b32_e32 v11, v13, v14
-; GFX7-NEXT: v_or_b32_e32 v1, v10, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX7-NEXT: v_or_b32_e32 v10, v12, v13
+; GFX7-NEXT: v_or_b32_e32 v0, v8, v0
+; GFX7-NEXT: v_or_b32_e32 v1, v9, v1
+; GFX7-NEXT: v_or_b32_e32 v3, v10, v3
; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX7-NEXT: v_or_b32_e32 v1, v1, v5
-; GFX7-NEXT: v_or_b32_e32 v2, v11, v2
-; GFX7-NEXT: v_lshlrev_b32_e32 v3, 24, v6
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 24, v6
; GFX7-NEXT: v_bfe_u32 v5, v4, 8, 8
; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX7-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX7-NEXT: v_and_b32_e32 v3, v4, v8
+; GFX7-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX7-NEXT: v_bfe_u32 v4, v4, 16, 8
; GFX7-NEXT: v_or_b32_e32 v3, v3, v5
; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s8
; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s9
; GFX8-UNPACKED-NEXT: image_load v[0:2], v0, s[0:7] dmask:0x7 unorm d16
-; GFX8-UNPACKED-NEXT: s_mov_b32 s0, 0xffff
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
-; GFX8-UNPACKED-NEXT: v_and_b32_e32 v3, s0, v1
-; GFX8-UNPACKED-NEXT: v_and_b32_e32 v1, s0, v2
+; GFX8-UNPACKED-NEXT: v_and_b32_e32 v3, 0xffff, v1
+; GFX8-UNPACKED-NEXT: v_and_b32_e32 v1, 0xffff, v2
; GFX8-UNPACKED-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX8-UNPACKED-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-UNPACKED-NEXT: ; return to shader part epilog
; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s8
; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s9
; GFX8-UNPACKED-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm d16
-; GFX8-UNPACKED-NEXT: s_mov_b32 s0, 0xffff
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
-; GFX8-UNPACKED-NEXT: v_and_b32_e32 v1, s0, v1
-; GFX8-UNPACKED-NEXT: v_and_b32_e32 v3, s0, v3
+; GFX8-UNPACKED-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX8-UNPACKED-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX8-UNPACKED-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX8-UNPACKED-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX8-UNPACKED-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX906-NEXT: s_movk_i32 s4, 0xff
; GFX906-NEXT: v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX906-NEXT: v_and_or_b32 v0, v0, s4, v1
-; GFX906-NEXT: v_and_b32_e32 v1, s4, v2
-; GFX906-NEXT: v_and_b32_e32 v2, s4, v3
+; GFX906-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX906-NEXT: v_and_b32_e32 v2, 0xff, v3
; GFX906-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX906-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX906-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX906-NEXT: v_lshlrev_b32_sdwa v1, s5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX906-NEXT: v_and_b32_e32 v2, s4, v6
-; GFX906-NEXT: v_and_b32_e32 v3, s4, v7
+; GFX906-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX906-NEXT: v_and_b32_e32 v3, 0xff, v7
; GFX906-NEXT: v_and_or_b32 v1, v4, s4, v1
; GFX906-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX906-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; GFX906-NEXT: s_movk_i32 s4, 0xff
; GFX906-NEXT: v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX906-NEXT: v_and_or_b32 v0, v0, s4, v1
-; GFX906-NEXT: v_and_b32_e32 v1, s4, v2
-; GFX906-NEXT: v_and_b32_e32 v2, s4, v3
+; GFX906-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX906-NEXT: v_and_b32_e32 v2, 0xff, v3
; GFX906-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX906-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX906-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX906-NEXT: v_lshlrev_b32_sdwa v1, s5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX906-NEXT: v_and_b32_e32 v2, s4, v6
-; GFX906-NEXT: v_and_b32_e32 v3, s4, v7
+; GFX906-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX906-NEXT: v_and_b32_e32 v3, 0xff, v7
; GFX906-NEXT: v_and_or_b32 v1, v4, s4, v1
; GFX906-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX906-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; GFX6-LABEL: v_lshr_i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_movk_i32 s4, 0xff
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GCN-LABEL: v_lshr_i24:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s4, 0xffffff
-; GCN-NEXT: v_and_b32_e32 v1, s4, v1
-; GCN-NEXT: v_and_b32_e32 v0, s4, v0
+; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-LABEL: v_lshr_i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-LABEL: v_lshr_v2i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
define amdgpu_ps float @lshr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {
; GFX6-LABEL: lshr_v2i16_sv:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_mov_b32 s2, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0
-; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: s_and_b32 s0, s1, 0xffff
; GFX6-NEXT: v_lshr_b32_e32 v1, s0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
define amdgpu_ps float @lshr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) {
; GFX6-LABEL: lshr_v2i16_vs:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0
; GFX6-NEXT: s_and_b32 s0, s1, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, s0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-LABEL: v_lshr_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v4, v0
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v5
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v4, v1
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v6
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v6
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v7
-; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v3, v4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-LABEL: v_lshr_v8i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v8
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v8, v0
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v9
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v9
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v8, v1
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v10
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v10
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v8, v2
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v11
-; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v11
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v3, v8, v3
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v12
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v12
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v8, v4
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v13
-; GFX6-NEXT: v_and_b32_e32 v5, s4, v5
-; GFX6-NEXT: v_mov_b32_e32 v16, 0xffff
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v13
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX6-NEXT: v_lshrrev_b32_e32 v5, v8, v5
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v14
-; GFX6-NEXT: v_and_b32_e32 v6, s4, v6
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v14
+; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX6-NEXT: v_lshrrev_b32_e32 v6, v8, v6
-; GFX6-NEXT: v_and_b32_e32 v8, v15, v16
-; GFX6-NEXT: v_and_b32_e32 v7, v7, v16
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v15
+; GFX6-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v7, v8, v7
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-LABEL: v_mul_i16:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7-NEXT: v_mul_u32_u24_e32 v0, v0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_mul_i16_signext:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7-NEXT: v_mul_u32_u24_e32 v0, v0, v1
; GFX7-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX7-NEXT: s_setpc_b64 s[30:31]
; GFX8-LABEL: v_mul_v2i16_fneg_lhs_fneg_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_mov_b32 s4, 0x80008000
-; GFX8-NEXT: v_xor_b32_e32 v0, s4, v0
-; GFX8-NEXT: v_xor_b32_e32 v1, s4, v1
+; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
; GFX8-NEXT: v_mul_lo_u16_e32 v2, v0, v1
; GFX8-NEXT: v_mul_lo_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
; GFX6-LABEL: v_orn2_v2i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_and_b32_e32 v0, v0, v4
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v4
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-LABEL: v_orn2_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v8, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_and_b32_e32 v0, v0, v8
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v8
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v5
-; GFX6-NEXT: v_and_b32_e32 v3, v4, v8
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v4
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX6-NEXT: v_and_b32_e32 v4, v6, v8
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v6
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX6-NEXT: v_xor_b32_e32 v3, -1, v3
; GFX6-LABEL: v_roundeven_v2f64:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s6, 1
-; GFX6-NEXT: v_and_b32_e32 v5, s6, v1
-; GFX6-NEXT: s_mov_b32 s7, 0x43300000
+; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v1
; GFX6-NEXT: v_mov_b32_e32 v4, 0
-; GFX6-NEXT: v_or_b32_e32 v5, s7, v5
+; GFX6-NEXT: v_or_b32_e32 v5, 0x43300000, v5
; GFX6-NEXT: v_add_f64 v[6:7], v[0:1], v[4:5]
; GFX6-NEXT: s_mov_b32 s4, -1
; GFX6-NEXT: s_mov_b32 s5, 0x432fffff
; GFX6-NEXT: v_add_f64 v[5:6], v[6:7], -v[4:5]
; GFX6-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
-; GFX6-NEXT: v_and_b32_e32 v5, s6, v3
-; GFX6-NEXT: v_or_b32_e32 v5, s7, v5
+; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v3
+; GFX6-NEXT: v_or_b32_e32 v5, 0x43300000, v5
; GFX6-NEXT: v_add_f64 v[7:8], v[2:3], v[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
; GFX6-NEXT: v_add_f64 v[4:5], v[7:8], -v[4:5]
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 24, v1
-; GFX6-NEXT: v_mov_b32_e32 v2, 0xff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0
-; GFX6-NEXT: v_and_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: v_mov_b32_e32 v2, 8
; GFX8-NEXT: v_lshrrev_b32_sdwa v3, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX8-NEXT: s_movk_i32 s5, 0x8000
; GFX8-NEXT: v_min_i16_e32 v5, 0, v0
; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_max_i16_e32 v4, 0, v0
-; GFX8-NEXT: v_sub_u16_e32 v5, s5, v5
-; GFX8-NEXT: v_sub_u16_e32 v4, s4, v4
+; GFX8-NEXT: v_sub_u16_e32 v5, 0x8000, v5
+; GFX8-NEXT: v_sub_u16_e32 v4, 0x7fff, v4
; GFX8-NEXT: v_max_i16_e32 v1, v5, v1
; GFX8-NEXT: v_min_i16_e32 v1, v1, v4
; GFX8-NEXT: v_min_i16_e32 v4, 0, v3
; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
; GFX8-NEXT: v_max_i16_e32 v1, 0, v3
-; GFX8-NEXT: v_sub_u16_e32 v4, s5, v4
-; GFX8-NEXT: v_sub_u16_e32 v1, s4, v1
+; GFX8-NEXT: v_sub_u16_e32 v4, 0x8000, v4
+; GFX8-NEXT: v_sub_u16_e32 v1, 0x7fff, v1
; GFX8-NEXT: v_max_i16_e32 v2, v4, v2
; GFX8-NEXT: v_min_i16_e32 v1, v2, v1
; GFX8-NEXT: v_add_u16_e32 v1, v3, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 24, v7
; GFX6-NEXT: v_max_i32_e32 v5, 0, v3
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v11, v6
-; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v9, v5
; GFX6-NEXT: v_max_i32_e32 v4, v6, v4
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 24, v2
; GFX6-NEXT: v_min_i32_e32 v4, v4, v5
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 24, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 24, v0
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX8-NEXT: s_movk_i32 s5, 0x8000
-; GFX8-NEXT: v_min_i16_e32 v10, 0, v0
+; GFX8-NEXT: v_min_i16_e32 v9, 0, v0
; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_max_i16_e32 v8, 0, v0
-; GFX8-NEXT: v_sub_u16_e32 v10, s5, v10
-; GFX8-NEXT: v_sub_u16_e32 v8, s4, v8
-; GFX8-NEXT: v_max_i16_e32 v1, v10, v1
+; GFX8-NEXT: v_sub_u16_e32 v9, 0x8000, v9
+; GFX8-NEXT: v_sub_u16_e32 v8, 0x7fff, v8
+; GFX8-NEXT: v_max_i16_e32 v1, v9, v1
; GFX8-NEXT: v_min_i16_e32 v1, v1, v8
; GFX8-NEXT: v_min_i16_e32 v8, 0, v3
; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
; GFX8-NEXT: v_max_i16_e32 v1, 0, v3
-; GFX8-NEXT: v_sub_u16_e32 v8, s5, v8
-; GFX8-NEXT: v_sub_u16_e32 v1, s4, v1
+; GFX8-NEXT: v_sub_u16_e32 v8, 0x8000, v8
+; GFX8-NEXT: v_sub_u16_e32 v1, 0x7fff, v1
; GFX8-NEXT: v_max_i16_e32 v2, v8, v2
; GFX8-NEXT: v_min_i16_e32 v1, v2, v1
; GFX8-NEXT: v_lshlrev_b16_e32 v2, 8, v4
; GFX8-NEXT: v_add_u16_e32 v1, v3, v1
; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v6
; GFX8-NEXT: v_min_i16_e32 v6, 0, v2
-; GFX8-NEXT: v_mov_b32_e32 v9, 0x7fff
; GFX8-NEXT: v_max_i16_e32 v4, 0, v2
-; GFX8-NEXT: v_sub_u16_e32 v6, s5, v6
-; GFX8-NEXT: v_sub_u16_e32 v4, v9, v4
+; GFX8-NEXT: v_sub_u16_e32 v6, 0x8000, v6
+; GFX8-NEXT: v_sub_u16_e32 v4, 0x7fff, v4
; GFX8-NEXT: v_max_i16_e32 v3, v6, v3
; GFX8-NEXT: v_min_i16_e32 v3, v3, v4
; GFX8-NEXT: v_add_u16_e32 v2, v2, v3
; GFX8-NEXT: v_lshlrev_b16_e32 v4, 8, v7
; GFX8-NEXT: v_max_i16_e32 v5, 0, v3
; GFX8-NEXT: v_sub_u16_e32 v6, 0x8000, v6
-; GFX8-NEXT: v_sub_u16_e32 v5, v9, v5
+; GFX8-NEXT: v_sub_u16_e32 v5, 0x7fff, v5
; GFX8-NEXT: v_max_i16_e32 v4, v6, v4
; GFX8-NEXT: v_min_i16_e32 v4, v4, v5
; GFX8-NEXT: v_add_u16_e32 v3, v3, v4
; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v2
-; GFX9-NEXT: v_and_b32_e32 v2, s4, v1
+; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: s_mov_b32 s5, 24
; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v2
-; GFX9-NEXT: v_and_b32_e32 v2, s0, v1
+; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX8-LABEL: v_saddsat_v2i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s5, 0x8000
; GFX8-NEXT: v_min_i16_e32 v4, 0, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_max_i16_e32 v3, 0, v0
-; GFX8-NEXT: v_sub_u16_e32 v4, s5, v4
-; GFX8-NEXT: v_sub_u16_e32 v3, s4, v3
+; GFX8-NEXT: v_sub_u16_e32 v4, 0x8000, v4
+; GFX8-NEXT: v_sub_u16_e32 v3, 0x7fff, v3
; GFX8-NEXT: v_max_i16_e32 v4, v4, v1
; GFX8-NEXT: v_min_i16_e32 v5, 0, v2
; GFX8-NEXT: v_min_i16_e32 v3, v4, v3
; GFX8-NEXT: v_max_i16_e32 v4, 0, v2
-; GFX8-NEXT: v_sub_u16_e32 v5, s5, v5
-; GFX8-NEXT: v_sub_u16_e32 v4, s4, v4
+; GFX8-NEXT: v_sub_u16_e32 v5, 0x8000, v5
+; GFX8-NEXT: v_sub_u16_e32 v4, 0x7fff, v4
; GFX8-NEXT: v_max_i16_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_min_i16_e32 v1, v1, v4
; GFX8-NEXT: v_add_u16_e32 v0, v0, v3
; GFX6-NEXT: v_min_i32_e32 v1, s1, v1
; GFX6-NEXT: v_add_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
-; GFX6-NEXT: s_mov_b32 s0, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
-; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog
; GFX6-NEXT: v_min_i32_e32 v2, v3, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
-; GFX6-NEXT: s_mov_b32 s0, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
-; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: saddsat_v2i16_vs:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_movk_i32 s3, 0x8000
; GFX8-NEXT: v_min_i16_e32 v3, 0, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX8-NEXT: s_movk_i32 s2, 0x7fff
; GFX8-NEXT: v_max_i16_e32 v2, 0, v0
-; GFX8-NEXT: v_sub_u16_e32 v3, s3, v3
-; GFX8-NEXT: v_sub_u16_e32 v2, s2, v2
+; GFX8-NEXT: v_sub_u16_e32 v3, 0x8000, v3
+; GFX8-NEXT: v_sub_u16_e32 v2, 0x7fff, v2
; GFX8-NEXT: v_max_i16_e32 v3, s0, v3
; GFX8-NEXT: v_min_i16_e32 v4, 0, v1
; GFX8-NEXT: s_lshr_b32 s1, s0, 16
; GFX8-NEXT: v_min_i16_e32 v2, v3, v2
; GFX8-NEXT: v_max_i16_e32 v3, 0, v1
-; GFX8-NEXT: v_sub_u16_e32 v4, s3, v4
-; GFX8-NEXT: v_sub_u16_e32 v3, s2, v3
+; GFX8-NEXT: v_sub_u16_e32 v4, 0x8000, v4
+; GFX8-NEXT: v_sub_u16_e32 v3, 0x7fff, v3
; GFX8-NEXT: v_max_i16_e32 v4, s1, v4
; GFX8-NEXT: v_min_i16_e32 v3, v4, v3
; GFX8-NEXT: v_add_u16_e32 v0, v0, v2
; GFX6-NEXT: v_max_i32_e32 v4, v6, v4
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: v_min_i32_e32 v4, v4, v5
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-LABEL: v_saddsat_v4i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s5, 0x8000
; GFX8-NEXT: v_min_i16_e32 v7, 0, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_max_i16_e32 v6, 0, v0
-; GFX8-NEXT: v_sub_u16_e32 v7, s5, v7
-; GFX8-NEXT: v_sub_u16_e32 v6, s4, v6
+; GFX8-NEXT: v_sub_u16_e32 v7, 0x8000, v7
+; GFX8-NEXT: v_sub_u16_e32 v6, 0x7fff, v6
; GFX8-NEXT: v_max_i16_e32 v7, v7, v2
; GFX8-NEXT: v_min_i16_e32 v8, 0, v4
; GFX8-NEXT: v_min_i16_e32 v6, v7, v6
; GFX8-NEXT: v_max_i16_e32 v7, 0, v4
-; GFX8-NEXT: v_sub_u16_e32 v8, s5, v8
-; GFX8-NEXT: v_sub_u16_e32 v7, s4, v7
+; GFX8-NEXT: v_sub_u16_e32 v8, 0x8000, v8
+; GFX8-NEXT: v_sub_u16_e32 v7, 0x7fff, v7
; GFX8-NEXT: v_max_i16_sdwa v2, v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_min_i16_e32 v8, 0, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX8-NEXT: v_min_i16_e32 v2, v2, v7
; GFX8-NEXT: v_max_i16_e32 v7, 0, v1
-; GFX8-NEXT: v_sub_u16_e32 v8, s5, v8
-; GFX8-NEXT: v_sub_u16_e32 v7, s4, v7
+; GFX8-NEXT: v_sub_u16_e32 v8, 0x8000, v8
+; GFX8-NEXT: v_sub_u16_e32 v7, 0x7fff, v7
; GFX8-NEXT: v_max_i16_e32 v8, v8, v3
; GFX8-NEXT: v_min_i16_e32 v9, 0, v5
; GFX8-NEXT: v_min_i16_e32 v7, v8, v7
; GFX8-NEXT: v_max_i16_e32 v8, 0, v5
-; GFX8-NEXT: v_sub_u16_e32 v9, s5, v9
-; GFX8-NEXT: v_sub_u16_e32 v8, s4, v8
+; GFX8-NEXT: v_sub_u16_e32 v9, 0x8000, v9
+; GFX8-NEXT: v_sub_u16_e32 v8, 0x7fff, v8
; GFX8-NEXT: v_max_i16_sdwa v3, v9, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_min_i16_e32 v3, v3, v8
; GFX8-NEXT: v_add_u16_e32 v0, v0, v6
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v13, v7
; GFX6-NEXT: v_max_i32_e32 v6, v8, v6
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_min_i32_e32 v6, v6, v7
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v5, 16, v5
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v4, 16, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_and_b32_e32 v3, s4, v5
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v5
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v4
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-LABEL: v_saddsat_v6i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s5, 0x8000
-; GFX8-NEXT: v_min_i16_e32 v11, 0, v0
+; GFX8-NEXT: v_min_i16_e32 v10, 0, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_max_i16_e32 v9, 0, v0
-; GFX8-NEXT: v_sub_u16_e32 v11, s5, v11
-; GFX8-NEXT: v_sub_u16_e32 v9, s4, v9
-; GFX8-NEXT: v_max_i16_e32 v11, v11, v3
-; GFX8-NEXT: v_min_i16_e32 v13, 0, v6
-; GFX8-NEXT: v_min_i16_e32 v9, v11, v9
-; GFX8-NEXT: v_max_i16_e32 v11, 0, v6
-; GFX8-NEXT: v_sub_u16_e32 v13, s5, v13
-; GFX8-NEXT: v_sub_u16_e32 v11, s4, v11
-; GFX8-NEXT: v_max_i16_sdwa v3, v13, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_min_i16_e32 v13, 0, v1
+; GFX8-NEXT: v_sub_u16_e32 v10, 0x8000, v10
+; GFX8-NEXT: v_sub_u16_e32 v9, 0x7fff, v9
+; GFX8-NEXT: v_max_i16_e32 v10, v10, v3
+; GFX8-NEXT: v_min_i16_e32 v11, 0, v6
+; GFX8-NEXT: v_min_i16_e32 v9, v10, v9
+; GFX8-NEXT: v_max_i16_e32 v10, 0, v6
+; GFX8-NEXT: v_sub_u16_e32 v11, 0x8000, v11
+; GFX8-NEXT: v_sub_u16_e32 v10, 0x7fff, v10
+; GFX8-NEXT: v_max_i16_sdwa v3, v11, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_min_i16_e32 v11, 0, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX8-NEXT: v_min_i16_e32 v3, v3, v11
-; GFX8-NEXT: v_max_i16_e32 v11, 0, v1
-; GFX8-NEXT: v_sub_u16_e32 v13, s5, v13
-; GFX8-NEXT: v_sub_u16_e32 v11, s4, v11
-; GFX8-NEXT: v_max_i16_e32 v13, v13, v4
-; GFX8-NEXT: v_min_i16_e32 v14, 0, v7
-; GFX8-NEXT: v_min_i16_e32 v11, v13, v11
-; GFX8-NEXT: v_max_i16_e32 v13, 0, v7
-; GFX8-NEXT: v_sub_u16_e32 v14, s5, v14
-; GFX8-NEXT: v_mov_b32_e32 v12, 0xffff8000
-; GFX8-NEXT: v_sub_u16_e32 v13, s4, v13
-; GFX8-NEXT: v_max_i16_sdwa v4, v14, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_min_i16_e32 v14, 0, v2
-; GFX8-NEXT: v_mov_b32_e32 v10, 0x7fff
-; GFX8-NEXT: v_min_i16_e32 v4, v4, v13
-; GFX8-NEXT: v_max_i16_e32 v13, 0, v2
-; GFX8-NEXT: v_sub_u16_e32 v14, v12, v14
+; GFX8-NEXT: v_min_i16_e32 v3, v3, v10
+; GFX8-NEXT: v_max_i16_e32 v10, 0, v1
+; GFX8-NEXT: v_sub_u16_e32 v11, 0x8000, v11
+; GFX8-NEXT: v_sub_u16_e32 v10, 0x7fff, v10
+; GFX8-NEXT: v_max_i16_e32 v11, v11, v4
+; GFX8-NEXT: v_min_i16_e32 v12, 0, v7
+; GFX8-NEXT: v_min_i16_e32 v10, v11, v10
+; GFX8-NEXT: v_max_i16_e32 v11, 0, v7
+; GFX8-NEXT: v_sub_u16_e32 v12, 0x8000, v12
+; GFX8-NEXT: v_sub_u16_e32 v11, 0x7fff, v11
+; GFX8-NEXT: v_max_i16_sdwa v4, v12, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_min_i16_e32 v12, 0, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX8-NEXT: v_sub_u16_e32 v13, v10, v13
-; GFX8-NEXT: v_max_i16_e32 v14, v14, v5
-; GFX8-NEXT: v_min_i16_e32 v13, v14, v13
-; GFX8-NEXT: v_max_i16_e32 v14, 0, v8
-; GFX8-NEXT: v_sub_u16_e32 v10, v10, v14
-; GFX8-NEXT: v_min_i16_e32 v14, 0, v8
-; GFX8-NEXT: v_sub_u16_e32 v12, v12, v14
-; GFX8-NEXT: v_max_i16_sdwa v5, v12, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_min_i16_e32 v4, v4, v11
+; GFX8-NEXT: v_max_i16_e32 v11, 0, v2
+; GFX8-NEXT: v_sub_u16_e32 v12, 0x8000, v12
+; GFX8-NEXT: v_sub_u16_e32 v11, 0x7fff, v11
+; GFX8-NEXT: v_max_i16_e32 v12, v12, v5
+; GFX8-NEXT: v_min_i16_e32 v13, 0, v8
+; GFX8-NEXT: v_min_i16_e32 v11, v12, v11
+; GFX8-NEXT: v_max_i16_e32 v12, 0, v8
+; GFX8-NEXT: v_sub_u16_e32 v13, 0x8000, v13
+; GFX8-NEXT: v_sub_u16_e32 v12, 0x7fff, v12
+; GFX8-NEXT: v_max_i16_sdwa v5, v13, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_add_u16_e32 v0, v0, v9
; GFX8-NEXT: v_add_u16_sdwa v3, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_min_i16_e32 v5, v5, v10
+; GFX8-NEXT: v_min_i16_e32 v5, v5, v12
; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
-; GFX8-NEXT: v_add_u16_e32 v1, v1, v11
+; GFX8-NEXT: v_add_u16_e32 v1, v1, v10
; GFX8-NEXT: v_add_u16_sdwa v3, v7, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX8-NEXT: v_add_u16_e32 v2, v2, v13
+; GFX8-NEXT: v_add_u16_e32 v2, v2, v11
; GFX8-NEXT: v_add_u16_sdwa v3, v8, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v15
; GFX6-NEXT: v_max_i32_e32 v9, 0, v7
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v19, v10
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v17, v9
; GFX6-NEXT: v_max_i32_e32 v8, v10, v8
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3
; GFX6-NEXT: v_min_i32_e32 v8, v8, v9
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v5, 16, v5
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v4, 16, v4
; GFX6-NEXT: v_ashrrev_i32_e32 v7, 16, v7
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_and_b32_e32 v3, s4, v5
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v5
; GFX6-NEXT: v_ashrrev_i32_e32 v6, 16, v6
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v4
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v7
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX6-NEXT: v_and_b32_e32 v3, s4, v6
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-LABEL: v_saddsat_v8i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s5, 0x8000
-; GFX8-NEXT: v_min_i16_e32 v14, 0, v0
+; GFX8-NEXT: v_min_i16_e32 v13, 0, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_max_i16_e32 v12, 0, v0
-; GFX8-NEXT: v_sub_u16_e32 v14, s5, v14
-; GFX8-NEXT: v_sub_u16_e32 v12, s4, v12
-; GFX8-NEXT: v_max_i16_e32 v14, v14, v4
-; GFX8-NEXT: v_min_i16_e32 v16, 0, v8
-; GFX8-NEXT: v_min_i16_e32 v12, v14, v12
-; GFX8-NEXT: v_max_i16_e32 v14, 0, v8
-; GFX8-NEXT: v_sub_u16_e32 v16, s5, v16
-; GFX8-NEXT: v_sub_u16_e32 v14, s4, v14
-; GFX8-NEXT: v_max_i16_sdwa v4, v16, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_min_i16_e32 v16, 0, v1
+; GFX8-NEXT: v_sub_u16_e32 v13, 0x8000, v13
+; GFX8-NEXT: v_sub_u16_e32 v12, 0x7fff, v12
+; GFX8-NEXT: v_max_i16_e32 v13, v13, v4
+; GFX8-NEXT: v_min_i16_e32 v14, 0, v8
+; GFX8-NEXT: v_min_i16_e32 v12, v13, v12
+; GFX8-NEXT: v_max_i16_e32 v13, 0, v8
+; GFX8-NEXT: v_sub_u16_e32 v14, 0x8000, v14
+; GFX8-NEXT: v_sub_u16_e32 v13, 0x7fff, v13
+; GFX8-NEXT: v_max_i16_sdwa v4, v14, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_min_i16_e32 v14, 0, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX8-NEXT: v_min_i16_e32 v4, v4, v14
-; GFX8-NEXT: v_max_i16_e32 v14, 0, v1
-; GFX8-NEXT: v_sub_u16_e32 v16, s5, v16
-; GFX8-NEXT: v_sub_u16_e32 v14, s4, v14
-; GFX8-NEXT: v_max_i16_e32 v16, v16, v5
-; GFX8-NEXT: v_min_i16_e32 v17, 0, v9
-; GFX8-NEXT: v_min_i16_e32 v14, v16, v14
-; GFX8-NEXT: v_max_i16_e32 v16, 0, v9
-; GFX8-NEXT: v_sub_u16_e32 v17, s5, v17
-; GFX8-NEXT: v_mov_b32_e32 v15, 0xffff8000
-; GFX8-NEXT: v_sub_u16_e32 v16, s4, v16
-; GFX8-NEXT: v_max_i16_sdwa v5, v17, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_min_i16_e32 v17, 0, v2
+; GFX8-NEXT: v_min_i16_e32 v4, v4, v13
+; GFX8-NEXT: v_max_i16_e32 v13, 0, v1
+; GFX8-NEXT: v_sub_u16_e32 v14, 0x8000, v14
+; GFX8-NEXT: v_sub_u16_e32 v13, 0x7fff, v13
+; GFX8-NEXT: v_max_i16_e32 v14, v14, v5
+; GFX8-NEXT: v_min_i16_e32 v15, 0, v9
+; GFX8-NEXT: v_min_i16_e32 v13, v14, v13
+; GFX8-NEXT: v_max_i16_e32 v14, 0, v9
+; GFX8-NEXT: v_sub_u16_e32 v15, 0x8000, v15
+; GFX8-NEXT: v_sub_u16_e32 v14, 0x7fff, v14
+; GFX8-NEXT: v_max_i16_sdwa v5, v15, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_min_i16_e32 v15, 0, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX8-NEXT: v_mov_b32_e32 v13, 0x7fff
-; GFX8-NEXT: v_min_i16_e32 v5, v5, v16
-; GFX8-NEXT: v_max_i16_e32 v16, 0, v2
-; GFX8-NEXT: v_sub_u16_e32 v17, v15, v17
-; GFX8-NEXT: v_sub_u16_e32 v16, v13, v16
-; GFX8-NEXT: v_max_i16_e32 v17, v17, v6
-; GFX8-NEXT: v_min_i16_e32 v18, 0, v10
-; GFX8-NEXT: v_min_i16_e32 v16, v17, v16
-; GFX8-NEXT: v_max_i16_e32 v17, 0, v10
-; GFX8-NEXT: v_sub_u16_e32 v18, v15, v18
-; GFX8-NEXT: v_sub_u16_e32 v17, v13, v17
-; GFX8-NEXT: v_max_i16_sdwa v6, v18, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_min_i16_e32 v18, 0, v3
-; GFX8-NEXT: v_min_i16_e32 v6, v6, v17
-; GFX8-NEXT: v_max_i16_e32 v17, 0, v3
-; GFX8-NEXT: v_sub_u16_e32 v18, v15, v18
+; GFX8-NEXT: v_min_i16_e32 v5, v5, v14
+; GFX8-NEXT: v_max_i16_e32 v14, 0, v2
+; GFX8-NEXT: v_sub_u16_e32 v15, 0x8000, v15
+; GFX8-NEXT: v_sub_u16_e32 v14, 0x7fff, v14
+; GFX8-NEXT: v_max_i16_e32 v15, v15, v6
+; GFX8-NEXT: v_min_i16_e32 v16, 0, v10
+; GFX8-NEXT: v_min_i16_e32 v14, v15, v14
+; GFX8-NEXT: v_max_i16_e32 v15, 0, v10
+; GFX8-NEXT: v_sub_u16_e32 v16, 0x8000, v16
+; GFX8-NEXT: v_sub_u16_e32 v15, 0x7fff, v15
+; GFX8-NEXT: v_max_i16_sdwa v6, v16, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_min_i16_e32 v16, 0, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX8-NEXT: v_sub_u16_e32 v17, v13, v17
-; GFX8-NEXT: v_max_i16_e32 v18, v18, v7
-; GFX8-NEXT: v_min_i16_e32 v17, v18, v17
-; GFX8-NEXT: v_max_i16_e32 v18, 0, v11
-; GFX8-NEXT: v_sub_u16_e32 v13, v13, v18
-; GFX8-NEXT: v_min_i16_e32 v18, 0, v11
-; GFX8-NEXT: v_sub_u16_e32 v15, v15, v18
+; GFX8-NEXT: v_min_i16_e32 v6, v6, v15
+; GFX8-NEXT: v_max_i16_e32 v15, 0, v3
+; GFX8-NEXT: v_sub_u16_e32 v16, 0x8000, v16
+; GFX8-NEXT: v_sub_u16_e32 v15, 0x7fff, v15
+; GFX8-NEXT: v_max_i16_e32 v16, v16, v7
+; GFX8-NEXT: v_min_i16_e32 v17, 0, v11
+; GFX8-NEXT: v_min_i16_e32 v15, v16, v15
+; GFX8-NEXT: v_max_i16_e32 v16, 0, v11
+; GFX8-NEXT: v_sub_u16_e32 v17, 0x8000, v17
; GFX8-NEXT: v_add_u16_e32 v0, v0, v12
; GFX8-NEXT: v_add_u16_sdwa v4, v8, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_max_i16_sdwa v7, v15, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_sub_u16_e32 v16, 0x7fff, v16
+; GFX8-NEXT: v_max_i16_sdwa v7, v17, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX8-NEXT: v_add_u16_e32 v1, v1, v14
+; GFX8-NEXT: v_add_u16_e32 v1, v1, v13
; GFX8-NEXT: v_add_u16_sdwa v4, v9, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_min_i16_e32 v7, v7, v13
+; GFX8-NEXT: v_min_i16_e32 v7, v7, v16
; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX8-NEXT: v_add_u16_e32 v2, v2, v16
+; GFX8-NEXT: v_add_u16_e32 v2, v2, v14
; GFX8-NEXT: v_add_u16_sdwa v4, v10, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX8-NEXT: v_add_u16_e32 v3, v3, v17
+; GFX8-NEXT: v_add_u16_e32 v3, v3, v15
; GFX8-NEXT: v_add_u16_sdwa v4, v11, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GISEL-LABEL: v_sdiv_v2i32_pow2_shl_denom:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_movk_i32 s4, 0x1000
+; GISEL-NEXT: v_lshl_b32_e32 v2, 0x1000, v2
+; GISEL-NEXT: v_lshl_b32_e32 v3, 0x1000, v3
; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v0
; GISEL-NEXT: v_ashrrev_i32_e32 v5, 31, v1
-; GISEL-NEXT: v_lshl_b32_e32 v2, s4, v2
-; GISEL-NEXT: v_lshl_b32_e32 v3, s4, v3
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v5
; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v2
-; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v3
-; GISEL-NEXT: v_xor_b32_e32 v1, v1, v5
+; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v5
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
; GISEL-NEXT: v_xor_b32_e32 v4, v4, v6
; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v7
+; GISEL-NEXT: v_xor_b32_e32 v1, v1, v5
; GISEL-NEXT: v_xor_b32_e32 v5, v5, v7
; GISEL-NEXT: v_xor_b32_e32 v2, v2, v6
; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7
; CGP-LABEL: v_sdiv_v2i32_pow2_shl_denom:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_movk_i32 s4, 0x1000
+; CGP-NEXT: v_lshl_b32_e32 v2, 0x1000, v2
+; CGP-NEXT: v_lshl_b32_e32 v3, 0x1000, v3
; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v0
; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1
-; CGP-NEXT: v_lshl_b32_e32 v2, s4, v2
-; CGP-NEXT: v_lshl_b32_e32 v3, s4, v3
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v5
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v2
-; CGP-NEXT: v_xor_b32_e32 v0, v0, v4
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; CGP-NEXT: v_ashrrev_i32_e32 v7, 31, v3
-; CGP-NEXT: v_xor_b32_e32 v1, v1, v5
-; CGP-NEXT: v_xor_b32_e32 v4, v4, v6
+; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v5
+; CGP-NEXT: v_xor_b32_e32 v8, v4, v6
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT: v_xor_b32_e32 v5, v5, v7
+; CGP-NEXT: v_xor_b32_e32 v0, v0, v4
+; CGP-NEXT: v_xor_b32_e32 v4, v5, v7
; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7
+; CGP-NEXT: v_xor_b32_e32 v1, v1, v5
; CGP-NEXT: v_xor_b32_e32 v2, v2, v6
; CGP-NEXT: v_xor_b32_e32 v3, v3, v7
-; CGP-NEXT: v_cvt_f32_u32_e32 v6, v2
-; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v2
-; CGP-NEXT: v_cvt_f32_u32_e32 v8, v3
+; CGP-NEXT: v_cvt_f32_u32_e32 v5, v2
+; CGP-NEXT: v_sub_i32_e32 v6, vcc, 0, v2
+; CGP-NEXT: v_cvt_f32_u32_e32 v7, v3
; CGP-NEXT: v_sub_i32_e32 v9, vcc, 0, v3
-; CGP-NEXT: v_rcp_f32_e32 v6, v6
-; CGP-NEXT: v_rcp_f32_e32 v8, v8
-; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
-; CGP-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
-; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6
-; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
-; CGP-NEXT: v_mul_lo_u32 v7, v7, v6
-; CGP-NEXT: v_mul_lo_u32 v9, v9, v8
-; CGP-NEXT: v_mul_lo_u32 v10, 0, v7
-; CGP-NEXT: v_mul_hi_u32 v7, v6, v7
+; CGP-NEXT: v_rcp_f32_e32 v5, v5
+; CGP-NEXT: v_rcp_f32_e32 v7, v7
+; CGP-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5
+; CGP-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
+; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5
+; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
+; CGP-NEXT: v_mul_lo_u32 v6, v6, v5
+; CGP-NEXT: v_mul_lo_u32 v9, v9, v7
+; CGP-NEXT: v_mul_lo_u32 v10, 0, v6
+; CGP-NEXT: v_mul_hi_u32 v6, v5, v6
; CGP-NEXT: v_mul_lo_u32 v11, 0, v9
-; CGP-NEXT: v_mul_hi_u32 v9, v8, v9
-; CGP-NEXT: v_add_i32_e32 v7, vcc, v10, v7
+; CGP-NEXT: v_mul_hi_u32 v9, v7, v9
+; CGP-NEXT: v_add_i32_e32 v6, vcc, v10, v6
; CGP-NEXT: v_add_i32_e32 v9, vcc, v11, v9
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v7
-; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v9
-; CGP-NEXT: v_mul_lo_u32 v8, 0, v6
-; CGP-NEXT: v_mul_hi_u32 v6, v0, v6
-; CGP-NEXT: v_mul_lo_u32 v9, 0, v7
-; CGP-NEXT: v_mul_hi_u32 v7, v1, v7
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v6
-; CGP-NEXT: v_add_i32_e32 v7, vcc, v9, v7
-; CGP-NEXT: v_mul_lo_u32 v8, v6, v2
-; CGP-NEXT: v_add_i32_e32 v9, vcc, 1, v6
-; CGP-NEXT: v_mul_lo_u32 v10, v7, v3
-; CGP-NEXT: v_add_i32_e32 v11, vcc, 1, v7
-; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
+; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v6
+; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v9
+; CGP-NEXT: v_mul_lo_u32 v7, 0, v5
+; CGP-NEXT: v_mul_hi_u32 v5, v0, v5
+; CGP-NEXT: v_mul_lo_u32 v9, 0, v6
+; CGP-NEXT: v_mul_hi_u32 v6, v1, v6
+; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; CGP-NEXT: v_add_i32_e32 v6, vcc, v9, v6
+; CGP-NEXT: v_mul_lo_u32 v7, v5, v2
+; CGP-NEXT: v_add_i32_e32 v9, vcc, 1, v5
+; CGP-NEXT: v_mul_lo_u32 v10, v6, v3
+; CGP-NEXT: v_add_i32_e32 v11, vcc, 1, v6
+; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v10
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
-; CGP-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
-; CGP-NEXT: v_sub_i32_e64 v8, s[4:5], v0, v2
+; CGP-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
+; CGP-NEXT: v_sub_i32_e64 v7, s[4:5], v0, v2
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3
-; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v11, s[4:5]
+; CGP-NEXT: v_cndmask_b32_e64 v6, v6, v11, s[4:5]
; CGP-NEXT: v_sub_i32_e64 v9, s[6:7], v1, v3
-; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
-; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v6
+; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
+; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v5
; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[4:5]
-; CGP-NEXT: v_add_i32_e32 v9, vcc, 1, v7
+; CGP-NEXT: v_add_i32_e32 v9, vcc, 1, v6
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
-; CGP-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
-; CGP-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc
-; CGP-NEXT: v_xor_b32_e32 v0, v0, v4
-; CGP-NEXT: v_xor_b32_e32 v1, v1, v5
-; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
-; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v5
+; CGP-NEXT: v_cndmask_b32_e32 v1, v6, v9, vcc
+; CGP-NEXT: v_xor_b32_e32 v0, v0, v8
+; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
+; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
+; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
; CGP-NEXT: s_setpc_b64 s[30:31]
%shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
%r = sdiv <2 x i32> %x, %shl.y
; GISEL-LABEL: v_sdiv_i32_24bit:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s4, 0xffffff
-; GISEL-NEXT: v_and_b32_e32 v0, s4, v0
-; GISEL-NEXT: v_and_b32_e32 v1, s4, v1
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v0
; GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CGP-LABEL: v_sdiv_i32_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s4, 0xffffff
-; CGP-NEXT: v_and_b32_e32 v0, s4, v0
-; CGP-NEXT: v_and_b32_e32 v1, s4, v1
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
; CGP-NEXT: v_rcp_f32_e32 v2, v2
; GISEL-LABEL: v_sdiv_v2i32_24bit:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s4, 0xffffff
-; GISEL-NEXT: v_and_b32_e32 v0, s4, v0
-; GISEL-NEXT: v_and_b32_e32 v1, s4, v1
-; GISEL-NEXT: v_and_b32_e32 v2, s4, v2
-; GISEL-NEXT: v_and_b32_e32 v3, s4, v3
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GISEL-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GISEL-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v0
; GISEL-NEXT: v_ashrrev_i32_e32 v5, 31, v2
; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; CGP-LABEL: v_sdiv_v2i32_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s4, 0xffffff
-; CGP-NEXT: v_and_b32_e32 v0, s4, v0
-; CGP-NEXT: v_and_b32_e32 v1, s4, v1
-; CGP-NEXT: v_and_b32_e32 v2, s4, v2
-; CGP-NEXT: v_and_b32_e32 v3, s4, v3
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2
; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3
; CHECK-LABEL: v_sdiv_i64_pow2k_denom:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: s_movk_i32 s4, 0x1000
-; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s4
-; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0
-; CHECK-NEXT: s_movk_i32 s5, 0xf000
-; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000
-; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
-; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x1000
+; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0
+; CHECK-NEXT: s_movk_i32 s4, 0xf000
; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1
+; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v4
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v4, v4
; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4
-; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
-; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT: v_mul_lo_u32 v6, s5, v4
-; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
-; CHECK-NEXT: v_mul_hi_u32 v8, s5, v2
-; CHECK-NEXT: v_mul_lo_u32 v7, s5, v2
+; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3
+; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
+; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
+; CHECK-NEXT: v_mul_lo_u32 v6, s4, v4
+; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
+; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
+; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
-; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
-; CHECK-NEXT: v_mul_lo_u32 v6, s5, v4
-; CHECK-NEXT: v_mul_hi_u32 v8, s5, v2
-; CHECK-NEXT: v_mul_lo_u32 v7, s5, v2
+; CHECK-NEXT: v_mul_lo_u32 v6, s4, v4
+; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
+; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
+; CHECK-NEXT: s_movk_i32 s4, 0x1000
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CGP-LABEL: v_sdiv_v2i64_pow2k_denom:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_movk_i32 s6, 0x1000
-; CGP-NEXT: v_cvt_f32_u32_e32 v4, s6
-; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
-; CGP-NEXT: s_movk_i32 s7, 0xf000
-; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
-; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
-; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v4
+; CGP-NEXT: v_cvt_f32_u32_e32 v5, 0x1000
+; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
+; CGP-NEXT: s_movk_i32 s6, 0xf000
; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v1
+; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
+; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v5
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4
+; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
; CGP-NEXT: v_trunc_f32_e32 v6, v6
; CGP-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5
; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6
-; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
-; CGP-NEXT: v_mul_lo_u32 v7, -1, v5
-; CGP-NEXT: v_mul_lo_u32 v8, s7, v6
-; CGP-NEXT: v_mul_hi_u32 v10, s7, v5
-; CGP-NEXT: v_mul_lo_u32 v9, s7, v5
; CGP-NEXT: v_xor_b32_e32 v0, v0, v4
+; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
+; CGP-NEXT: v_mul_lo_u32 v7, -1, v5
+; CGP-NEXT: v_mul_lo_u32 v8, s6, v6
+; CGP-NEXT: v_mul_hi_u32 v10, s6, v5
+; CGP-NEXT: v_mul_lo_u32 v9, s6, v5
+; CGP-NEXT: s_movk_i32 s7, 0x1000
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_mul_lo_u32 v8, v6, v9
; CGP-NEXT: v_mul_lo_u32 v10, v5, v7
; CGP-NEXT: v_mul_hi_u32 v11, v5, v9
; CGP-NEXT: v_mul_hi_u32 v9, v6, v9
-; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
+; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CGP-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; CGP-NEXT: v_mul_lo_u32 v7, -1, v5
-; CGP-NEXT: v_mul_lo_u32 v8, s7, v6
-; CGP-NEXT: v_mul_hi_u32 v10, s7, v5
-; CGP-NEXT: v_mul_lo_u32 v9, s7, v5
+; CGP-NEXT: v_mul_lo_u32 v8, s6, v6
+; CGP-NEXT: v_mul_hi_u32 v10, s6, v5
+; CGP-NEXT: v_mul_lo_u32 v9, s6, v5
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_mul_lo_u32 v8, v6, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CGP-NEXT: v_mul_lo_u32 v8, 0, v7
-; CGP-NEXT: v_mul_lo_u32 v9, s6, v6
-; CGP-NEXT: v_mul_hi_u32 v11, s6, v7
-; CGP-NEXT: v_mul_lo_u32 v10, s6, v7
+; CGP-NEXT: v_mul_lo_u32 v9, s7, v6
+; CGP-NEXT: v_mul_hi_u32 v11, s7, v7
+; CGP-NEXT: v_mul_lo_u32 v10, s7, v7
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v10
; CGP-NEXT: v_addc_u32_e32 v11, vcc, 0, v10, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; CGP-NEXT: v_cvt_f32_u32_e32 v9, v5
+; CGP-NEXT: v_cvt_f32_u32_e32 v9, 0x1000
; CGP-NEXT: v_cndmask_b32_e32 v1, v10, v11, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; CGP-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
; CGP-NEXT: v_mul_lo_u32 v9, -1, v6
-; CGP-NEXT: v_mul_lo_u32 v10, s7, v8
-; CGP-NEXT: v_mul_hi_u32 v12, s7, v6
-; CGP-NEXT: v_mul_lo_u32 v11, s7, v6
+; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
+; CGP-NEXT: v_mul_hi_u32 v12, s6, v6
+; CGP-NEXT: v_mul_lo_u32 v11, s6, v6
; CGP-NEXT: v_xor_b32_e32 v0, v0, v4
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v10
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v9, -1, v6
-; CGP-NEXT: v_mul_lo_u32 v10, s7, v8
-; CGP-NEXT: v_mul_hi_u32 v12, s7, v6
-; CGP-NEXT: v_mul_lo_u32 v11, s7, v6
+; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
+; CGP-NEXT: v_mul_hi_u32 v12, s6, v6
+; CGP-NEXT: v_mul_lo_u32 v11, s6, v6
; CGP-NEXT: v_xor_b32_e32 v3, v3, v7
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CGP-NEXT: v_mul_lo_u32 v8, 0, v4
-; CGP-NEXT: v_mul_lo_u32 v9, s6, v6
-; CGP-NEXT: v_mul_hi_u32 v11, s6, v4
-; CGP-NEXT: v_mul_lo_u32 v10, s6, v4
+; CGP-NEXT: v_mul_lo_u32 v9, s7, v6
+; CGP-NEXT: v_mul_hi_u32 v11, s7, v4
+; CGP-NEXT: v_mul_lo_u32 v10, s7, v4
; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CHECK-LABEL: v_sdiv_i64_oddk_denom:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: s_mov_b32 s4, 0x12d8fb
-; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s4
-; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0
-; CHECK-NEXT: s_mov_b32 s5, 0xffed2705
-; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000
-; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
-; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x12d8fb
+; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0
+; CHECK-NEXT: s_mov_b32 s4, 0xffed2705
; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1
+; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v4
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v4, v4
; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4
-; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
-; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT: v_mul_lo_u32 v6, s5, v4
-; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
-; CHECK-NEXT: v_mul_hi_u32 v8, s5, v2
-; CHECK-NEXT: v_mul_lo_u32 v7, s5, v2
+; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3
+; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
+; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
+; CHECK-NEXT: v_mul_lo_u32 v6, s4, v4
+; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
+; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
+; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
-; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
-; CHECK-NEXT: v_mul_lo_u32 v6, s5, v4
-; CHECK-NEXT: v_mul_hi_u32 v8, s5, v2
-; CHECK-NEXT: v_mul_lo_u32 v7, s5, v2
+; CHECK-NEXT: v_mul_lo_u32 v6, s4, v4
+; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
+; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
+; CHECK-NEXT: s_mov_b32 s4, 0x12d8fb
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CGP-LABEL: v_sdiv_v2i64_oddk_denom:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s6, 0x12d8fb
-; CGP-NEXT: v_cvt_f32_u32_e32 v4, s6
-; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
-; CGP-NEXT: s_mov_b32 s7, 0xffed2705
-; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
-; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
-; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v4
+; CGP-NEXT: v_cvt_f32_u32_e32 v5, 0x12d8fb
+; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
+; CGP-NEXT: s_mov_b32 s6, 0xffed2705
; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v1
+; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
+; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v5
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4
+; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
; CGP-NEXT: v_trunc_f32_e32 v6, v6
; CGP-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5
; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6
-; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
-; CGP-NEXT: v_mul_lo_u32 v7, -1, v5
-; CGP-NEXT: v_mul_lo_u32 v8, s7, v6
-; CGP-NEXT: v_mul_hi_u32 v10, s7, v5
-; CGP-NEXT: v_mul_lo_u32 v9, s7, v5
; CGP-NEXT: v_xor_b32_e32 v0, v0, v4
+; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
+; CGP-NEXT: v_mul_lo_u32 v7, -1, v5
+; CGP-NEXT: v_mul_lo_u32 v8, s6, v6
+; CGP-NEXT: v_mul_hi_u32 v10, s6, v5
+; CGP-NEXT: v_mul_lo_u32 v9, s6, v5
+; CGP-NEXT: s_mov_b32 s7, 0x12d8fb
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_mul_lo_u32 v8, v6, v9
; CGP-NEXT: v_mul_lo_u32 v10, v5, v7
; CGP-NEXT: v_mul_hi_u32 v11, v5, v9
; CGP-NEXT: v_mul_hi_u32 v9, v6, v9
-; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
+; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CGP-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; CGP-NEXT: v_mul_lo_u32 v7, -1, v5
-; CGP-NEXT: v_mul_lo_u32 v8, s7, v6
-; CGP-NEXT: v_mul_hi_u32 v10, s7, v5
-; CGP-NEXT: v_mul_lo_u32 v9, s7, v5
+; CGP-NEXT: v_mul_lo_u32 v8, s6, v6
+; CGP-NEXT: v_mul_hi_u32 v10, s6, v5
+; CGP-NEXT: v_mul_lo_u32 v9, s6, v5
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_mul_lo_u32 v8, v6, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CGP-NEXT: v_mul_lo_u32 v8, 0, v7
-; CGP-NEXT: v_mul_lo_u32 v9, s6, v6
-; CGP-NEXT: v_mul_hi_u32 v11, s6, v7
-; CGP-NEXT: v_mul_lo_u32 v10, s6, v7
+; CGP-NEXT: v_mul_lo_u32 v9, s7, v6
+; CGP-NEXT: v_mul_hi_u32 v11, s7, v7
+; CGP-NEXT: v_mul_lo_u32 v10, s7, v7
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v10
; CGP-NEXT: v_addc_u32_e32 v11, vcc, 0, v10, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; CGP-NEXT: v_cvt_f32_u32_e32 v9, v5
+; CGP-NEXT: v_cvt_f32_u32_e32 v9, 0x12d8fb
; CGP-NEXT: v_cndmask_b32_e32 v1, v10, v11, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; CGP-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
; CGP-NEXT: v_mul_lo_u32 v9, -1, v6
-; CGP-NEXT: v_mul_lo_u32 v10, s7, v8
-; CGP-NEXT: v_mul_hi_u32 v12, s7, v6
-; CGP-NEXT: v_mul_lo_u32 v11, s7, v6
+; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
+; CGP-NEXT: v_mul_hi_u32 v12, s6, v6
+; CGP-NEXT: v_mul_lo_u32 v11, s6, v6
; CGP-NEXT: v_xor_b32_e32 v0, v0, v4
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v10
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v9, -1, v6
-; CGP-NEXT: v_mul_lo_u32 v10, s7, v8
-; CGP-NEXT: v_mul_hi_u32 v12, s7, v6
-; CGP-NEXT: v_mul_lo_u32 v11, s7, v6
+; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
+; CGP-NEXT: v_mul_hi_u32 v12, s6, v6
+; CGP-NEXT: v_mul_lo_u32 v11, s6, v6
; CGP-NEXT: v_xor_b32_e32 v3, v3, v7
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CGP-NEXT: v_mul_lo_u32 v8, 0, v4
-; CGP-NEXT: v_mul_lo_u32 v9, s6, v6
-; CGP-NEXT: v_mul_hi_u32 v11, s6, v4
-; CGP-NEXT: v_mul_lo_u32 v10, s6, v4
+; CGP-NEXT: v_mul_lo_u32 v9, s7, v6
+; CGP-NEXT: v_mul_hi_u32 v11, s7, v4
+; CGP-NEXT: v_mul_lo_u32 v10, s7, v4
; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; GISEL-LABEL: v_sdiv_i64_24bit:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s4, 0xffffff
-; GISEL-NEXT: v_and_b32_e32 v1, s4, v2
+; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v2
; GISEL-NEXT: v_cvt_f32_u32_e32 v2, v1
; GISEL-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
-; GISEL-NEXT: v_and_b32_e32 v0, s4, v0
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GISEL-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GISEL-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-LABEL: v_sdiv_i64_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s4, 0xffffff
-; CGP-NEXT: v_and_b32_e32 v1, s4, v2
+; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v2
; CGP-NEXT: v_cvt_f32_i32_e32 v1, v1
-; CGP-NEXT: v_and_b32_e32 v0, s4, v0
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; CGP-NEXT: v_cvt_f32_i32_e32 v0, v0
; CGP-NEXT: v_rcp_f32_e32 v2, v1
; CGP-NEXT: v_mul_f32_e32 v2, v0, v2
; GISEL-LABEL: v_sdiv_v2i64_24bit:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s6, 0xffffff
-; GISEL-NEXT: v_and_b32_e32 v1, s6, v4
+; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v4
; GISEL-NEXT: v_add_i32_e32 v1, vcc, 0, v1
; GISEL-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v1
; GISEL-NEXT: v_subb_u32_e32 v9, vcc, 0, v3, vcc
; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
-; GISEL-NEXT: v_and_b32_e32 v5, s6, v0
-; GISEL-NEXT: v_and_b32_e32 v6, s6, v6
+; GISEL-NEXT: v_and_b32_e32 v5, 0xffffff, v0
+; GISEL-NEXT: v_and_b32_e32 v6, 0xffffff, v6
; GISEL-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v4
; GISEL-NEXT: v_mul_f32_e32 v4, 0x2f800000, v0
; GISEL-NEXT: v_trunc_f32_e32 v4, v4
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v0, v12
; GISEL-NEXT: v_mul_lo_u32 v12, v4, v11
; GISEL-NEXT: v_mul_lo_u32 v13, v7, v10
-; GISEL-NEXT: v_and_b32_e32 v0, s6, v2
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v2
; GISEL-NEXT: v_mul_hi_u32 v2, v7, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v4, v11
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; CGP-LABEL: v_sdiv_v2i64_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s4, 0xffffff
-; CGP-NEXT: v_and_b32_e32 v1, s4, v4
+; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v4
; CGP-NEXT: v_cvt_f32_i32_e32 v1, v1
-; CGP-NEXT: v_and_b32_e32 v0, s4, v0
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; CGP-NEXT: v_cvt_f32_i32_e32 v0, v0
-; CGP-NEXT: v_and_b32_e32 v4, s4, v6
+; CGP-NEXT: v_and_b32_e32 v4, 0xffffff, v6
; CGP-NEXT: v_rcp_f32_e32 v3, v1
; CGP-NEXT: v_cvt_f32_i32_e32 v4, v4
-; CGP-NEXT: v_and_b32_e32 v2, s4, v2
+; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; CGP-NEXT: v_cvt_f32_i32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v3, v0, v3
; CGP-NEXT: v_trunc_f32_e32 v3, v3
; GFX8-LABEL: sdivrem_v4i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x4f7ffffe
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_ashr_i32 s2, s12, 31
; GFX8-NEXT: s_add_i32 s0, s13, s16
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_xor_b32 s13, s0, s16
-; GFX8-NEXT: v_cvt_f32_u32_e32 v3, s13
+; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s13
; GFX8-NEXT: s_ashr_i32 s12, s8, 31
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_add_i32 s0, s8, s12
; GFX8-NEXT: s_xor_b32 s0, s0, s12
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX8-NEXT: v_mul_lo_u32 v1, s1, v0
+; GFX8-NEXT: s_sub_i32 s8, 0, s13
; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0
-; GFX8-NEXT: v_mul_f32_e32 v1, v3, v2
+; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX8-NEXT: v_mul_lo_u32 v3, v0, s3
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v0
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s0, v3
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s3, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v0
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s3, v3
-; GFX8-NEXT: s_sub_i32 s0, 0, s13
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GFX8-NEXT: v_mul_lo_u32 v4, s0, v1
+; GFX8-NEXT: v_mul_lo_u32 v2, v0, s3
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s0, v2
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s3, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s3, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX8-NEXT: v_mul_lo_u32 v3, s8, v1
; GFX8-NEXT: s_xor_b32 s0, s12, s2
; GFX8-NEXT: s_ashr_i32 s2, s9, 31
; GFX8-NEXT: s_add_i32 s1, s9, s2
-; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX8-NEXT: s_xor_b32 s1, s1, s2
; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0
-; GFX8-NEXT: v_xor_b32_e32 v3, s12, v3
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v4
+; GFX8-NEXT: v_xor_b32_e32 v2, s12, v2
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: v_mul_hi_u32 v1, s1, v1
; GFX8-NEXT: s_ashr_i32 s3, s14, 31
; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s0, v0
-; GFX8-NEXT: v_mul_lo_u32 v5, v1, s13
-; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s12, v3
+; GFX8-NEXT: v_mul_lo_u32 v3, v1, s13
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s12, v2
; GFX8-NEXT: s_add_i32 s0, s14, s3
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s1, v5
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, 1, v1
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s13, v3
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s1, v3
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s13, v2
; GFX8-NEXT: s_xor_b32 s8, s0, s3
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX8-NEXT: v_cvt_f32_u32_e32 v3, s8
+; GFX8-NEXT: v_subrev_u32_e64 v5, s[0:1], s13, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 1, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s13, v2
+; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX8-NEXT: v_cvt_f32_u32_e32 v5, s8
-; GFX8-NEXT: v_subrev_u32_e64 v6, s[0:1], s13, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v5, v5
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, 1, v1
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s13, v3
-; GFX8-NEXT: v_mul_f32_e32 v5, v5, v2
-; GFX8-NEXT: v_cvt_u32_f32_e32 v5, v5
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX8-NEXT: v_subrev_u32_e64 v6, s[0:1], s13, v3
+; GFX8-NEXT: v_subrev_u32_e64 v5, s[0:1], s13, v2
; GFX8-NEXT: s_sub_i32 s0, 0, s8
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
-; GFX8-NEXT: v_mul_lo_u32 v6, s0, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX8-NEXT: v_mul_lo_u32 v5, s0, v3
; GFX8-NEXT: s_ashr_i32 s9, s10, 31
; GFX8-NEXT: s_add_i32 s1, s10, s9
; GFX8-NEXT: s_xor_b32 s1, s1, s9
-; GFX8-NEXT: v_mul_hi_u32 v6, v5, v6
+; GFX8-NEXT: v_mul_hi_u32 v5, v3, v5
; GFX8-NEXT: s_xor_b32 s0, s2, s16
-; GFX8-NEXT: v_xor_b32_e32 v3, s2, v3
+; GFX8-NEXT: v_xor_b32_e32 v2, s2, v2
; GFX8-NEXT: v_xor_b32_e32 v1, s0, v1
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v6
-; GFX8-NEXT: v_mul_hi_u32 v6, s1, v5
-; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s2, v3
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5
+; GFX8-NEXT: v_mul_hi_u32 v3, s1, v3
+; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s2, v2
; GFX8-NEXT: s_ashr_i32 s2, s15, 31
-; GFX8-NEXT: v_mul_lo_u32 v7, v6, s8
+; GFX8-NEXT: v_mul_lo_u32 v6, v3, s8
; GFX8-NEXT: v_subrev_u32_e32 v1, vcc, s0, v1
; GFX8-NEXT: s_add_i32 s0, s15, s2
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s1, v7
-; GFX8-NEXT: v_add_u32_e32 v7, vcc, 1, v6
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s1, v6
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, 1, v3
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v2
; GFX8-NEXT: s_xor_b32 s10, s0, s2
-; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; GFX8-NEXT: v_cvt_f32_u32_e32 v7, s10
-; GFX8-NEXT: v_subrev_u32_e64 v8, s[0:1], s8, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v7, v7
-; GFX8-NEXT: v_add_u32_e32 v8, vcc, 1, v6
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
-; GFX8-NEXT: v_mul_f32_e32 v2, v7, v2
-; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX8-NEXT: v_subrev_u32_e64 v7, s[0:1], s8, v3
-; GFX8-NEXT: s_sub_i32 s0, 0, s10
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX8-NEXT: v_cvt_f32_u32_e32 v6, s10
+; GFX8-NEXT: v_subrev_u32_e64 v7, s[0:1], s8, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, 1, v3
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v2
+; GFX8-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
+; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
-; GFX8-NEXT: v_mul_lo_u32 v7, s0, v2
+; GFX8-NEXT: v_subrev_u32_e64 v7, s[0:1], s8, v2
+; GFX8-NEXT: s_sub_i32 s0, 0, s10
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v2, v7, vcc
+; GFX8-NEXT: v_mul_lo_u32 v2, s0, v6
; GFX8-NEXT: s_xor_b32 s0, s9, s3
; GFX8-NEXT: s_ashr_i32 s3, s11, 31
; GFX8-NEXT: s_add_i32 s1, s11, s3
-; GFX8-NEXT: v_mul_hi_u32 v7, v2, v7
-; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; GFX8-NEXT: v_mul_hi_u32 v2, v6, v2
; GFX8-NEXT: s_xor_b32 s1, s1, s3
-; GFX8-NEXT: v_xor_b32_e32 v6, s0, v6
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7
-; GFX8-NEXT: v_mul_hi_u32 v7, s1, v2
-; GFX8-NEXT: v_xor_b32_e32 v3, s9, v3
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s0, v6
-; GFX8-NEXT: v_mul_lo_u32 v8, v7, s10
+; GFX8-NEXT: v_xor_b32_e32 v3, s0, v3
+; GFX8-NEXT: v_add_u32_e32 v2, vcc, v6, v2
+; GFX8-NEXT: v_mul_hi_u32 v8, s1, v2
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s0, v3
+; GFX8-NEXT: v_xor_b32_e32 v3, s9, v7
+; GFX8-NEXT: v_mul_lo_u32 v7, v8, s10
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s9, v3
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s1, v8
-; GFX8-NEXT: v_add_u32_e32 v8, vcc, 1, v7
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s1, v7
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, 1, v8
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s10, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX8-NEXT: v_subrev_u32_e64 v8, s[0:1], s10, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GFX8-NEXT: v_add_u32_e32 v8, vcc, 1, v7
; GFX9-LABEL: sdivrem_v4i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x4f7ffffe
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s6, s12, 31
; GFX9-NEXT: s_add_i32 s0, s12, s6
; GFX9-NEXT: s_xor_b32 s7, s0, s6
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GFX9-NEXT: s_ashr_i32 s5, s13, 31
-; GFX9-NEXT: s_add_i32 s12, s13, s5
+; GFX9-NEXT: s_ashr_i32 s4, s13, 31
+; GFX9-NEXT: s_add_i32 s5, s13, s4
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_xor_b32 s12, s12, s5
-; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s12
+; GFX9-NEXT: s_xor_b32 s5, s5, s4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s5
; GFX9-NEXT: s_sub_i32 s13, 0, s7
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX9-NEXT: s_ashr_i32 s4, s8, 31
-; GFX9-NEXT: s_add_i32 s8, s8, s4
-; GFX9-NEXT: v_mul_lo_u32 v3, s13, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX9-NEXT: s_ashr_i32 s12, s8, 31
+; GFX9-NEXT: s_add_i32 s8, s8, s12
+; GFX9-NEXT: v_mul_lo_u32 v2, s13, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: s_xor_b32 s8, s8, s4
-; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3
-; GFX9-NEXT: s_sub_i32 s16, 0, s12
+; GFX9-NEXT: s_xor_b32 s8, s8, s12
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: s_sub_i32 s13, 0, s5
+; GFX9-NEXT: v_mul_lo_u32 v3, s13, v1
; GFX9-NEXT: s_ashr_i32 s13, s9, 31
-; GFX9-NEXT: s_add_i32 s9, s9, s13
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v0, s8, v0
-; GFX9-NEXT: v_mul_lo_u32 v3, s16, v1
+; GFX9-NEXT: v_mul_hi_u32 v2, v1, v3
+; GFX9-NEXT: s_add_i32 s9, s9, s13
; GFX9-NEXT: s_xor_b32 s9, s9, s13
-; GFX9-NEXT: s_xor_b32 s6, s4, s6
-; GFX9-NEXT: v_mul_lo_u32 v4, v0, s7
-; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
-; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
-; GFX9-NEXT: s_xor_b32 s5, s13, s5
-; GFX9-NEXT: v_sub_u32_e32 v4, s8, v4
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v5, s7, v4
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, v0, s7
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u32_e32 v2, 1, v0
; GFX9-NEXT: v_mul_hi_u32 v1, s9, v1
-; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v5, s7, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; GFX9-NEXT: v_mul_lo_u32 v5, v1, s12
-; GFX9-NEXT: v_xor_b32_e32 v3, s4, v3
+; GFX9-NEXT: v_sub_u32_e32 v3, s8, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v2, s7, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v2
+; GFX9-NEXT: s_xor_b32 s6, s12, s6
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, s6, v0
-; GFX9-NEXT: v_subrev_u32_e32 v4, s4, v3
-; GFX9-NEXT: s_ashr_i32 s4, s14, 31
+; GFX9-NEXT: v_mul_lo_u32 v3, v1, s5
; GFX9-NEXT: v_subrev_u32_e32 v0, s6, v0
-; GFX9-NEXT: s_add_i32 s6, s14, s4
-; GFX9-NEXT: s_xor_b32 s6, s6, s4
-; GFX9-NEXT: v_sub_u32_e32 v3, s9, v5
-; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s6
-; GFX9-NEXT: v_add_u32_e32 v6, 1, v1
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5
-; GFX9-NEXT: v_subrev_u32_e32 v6, s12, v3
+; GFX9-NEXT: s_ashr_i32 s6, s14, 31
+; GFX9-NEXT: s_add_i32 s7, s14, s6
+; GFX9-NEXT: v_xor_b32_e32 v2, s12, v2
+; GFX9-NEXT: s_xor_b32 s7, s7, s6
+; GFX9-NEXT: v_subrev_u32_e32 v4, s12, v2
+; GFX9-NEXT: v_sub_u32_e32 v2, s9, v3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s7
+; GFX9-NEXT: v_add_u32_e32 v5, 1, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX9-NEXT: v_subrev_u32_e32 v5, s5, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX9-NEXT: v_add_u32_e32 v5, 1, v1
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v2
+; GFX9-NEXT: s_sub_i32 s8, 0, s7
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX9-NEXT: v_mul_lo_u32 v5, s8, v3
+; GFX9-NEXT: s_xor_b32 s4, s13, s4
+; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1
+; GFX9-NEXT: v_subrev_u32_e32 v1, s4, v1
+; GFX9-NEXT: s_ashr_i32 s4, s15, 31
+; GFX9-NEXT: s_add_i32 s9, s15, s4
+; GFX9-NEXT: v_mul_hi_u32 v5, v3, v5
+; GFX9-NEXT: s_xor_b32 s9, s9, s4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s9
+; GFX9-NEXT: v_subrev_u32_e32 v6, s5, v2
+; GFX9-NEXT: s_ashr_i32 s5, s10, 31
+; GFX9-NEXT: s_add_i32 s8, s10, s5
+; GFX9-NEXT: s_xor_b32 s8, s8, s5
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, s8, v3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX9-NEXT: v_xor_b32_e32 v2, s13, v2
+; GFX9-NEXT: v_mul_lo_u32 v6, v3, s7
+; GFX9-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
+; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX9-NEXT: v_subrev_u32_e32 v5, s13, v2
+; GFX9-NEXT: v_sub_u32_e32 v2, s8, v6
+; GFX9-NEXT: s_sub_i32 s8, 0, s9
+; GFX9-NEXT: v_mul_lo_u32 v8, s8, v7
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
-; GFX9-NEXT: v_add_u32_e32 v6, 1, v1
-; GFX9-NEXT: v_mul_f32_e32 v5, v5, v2
-; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
-; GFX9-NEXT: s_sub_i32 s7, 0, s6
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX9-NEXT: v_mul_lo_u32 v6, s7, v5
-; GFX9-NEXT: v_xor_b32_e32 v1, s5, v1
-; GFX9-NEXT: v_subrev_u32_e32 v1, s5, v1
-; GFX9-NEXT: s_ashr_i32 s5, s15, 31
-; GFX9-NEXT: s_add_i32 s9, s15, s5
-; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6
-; GFX9-NEXT: s_xor_b32 s9, s9, s5
-; GFX9-NEXT: v_cvt_f32_u32_e32 v8, s9
-; GFX9-NEXT: s_ashr_i32 s7, s10, 31
-; GFX9-NEXT: s_add_i32 s8, s10, s7
+; GFX9-NEXT: v_subrev_u32_e32 v6, s7, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX9-NEXT: v_mul_hi_u32 v8, v7, v8
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v6, s7, v2
+; GFX9-NEXT: s_ashr_i32 s7, s11, 31
+; GFX9-NEXT: s_add_i32 s8, s11, s7
; GFX9-NEXT: s_xor_b32 s8, s8, s7
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v6
-; GFX9-NEXT: v_mul_hi_u32 v6, s8, v5
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v8
-; GFX9-NEXT: v_subrev_u32_e32 v7, s12, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
-; GFX9-NEXT: v_mul_lo_u32 v7, v6, s6
-; GFX9-NEXT: v_mul_f32_e32 v2, v8, v2
-; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX9-NEXT: v_xor_b32_e32 v3, s13, v3
-; GFX9-NEXT: v_subrev_u32_e32 v5, s13, v3
-; GFX9-NEXT: v_sub_u32_e32 v3, s8, v7
-; GFX9-NEXT: s_sub_i32 s8, 0, s9
-; GFX9-NEXT: v_mul_lo_u32 v8, s8, v2
-; GFX9-NEXT: v_add_u32_e32 v7, 1, v6
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v7, s6, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
-; GFX9-NEXT: v_mul_hi_u32 v8, v2, v8
-; GFX9-NEXT: v_add_u32_e32 v7, 1, v6
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v7, s6, v3
-; GFX9-NEXT: s_ashr_i32 s6, s11, 31
-; GFX9-NEXT: s_add_i32 s8, s11, s6
-; GFX9-NEXT: s_xor_b32 s8, s8, s6
-; GFX9-NEXT: v_add_u32_e32 v2, v2, v8
-; GFX9-NEXT: v_mul_hi_u32 v8, s8, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX9-NEXT: v_add_u32_e32 v7, v7, v8
+; GFX9-NEXT: v_mul_hi_u32 v7, s8, v7
+; GFX9-NEXT: s_xor_b32 s6, s5, s6
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v2, v6, vcc
+; GFX9-NEXT: v_xor_b32_e32 v2, s6, v3
+; GFX9-NEXT: v_mul_lo_u32 v3, v7, s9
+; GFX9-NEXT: v_add_u32_e32 v8, 1, v7
; GFX9-NEXT: s_xor_b32 s4, s7, s4
-; GFX9-NEXT: v_xor_b32_e32 v3, s7, v3
-; GFX9-NEXT: v_mul_lo_u32 v7, v8, s9
-; GFX9-NEXT: v_xor_b32_e32 v2, s4, v6
-; GFX9-NEXT: v_subrev_u32_e32 v6, s7, v3
-; GFX9-NEXT: v_subrev_u32_e32 v2, s4, v2
-; GFX9-NEXT: v_sub_u32_e32 v3, s8, v7
-; GFX9-NEXT: v_add_u32_e32 v7, 1, v8
+; GFX9-NEXT: v_subrev_u32_e32 v2, s6, v2
+; GFX9-NEXT: v_sub_u32_e32 v3, s8, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GFX9-NEXT: v_subrev_u32_e32 v8, s9, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GFX9-NEXT: v_add_u32_e32 v8, 1, v7
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GFX9-NEXT: v_subrev_u32_e32 v8, s9, v3
-; GFX9-NEXT: s_xor_b32 s4, s6, s5
; GFX9-NEXT: v_cndmask_b32_e32 v8, v3, v8, vcc
; GFX9-NEXT: v_xor_b32_e32 v3, s4, v7
+; GFX9-NEXT: v_xor_b32_e32 v6, s5, v6
; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v3
-; GFX9-NEXT: v_xor_b32_e32 v7, s6, v8
+; GFX9-NEXT: v_xor_b32_e32 v7, s7, v8
; GFX9-NEXT: v_mov_b32_e32 v8, 0
-; GFX9-NEXT: v_subrev_u32_e32 v7, s6, v7
+; GFX9-NEXT: v_subrev_u32_e32 v6, s5, v6
+; GFX9-NEXT: v_subrev_u32_e32 v7, s7, v7
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1]
; GFX9-NEXT: global_store_dwordx4 v8, v[4:7], s[2:3]
; GFX8-NEXT: v_xor_b32_e32 v1, s0, v1
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: v_subrev_u32_e32 v1, vcc, s0, v1
-; GFX8-NEXT: s_movk_i32 s0, 0xff
-; GFX8-NEXT: v_and_b32_e32 v1, s0, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX8-NEXT: v_xor_b32_e32 v3, s2, v3
; GFX8-NEXT: v_or_b32_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s2, v3
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: flat_store_short v[0:1], v4
-; GFX8-NEXT: v_and_b32_e32 v0, s0, v3
+; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v3
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX8-NEXT: v_or_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1
; GFX9-NEXT: v_subrev_u32_e32 v4, s5, v3
; GFX9-NEXT: v_subrev_u32_e32 v1, s4, v1
-; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GFX9-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX9-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX9-NEXT: v_subrev_u32_e32 v0, s6, v0
; GFX9-NEXT: v_xor_b32_e32 v3, s11, v3
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX9-NEXT: v_xor_b32_e32 v2, s10, v2
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_short v1, v0, s[0:1]
-; GFX9-NEXT: v_and_b32_e32 v0, s4, v3
+; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v3
; GFX9-NEXT: v_subrev_u32_e32 v2, s10, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: v_xor_b32_e32 v1, s0, v1
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: v_subrev_u32_e32 v1, vcc, s0, v1
-; GFX8-NEXT: s_mov_b32 s0, 0xffff
; GFX8-NEXT: v_xor_b32_e32 v3, s2, v3
-; GFX8-NEXT: v_and_b32_e32 v1, s0, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s2, v3
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX8-NEXT: v_or_b32_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v0, s0, v3
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_or_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
define amdgpu_kernel void @sdivrem_i27(i27 addrspace(1)* %out0, i27 addrspace(1)* %out1, i27 %x, i27 %y) {
; GFX8-LABEL: sdivrem_i27:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x10
-; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
-; GFX8-NEXT: s_mov_b32 s9, 0x7ffffff
+; GFX8-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_bfe_i32 s1, s1, 0x1b0000
-; GFX8-NEXT: s_ashr_i32 s2, s1, 31
-; GFX8-NEXT: s_add_i32 s1, s1, s2
-; GFX8-NEXT: s_xor_b32 s3, s1, s2
-; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s3
-; GFX8-NEXT: s_sub_i32 s1, 0, s3
-; GFX8-NEXT: s_bfe_i32 s0, s0, 0x1b0000
-; GFX8-NEXT: s_ashr_i32 s8, s0, 31
+; GFX8-NEXT: s_bfe_i32 s0, s7, 0x1b0000
+; GFX8-NEXT: s_ashr_i32 s7, s0, 31
+; GFX8-NEXT: s_add_i32 s0, s0, s7
+; GFX8-NEXT: s_xor_b32 s8, s0, s7
+; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s8
+; GFX8-NEXT: s_sub_i32 s0, 0, s8
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX8-NEXT: s_add_i32 s0, s0, s8
-; GFX8-NEXT: s_xor_b32 s0, s0, s8
-; GFX8-NEXT: s_xor_b32 s2, s8, s2
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_lo_u32 v1, s1, v0
+; GFX8-NEXT: v_mul_lo_u32 v1, s0, v0
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX8-NEXT: s_bfe_i32 s4, s6, 0x1b0000
+; GFX8-NEXT: s_ashr_i32 s5, s4, 31
; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX8-NEXT: s_add_i32 s4, s4, s5
+; GFX8-NEXT: s_xor_b32 s4, s4, s5
+; GFX8-NEXT: s_xor_b32 s6, s5, s7
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
-; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0
-; GFX8-NEXT: v_mul_lo_u32 v1, v0, s3
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v0
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s0, v1
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT: v_subrev_u32_e64 v2, s[0:1], s3, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v0
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT: v_subrev_u32_e64 v2, s[0:1], s3, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX8-NEXT: v_xor_b32_e32 v0, s2, v0
-; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s2, v0
-; GFX8-NEXT: v_xor_b32_e32 v1, s8, v1
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s8, v1
-; GFX8-NEXT: v_and_b32_e32 v3, s9, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: flat_store_dword v[0:1], v3
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NEXT: v_and_b32_e32 v2, s9, v2
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mul_hi_u32 v2, s4, v0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mul_lo_u32 v3, v2, s8
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v2
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s4, v3
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s8, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v2
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s8, v3
+; GFX8-NEXT: v_xor_b32_e32 v2, s6, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT: v_xor_b32_e32 v3, s5, v3
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7ffffff, v2
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s5, v3
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7ffffff, v3
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_lo_u32 v1, s1, v0
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GFX9-NEXT: s_xor_b32 s5, s8, s6
-; GFX9-NEXT: s_mov_b32 s4, 0x7ffffff
+; GFX9-NEXT: s_xor_b32 s4, s8, s6
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_mul_hi_u32 v0, s9, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX9-NEXT: v_xor_b32_e32 v0, s5, v0
-; GFX9-NEXT: v_subrev_u32_e32 v0, s5, v0
+; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0
+; GFX9-NEXT: v_subrev_u32_e32 v0, s4, v0
; GFX9-NEXT: v_xor_b32_e32 v1, s8, v1
; GFX9-NEXT: v_subrev_u32_e32 v1, s8, v1
-; GFX9-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7ffffff, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
-; GFX9-NEXT: v_and_b32_e32 v0, s4, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7ffffff, v1
; GFX9-NEXT: global_store_dword v2, v0, s[2:3]
; GFX9-NEXT: s_endpgm
;
; GFX7-LABEL: v_shl_v2i64_zext_v2i32:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_brev_b32 s4, -4
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v1
+; GFX7-NEXT: v_and_b32_e32 v2, 0x3fffffff, v1
; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0x3fffffff, v0
; GFX7-NEXT: v_mov_b32_e32 v3, v1
; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
; GFX7-NEXT: v_lshl_b64 v[2:3], v[2:3], 2
; GFX8-LABEL: v_shl_v2i64_zext_v2i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s4, -4
-; GFX8-NEXT: v_and_b32_e32 v2, s4, v1
+; GFX8-NEXT: v_and_b32_e32 v2, 0x3fffffff, v1
; GFX8-NEXT: v_mov_b32_e32 v1, 0
-; GFX8-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0x3fffffff, v0
; GFX8-NEXT: v_mov_b32_e32 v3, v1
; GFX8-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
; GFX8-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]
; GFX9-LABEL: v_shl_v2i64_zext_v2i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_brev_b32 s4, -4
-; GFX9-NEXT: v_and_b32_e32 v2, s4, v1
+; GFX9-NEXT: v_and_b32_e32 v2, 0x3fffffff, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0x3fffffff, v0
; GFX9-NEXT: v_mov_b32_e32 v3, v1
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]
; GFX7-LABEL: v_shl_v2i64_sext_v2i32:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_brev_b32 s4, -8
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0x1fffffff, v0
+; GFX7-NEXT: v_and_b32_e32 v2, 0x1fffffff, v1
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX7-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
; GFX8-LABEL: v_shl_v2i64_sext_v2i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s4, -8
-; GFX8-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX8-NEXT: v_and_b32_e32 v2, s4, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0x1fffffff, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 0x1fffffff, v1
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
; GFX9-LABEL: v_shl_v2i64_sext_v2i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_brev_b32 s4, -8
-; GFX9-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX9-NEXT: v_and_b32_e32 v2, s4, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0x1fffffff, v0
+; GFX9-NEXT: v_and_b32_e32 v2, 0x1fffffff, v1
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
; GFX7-LABEL: v_shl_v2i32_zext_v2i16:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
; GFX7-NEXT: v_and_b32_e32 v0, 0x3fff3fff, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX7-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 2, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
; GFX6-LABEL: v_shl_v2i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v2, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
define amdgpu_ps float @shl_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {
; GFX6-LABEL: shl_v2i16_sv:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_mov_b32 s2, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshl_b32_e32 v1, s1, v1
; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0
-; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog
; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s0, v0
; GFX6-NEXT: s_and_b32 s0, s1, 0xffff
-; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v1, s0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog
; GFX6-LABEL: v_shl_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v4, v0
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v5
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v4, v1
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v6
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v7
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v3, v4, v3
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX6-LABEL: v_shl_v8i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v8
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v8, v0
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v9
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v9
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v8, v1
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v10
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v10
; GFX6-NEXT: v_lshlrev_b32_e32 v2, v8, v2
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v11
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v11
; GFX6-NEXT: v_lshlrev_b32_e32 v3, v8, v3
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v12
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v12
; GFX6-NEXT: v_lshlrev_b32_e32 v4, v8, v4
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v13
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_mov_b32_e32 v16, 0xffff
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v13
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v5, v8, v5
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v14
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v14
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v6, v8, v6
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v15
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v15
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, v2, v16
-; GFX6-NEXT: v_and_b32_e32 v2, v3, v16
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v7, v8, v7
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_and_b32_e32 v3, v5, v16
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v5
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_and_b32_e32 v2, v4, v16
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_and_b32_e32 v4, v7, v16
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX6-NEXT: v_and_b32_e32 v3, v6, v16
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GISEL-LABEL: v_srem_v2i32_pow2_shl_denom:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_movk_i32 s4, 0x1000
+; GISEL-NEXT: v_lshl_b32_e32 v2, 0x1000, v2
+; GISEL-NEXT: v_lshl_b32_e32 v3, 0x1000, v3
; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v0
; GISEL-NEXT: v_ashrrev_i32_e32 v5, 31, v1
-; GISEL-NEXT: v_lshl_b32_e32 v2, s4, v2
-; GISEL-NEXT: v_lshl_b32_e32 v3, s4, v3
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v5
; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v2
-; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v3
-; GISEL-NEXT: v_xor_b32_e32 v1, v1, v5
+; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v5
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v7
+; GISEL-NEXT: v_xor_b32_e32 v1, v1, v5
; GISEL-NEXT: v_xor_b32_e32 v2, v2, v6
; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7
; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v2
; CGP-LABEL: v_srem_v2i32_pow2_shl_denom:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_movk_i32 s4, 0x1000
+; CGP-NEXT: v_lshl_b32_e32 v2, 0x1000, v2
+; CGP-NEXT: v_lshl_b32_e32 v3, 0x1000, v3
; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v0
; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1
-; CGP-NEXT: v_lshl_b32_e32 v2, s4, v2
-; CGP-NEXT: v_lshl_b32_e32 v3, s4, v3
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v5
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v2
-; CGP-NEXT: v_xor_b32_e32 v0, v0, v4
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; CGP-NEXT: v_ashrrev_i32_e32 v7, 31, v3
-; CGP-NEXT: v_xor_b32_e32 v1, v1, v5
+; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v5
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; CGP-NEXT: v_xor_b32_e32 v0, v0, v4
; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7
+; CGP-NEXT: v_xor_b32_e32 v1, v1, v5
; CGP-NEXT: v_xor_b32_e32 v2, v2, v6
; CGP-NEXT: v_xor_b32_e32 v3, v3, v7
; CGP-NEXT: v_cvt_f32_u32_e32 v6, v2
; GISEL-LABEL: v_srem_i32_24bit:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s4, 0xffffff
-; GISEL-NEXT: v_and_b32_e32 v0, s4, v0
-; GISEL-NEXT: v_and_b32_e32 v1, s4, v1
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v0
; GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CGP-LABEL: v_srem_i32_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s4, 0xffffff
-; CGP-NEXT: v_and_b32_e32 v0, s4, v0
-; CGP-NEXT: v_and_b32_e32 v1, s4, v1
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
; CGP-NEXT: v_rcp_f32_e32 v2, v2
; GISEL-LABEL: v_srem_v2i32_24bit:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s4, 0xffffff
-; GISEL-NEXT: v_and_b32_e32 v0, s4, v0
-; GISEL-NEXT: v_and_b32_e32 v1, s4, v1
-; GISEL-NEXT: v_and_b32_e32 v2, s4, v2
-; GISEL-NEXT: v_and_b32_e32 v3, s4, v3
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GISEL-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GISEL-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v0
; GISEL-NEXT: v_ashrrev_i32_e32 v5, 31, v2
; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; CGP-LABEL: v_srem_v2i32_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s4, 0xffffff
-; CGP-NEXT: v_and_b32_e32 v0, s4, v0
-; CGP-NEXT: v_and_b32_e32 v1, s4, v1
-; CGP-NEXT: v_and_b32_e32 v2, s4, v2
-; CGP-NEXT: v_and_b32_e32 v3, s4, v3
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2
; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3
; CHECK-LABEL: v_srem_i64_pow2k_denom:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: s_movk_i32 s4, 0x1000
-; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s4
-; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0
-; CHECK-NEXT: s_movk_i32 s5, 0xf000
-; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000
-; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
-; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x1000
+; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0
+; CHECK-NEXT: s_movk_i32 s4, 0xf000
; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1
+; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v4
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v4, v4
; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4
-; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
-; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT: v_mul_lo_u32 v6, s5, v4
-; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
-; CHECK-NEXT: v_mul_hi_u32 v8, s5, v2
-; CHECK-NEXT: v_mul_lo_u32 v7, s5, v2
+; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3
+; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
+; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
+; CHECK-NEXT: v_mul_lo_u32 v6, s4, v4
+; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
+; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
+; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
-; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
-; CHECK-NEXT: v_mul_lo_u32 v6, s5, v4
-; CHECK-NEXT: v_mul_hi_u32 v8, s5, v2
-; CHECK-NEXT: v_mul_lo_u32 v7, s5, v2
+; CHECK-NEXT: v_mul_lo_u32 v6, s4, v4
+; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
+; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
+; CHECK-NEXT: s_movk_i32 s4, 0x1000
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CGP-LABEL: v_srem_v2i64_pow2k_denom:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_movk_i32 s6, 0x1000
-; CGP-NEXT: v_cvt_f32_u32_e32 v4, s6
-; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
-; CGP-NEXT: s_movk_i32 s7, 0xf000
-; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
-; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
-; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v4
+; CGP-NEXT: v_cvt_f32_u32_e32 v5, 0x1000
+; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
+; CGP-NEXT: s_movk_i32 s6, 0xf000
; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v1
+; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
+; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v5
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4
+; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
; CGP-NEXT: v_trunc_f32_e32 v6, v6
; CGP-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5
; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6
-; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
-; CGP-NEXT: v_mul_lo_u32 v7, -1, v5
-; CGP-NEXT: v_mul_lo_u32 v8, s7, v6
-; CGP-NEXT: v_mul_hi_u32 v10, s7, v5
-; CGP-NEXT: v_mul_lo_u32 v9, s7, v5
; CGP-NEXT: v_xor_b32_e32 v0, v0, v4
+; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
+; CGP-NEXT: v_mul_lo_u32 v7, -1, v5
+; CGP-NEXT: v_mul_lo_u32 v8, s6, v6
+; CGP-NEXT: v_mul_hi_u32 v10, s6, v5
+; CGP-NEXT: v_mul_lo_u32 v9, s6, v5
+; CGP-NEXT: s_movk_i32 s7, 0x1000
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_mul_lo_u32 v8, v6, v9
; CGP-NEXT: v_mul_lo_u32 v10, v5, v7
; CGP-NEXT: v_mul_hi_u32 v11, v5, v9
; CGP-NEXT: v_mul_hi_u32 v9, v6, v9
-; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
+; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CGP-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; CGP-NEXT: v_mul_lo_u32 v7, -1, v5
-; CGP-NEXT: v_mul_lo_u32 v8, s7, v6
-; CGP-NEXT: v_mul_hi_u32 v10, s7, v5
-; CGP-NEXT: v_mul_lo_u32 v9, s7, v5
+; CGP-NEXT: v_mul_lo_u32 v8, s6, v6
+; CGP-NEXT: v_mul_hi_u32 v10, s6, v5
+; CGP-NEXT: v_mul_lo_u32 v9, s6, v5
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_mul_lo_u32 v8, v6, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CGP-NEXT: v_mul_lo_u32 v8, 0, v7
-; CGP-NEXT: v_mul_lo_u32 v6, s6, v6
-; CGP-NEXT: v_mul_lo_u32 v9, s6, v7
-; CGP-NEXT: v_mul_hi_u32 v7, s6, v7
+; CGP-NEXT: v_mul_lo_u32 v6, s7, v6
+; CGP-NEXT: v_mul_lo_u32 v9, s7, v7
+; CGP-NEXT: v_mul_hi_u32 v7, s7, v7
; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v9
; CGP-NEXT: v_sub_i32_e32 v10, vcc, v8, v5
; CGP-NEXT: v_subbrev_u32_e32 v11, vcc, 0, v1, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
-; CGP-NEXT: v_cvt_f32_u32_e32 v9, v5
+; CGP-NEXT: v_cvt_f32_u32_e32 v9, 0x1000
; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v7
; CGP-NEXT: v_mul_lo_u32 v9, -1, v6
-; CGP-NEXT: v_mul_lo_u32 v10, s7, v8
-; CGP-NEXT: v_mul_hi_u32 v12, s7, v6
-; CGP-NEXT: v_mul_lo_u32 v11, s7, v6
+; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
+; CGP-NEXT: v_mul_hi_u32 v12, s6, v6
+; CGP-NEXT: v_mul_lo_u32 v11, s6, v6
; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v10
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v9, -1, v6
-; CGP-NEXT: v_mul_lo_u32 v10, s7, v8
-; CGP-NEXT: v_mul_hi_u32 v12, s7, v6
-; CGP-NEXT: v_mul_lo_u32 v11, s7, v6
+; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
+; CGP-NEXT: v_mul_hi_u32 v12, s6, v6
+; CGP-NEXT: v_mul_lo_u32 v11, s6, v6
; CGP-NEXT: v_xor_b32_e32 v2, v2, v7
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CGP-NEXT: v_mul_lo_u32 v8, 0, v4
-; CGP-NEXT: v_mul_lo_u32 v6, s6, v6
-; CGP-NEXT: v_mul_lo_u32 v9, s6, v4
-; CGP-NEXT: v_mul_hi_u32 v4, s6, v4
+; CGP-NEXT: v_mul_lo_u32 v6, s7, v6
+; CGP-NEXT: v_mul_lo_u32 v9, s7, v4
+; CGP-NEXT: v_mul_hi_u32 v4, s7, v4
; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CHECK-LABEL: v_srem_i64_oddk_denom:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: s_mov_b32 s4, 0x12d8fb
-; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s4
-; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0
-; CHECK-NEXT: s_mov_b32 s5, 0xffed2705
-; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000
-; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
-; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x12d8fb
+; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0
+; CHECK-NEXT: s_mov_b32 s4, 0xffed2705
; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1
+; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v4
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v4, v4
; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4
-; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
-; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT: v_mul_lo_u32 v6, s5, v4
-; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
-; CHECK-NEXT: v_mul_hi_u32 v8, s5, v2
-; CHECK-NEXT: v_mul_lo_u32 v7, s5, v2
+; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3
+; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
+; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
+; CHECK-NEXT: v_mul_lo_u32 v6, s4, v4
+; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
+; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
+; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
-; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
-; CHECK-NEXT: v_mul_lo_u32 v6, s5, v4
-; CHECK-NEXT: v_mul_hi_u32 v8, s5, v2
-; CHECK-NEXT: v_mul_lo_u32 v7, s5, v2
+; CHECK-NEXT: v_mul_lo_u32 v6, s4, v4
+; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
+; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
+; CHECK-NEXT: s_mov_b32 s4, 0x12d8fb
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CGP-LABEL: v_srem_v2i64_oddk_denom:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s6, 0x12d8fb
-; CGP-NEXT: v_cvt_f32_u32_e32 v4, s6
-; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
-; CGP-NEXT: s_mov_b32 s7, 0xffed2705
-; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
-; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
-; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v4
+; CGP-NEXT: v_cvt_f32_u32_e32 v5, 0x12d8fb
+; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
+; CGP-NEXT: s_mov_b32 s6, 0xffed2705
; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v1
+; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
+; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v5
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4
+; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
; CGP-NEXT: v_trunc_f32_e32 v6, v6
; CGP-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5
; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6
-; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
-; CGP-NEXT: v_mul_lo_u32 v7, -1, v5
-; CGP-NEXT: v_mul_lo_u32 v8, s7, v6
-; CGP-NEXT: v_mul_hi_u32 v10, s7, v5
-; CGP-NEXT: v_mul_lo_u32 v9, s7, v5
; CGP-NEXT: v_xor_b32_e32 v0, v0, v4
+; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
+; CGP-NEXT: v_mul_lo_u32 v7, -1, v5
+; CGP-NEXT: v_mul_lo_u32 v8, s6, v6
+; CGP-NEXT: v_mul_hi_u32 v10, s6, v5
+; CGP-NEXT: v_mul_lo_u32 v9, s6, v5
+; CGP-NEXT: s_mov_b32 s7, 0x12d8fb
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_mul_lo_u32 v8, v6, v9
; CGP-NEXT: v_mul_lo_u32 v10, v5, v7
; CGP-NEXT: v_mul_hi_u32 v11, v5, v9
; CGP-NEXT: v_mul_hi_u32 v9, v6, v9
-; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
+; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CGP-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; CGP-NEXT: v_mul_lo_u32 v7, -1, v5
-; CGP-NEXT: v_mul_lo_u32 v8, s7, v6
-; CGP-NEXT: v_mul_hi_u32 v10, s7, v5
-; CGP-NEXT: v_mul_lo_u32 v9, s7, v5
+; CGP-NEXT: v_mul_lo_u32 v8, s6, v6
+; CGP-NEXT: v_mul_hi_u32 v10, s6, v5
+; CGP-NEXT: v_mul_lo_u32 v9, s6, v5
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_mul_lo_u32 v8, v6, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CGP-NEXT: v_mul_lo_u32 v8, 0, v7
-; CGP-NEXT: v_mul_lo_u32 v6, s6, v6
-; CGP-NEXT: v_mul_lo_u32 v9, s6, v7
-; CGP-NEXT: v_mul_hi_u32 v7, s6, v7
+; CGP-NEXT: v_mul_lo_u32 v6, s7, v6
+; CGP-NEXT: v_mul_lo_u32 v9, s7, v7
+; CGP-NEXT: v_mul_hi_u32 v7, s7, v7
; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v9
; CGP-NEXT: v_sub_i32_e32 v10, vcc, v8, v5
; CGP-NEXT: v_subbrev_u32_e32 v11, vcc, 0, v1, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
-; CGP-NEXT: v_cvt_f32_u32_e32 v9, v5
+; CGP-NEXT: v_cvt_f32_u32_e32 v9, 0x12d8fb
; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v7
; CGP-NEXT: v_mul_lo_u32 v9, -1, v6
-; CGP-NEXT: v_mul_lo_u32 v10, s7, v8
-; CGP-NEXT: v_mul_hi_u32 v12, s7, v6
-; CGP-NEXT: v_mul_lo_u32 v11, s7, v6
+; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
+; CGP-NEXT: v_mul_hi_u32 v12, s6, v6
+; CGP-NEXT: v_mul_lo_u32 v11, s6, v6
; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v10
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v9, -1, v6
-; CGP-NEXT: v_mul_lo_u32 v10, s7, v8
-; CGP-NEXT: v_mul_hi_u32 v12, s7, v6
-; CGP-NEXT: v_mul_lo_u32 v11, s7, v6
+; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
+; CGP-NEXT: v_mul_hi_u32 v12, s6, v6
+; CGP-NEXT: v_mul_lo_u32 v11, s6, v6
; CGP-NEXT: v_xor_b32_e32 v2, v2, v7
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CGP-NEXT: v_mul_lo_u32 v8, 0, v4
-; CGP-NEXT: v_mul_lo_u32 v6, s6, v6
-; CGP-NEXT: v_mul_lo_u32 v9, s6, v4
-; CGP-NEXT: v_mul_hi_u32 v4, s6, v4
+; CGP-NEXT: v_mul_lo_u32 v6, s7, v6
+; CGP-NEXT: v_mul_lo_u32 v9, s7, v4
+; CGP-NEXT: v_mul_hi_u32 v4, s7, v4
; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; GISEL-LABEL: v_srem_i64_24bit:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s4, 0xffffff
-; GISEL-NEXT: v_and_b32_e32 v1, s4, v2
+; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v2
; GISEL-NEXT: v_cvt_f32_u32_e32 v2, v1
; GISEL-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
-; GISEL-NEXT: v_and_b32_e32 v0, s4, v0
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GISEL-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GISEL-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-LABEL: v_srem_i64_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s4, 0xffffff
-; CGP-NEXT: v_and_b32_e32 v1, s4, v2
+; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v2
; CGP-NEXT: v_cvt_f32_i32_e32 v2, v1
-; CGP-NEXT: v_and_b32_e32 v0, s4, v0
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; CGP-NEXT: v_cvt_f32_i32_e32 v3, v0
; CGP-NEXT: v_rcp_f32_e32 v4, v2
; CGP-NEXT: v_mul_f32_e32 v4, v3, v4
; GISEL-LABEL: v_srem_v2i64_24bit:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s6, 0xffffff
-; GISEL-NEXT: v_and_b32_e32 v1, s6, v4
+; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v4
; GISEL-NEXT: v_add_i32_e32 v1, vcc, 0, v1
; GISEL-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v1
; GISEL-NEXT: v_subb_u32_e32 v9, vcc, 0, v3, vcc
; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
-; GISEL-NEXT: v_and_b32_e32 v5, s6, v0
-; GISEL-NEXT: v_and_b32_e32 v6, s6, v6
+; GISEL-NEXT: v_and_b32_e32 v5, 0xffffff, v0
+; GISEL-NEXT: v_and_b32_e32 v6, 0xffffff, v6
; GISEL-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v4
; GISEL-NEXT: v_mul_f32_e32 v4, 0x2f800000, v0
; GISEL-NEXT: v_trunc_f32_e32 v4, v4
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v0, v12
; GISEL-NEXT: v_mul_lo_u32 v12, v4, v11
; GISEL-NEXT: v_mul_lo_u32 v13, v7, v10
-; GISEL-NEXT: v_and_b32_e32 v0, s6, v2
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v2
; GISEL-NEXT: v_mul_hi_u32 v2, v7, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v4, v11
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; CGP-LABEL: v_srem_v2i64_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s4, 0xffffff
-; CGP-NEXT: v_and_b32_e32 v1, s4, v4
+; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v4
; CGP-NEXT: v_cvt_f32_i32_e32 v3, v1
-; CGP-NEXT: v_and_b32_e32 v0, s4, v0
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; CGP-NEXT: v_cvt_f32_i32_e32 v4, v0
-; CGP-NEXT: v_and_b32_e32 v6, s4, v6
+; CGP-NEXT: v_and_b32_e32 v6, 0xffffff, v6
; CGP-NEXT: v_rcp_f32_e32 v5, v3
-; CGP-NEXT: v_and_b32_e32 v2, s4, v2
+; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; CGP-NEXT: v_mul_f32_e32 v5, v4, v5
; CGP-NEXT: v_trunc_f32_e32 v5, v5
; CGP-NEXT: v_mad_f32 v4, -v5, v3, v4
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 24, v1
-; GFX6-NEXT: v_mov_b32_e32 v2, 0xff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0
-; GFX6-NEXT: v_and_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: v_mov_b32_e32 v2, 8
; GFX8-NEXT: v_lshrrev_b32_sdwa v3, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_max_i16_e32 v4, -1, v0
; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX8-NEXT: s_movk_i32 s5, 0x8000
-; GFX8-NEXT: v_subrev_u16_e32 v4, s4, v4
+; GFX8-NEXT: v_subrev_u16_e32 v4, 0x7fff, v4
; GFX8-NEXT: v_min_i16_e32 v5, -1, v0
-; GFX8-NEXT: v_subrev_u16_e32 v5, s5, v5
+; GFX8-NEXT: v_subrev_u16_e32 v5, 0x8000, v5
; GFX8-NEXT: v_max_i16_e32 v1, v4, v1
; GFX8-NEXT: v_min_i16_e32 v1, v1, v5
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
; GFX8-NEXT: v_max_i16_e32 v1, -1, v3
-; GFX8-NEXT: v_subrev_u16_e32 v1, s4, v1
+; GFX8-NEXT: v_subrev_u16_e32 v1, 0x7fff, v1
; GFX8-NEXT: v_min_i16_e32 v4, -1, v3
-; GFX8-NEXT: v_subrev_u16_e32 v4, s5, v4
+; GFX8-NEXT: v_subrev_u16_e32 v4, 0x8000, v4
; GFX8-NEXT: v_max_i16_e32 v1, v1, v2
; GFX8-NEXT: v_min_i16_e32 v1, v1, v4
; GFX8-NEXT: v_sub_u16_e32 v1, v3, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 24, v7
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v9
; GFX6-NEXT: v_min_i32_e32 v6, -1, v3
-; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v11
; GFX6-NEXT: v_max_i32_e32 v4, v5, v4
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 24, v2
; GFX6-NEXT: v_min_i32_e32 v4, v4, v6
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
+; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 24, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 24, v0
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_max_i16_e32 v8, -1, v0
; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX8-NEXT: s_movk_i32 s5, 0x8000
-; GFX8-NEXT: v_subrev_u16_e32 v8, s4, v8
-; GFX8-NEXT: v_min_i16_e32 v10, -1, v0
-; GFX8-NEXT: v_subrev_u16_e32 v10, s5, v10
+; GFX8-NEXT: v_subrev_u16_e32 v8, 0x7fff, v8
+; GFX8-NEXT: v_min_i16_e32 v9, -1, v0
+; GFX8-NEXT: v_subrev_u16_e32 v9, 0x8000, v9
; GFX8-NEXT: v_max_i16_e32 v1, v8, v1
-; GFX8-NEXT: v_min_i16_e32 v1, v1, v10
+; GFX8-NEXT: v_min_i16_e32 v1, v1, v9
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
; GFX8-NEXT: v_max_i16_e32 v1, -1, v3
-; GFX8-NEXT: v_subrev_u16_e32 v1, s4, v1
+; GFX8-NEXT: v_subrev_u16_e32 v1, 0x7fff, v1
; GFX8-NEXT: v_min_i16_e32 v8, -1, v3
-; GFX8-NEXT: v_subrev_u16_e32 v8, s5, v8
+; GFX8-NEXT: v_subrev_u16_e32 v8, 0x8000, v8
; GFX8-NEXT: v_max_i16_e32 v1, v1, v2
; GFX8-NEXT: v_lshlrev_b16_e32 v2, 8, v4
-; GFX8-NEXT: v_mov_b32_e32 v9, 0x7fff
; GFX8-NEXT: v_min_i16_e32 v1, v1, v8
; GFX8-NEXT: v_max_i16_e32 v4, -1, v2
; GFX8-NEXT: v_sub_u16_e32 v1, v3, v1
; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v6
-; GFX8-NEXT: v_sub_u16_e32 v4, v4, v9
+; GFX8-NEXT: v_subrev_u16_e32 v4, 0x7fff, v4
; GFX8-NEXT: v_min_i16_e32 v6, -1, v2
-; GFX8-NEXT: v_subrev_u16_e32 v6, s5, v6
+; GFX8-NEXT: v_subrev_u16_e32 v6, 0x8000, v6
; GFX8-NEXT: v_max_i16_e32 v3, v4, v3
; GFX8-NEXT: v_min_i16_e32 v3, v3, v6
; GFX8-NEXT: v_sub_u16_e32 v2, v2, v3
; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v5
; GFX8-NEXT: v_max_i16_e32 v5, -1, v3
; GFX8-NEXT: v_lshlrev_b16_e32 v4, 8, v7
-; GFX8-NEXT: v_sub_u16_e32 v5, v5, v9
+; GFX8-NEXT: v_subrev_u16_e32 v5, 0x7fff, v5
; GFX8-NEXT: v_min_i16_e32 v6, -1, v3
; GFX8-NEXT: v_subrev_u16_e32 v6, 0x8000, v6
; GFX8-NEXT: v_max_i16_e32 v4, v5, v4
; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v2
-; GFX9-NEXT: v_and_b32_e32 v2, s4, v1
+; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: s_mov_b32 s5, 24
; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v2
-; GFX9-NEXT: v_and_b32_e32 v2, s0, v1
+; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX8-LABEL: v_ssubsat_v2i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_max_i16_e32 v3, -1, v0
-; GFX8-NEXT: s_movk_i32 s5, 0x8000
-; GFX8-NEXT: v_subrev_u16_e32 v3, s4, v3
+; GFX8-NEXT: v_subrev_u16_e32 v3, 0x7fff, v3
; GFX8-NEXT: v_min_i16_e32 v4, -1, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX8-NEXT: v_subrev_u16_e32 v4, s5, v4
+; GFX8-NEXT: v_subrev_u16_e32 v4, 0x8000, v4
; GFX8-NEXT: v_max_i16_e32 v3, v3, v1
; GFX8-NEXT: v_min_i16_e32 v3, v3, v4
; GFX8-NEXT: v_max_i16_e32 v4, -1, v2
-; GFX8-NEXT: v_subrev_u16_e32 v4, s4, v4
+; GFX8-NEXT: v_subrev_u16_e32 v4, 0x7fff, v4
; GFX8-NEXT: v_min_i16_e32 v5, -1, v2
-; GFX8-NEXT: v_subrev_u16_e32 v5, s5, v5
+; GFX8-NEXT: v_subrev_u16_e32 v5, 0x8000, v5
; GFX8-NEXT: v_max_i16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_min_i16_e32 v1, v1, v5
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v3
; GFX6-NEXT: v_min_i32_e32 v1, s2, v1
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
-; GFX6-NEXT: s_mov_b32 s0, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
-; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
-; GFX6-NEXT: s_mov_b32 s0, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
-; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: ssubsat_v2i16_vs:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_movk_i32 s2, 0x7fff
; GFX8-NEXT: v_max_i16_e32 v2, -1, v0
-; GFX8-NEXT: s_movk_i32 s3, 0x8000
-; GFX8-NEXT: v_subrev_u16_e32 v2, s2, v2
+; GFX8-NEXT: v_subrev_u16_e32 v2, 0x7fff, v2
; GFX8-NEXT: v_min_i16_e32 v3, -1, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX8-NEXT: v_subrev_u16_e32 v3, s3, v3
+; GFX8-NEXT: v_subrev_u16_e32 v3, 0x8000, v3
; GFX8-NEXT: v_max_i16_e32 v2, s0, v2
; GFX8-NEXT: v_min_i16_e32 v2, v2, v3
; GFX8-NEXT: v_max_i16_e32 v3, -1, v1
; GFX8-NEXT: s_lshr_b32 s1, s0, 16
-; GFX8-NEXT: v_subrev_u16_e32 v3, s2, v3
+; GFX8-NEXT: v_subrev_u16_e32 v3, 0x7fff, v3
; GFX8-NEXT: v_min_i16_e32 v4, -1, v1
-; GFX8-NEXT: v_subrev_u16_e32 v4, s3, v4
+; GFX8-NEXT: v_subrev_u16_e32 v4, 0x8000, v4
; GFX8-NEXT: v_max_i16_e32 v3, s1, v3
; GFX8-NEXT: v_min_i16_e32 v3, v3, v4
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v2
; GFX6-NEXT: v_max_i32_e32 v4, v5, v4
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: v_min_i32_e32 v4, v4, v6
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-LABEL: v_ssubsat_v4i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_max_i16_e32 v6, -1, v0
-; GFX8-NEXT: s_movk_i32 s5, 0x8000
-; GFX8-NEXT: v_subrev_u16_e32 v6, s4, v6
+; GFX8-NEXT: v_subrev_u16_e32 v6, 0x7fff, v6
; GFX8-NEXT: v_min_i16_e32 v7, -1, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX8-NEXT: v_subrev_u16_e32 v7, s5, v7
+; GFX8-NEXT: v_subrev_u16_e32 v7, 0x8000, v7
; GFX8-NEXT: v_max_i16_e32 v6, v6, v2
; GFX8-NEXT: v_min_i16_e32 v6, v6, v7
; GFX8-NEXT: v_max_i16_e32 v7, -1, v4
-; GFX8-NEXT: v_subrev_u16_e32 v7, s4, v7
+; GFX8-NEXT: v_subrev_u16_e32 v7, 0x7fff, v7
; GFX8-NEXT: v_min_i16_e32 v8, -1, v4
-; GFX8-NEXT: v_subrev_u16_e32 v8, s5, v8
+; GFX8-NEXT: v_subrev_u16_e32 v8, 0x8000, v8
; GFX8-NEXT: v_max_i16_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_max_i16_e32 v7, -1, v1
; GFX8-NEXT: v_min_i16_e32 v2, v2, v8
-; GFX8-NEXT: v_subrev_u16_e32 v7, s4, v7
+; GFX8-NEXT: v_subrev_u16_e32 v7, 0x7fff, v7
; GFX8-NEXT: v_min_i16_e32 v8, -1, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX8-NEXT: v_subrev_u16_e32 v8, s5, v8
+; GFX8-NEXT: v_subrev_u16_e32 v8, 0x8000, v8
; GFX8-NEXT: v_max_i16_e32 v7, v7, v3
; GFX8-NEXT: v_min_i16_e32 v7, v7, v8
; GFX8-NEXT: v_max_i16_e32 v8, -1, v5
-; GFX8-NEXT: v_subrev_u16_e32 v8, s4, v8
+; GFX8-NEXT: v_subrev_u16_e32 v8, 0x7fff, v8
; GFX8-NEXT: v_min_i16_e32 v9, -1, v5
-; GFX8-NEXT: v_subrev_u16_e32 v9, s5, v9
+; GFX8-NEXT: v_subrev_u16_e32 v9, 0x8000, v9
; GFX8-NEXT: v_max_i16_sdwa v3, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_min_i16_e32 v3, v3, v9
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v6
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v8, v15
; GFX6-NEXT: v_max_i32_e32 v6, v7, v6
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_min_i32_e32 v6, v6, v8
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v6
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v5, 16, v5
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v4, 16, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_and_b32_e32 v3, s4, v5
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v5
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v4
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-LABEL: v_ssubsat_v6i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_max_i16_e32 v9, -1, v0
-; GFX8-NEXT: s_movk_i32 s5, 0x8000
-; GFX8-NEXT: v_subrev_u16_e32 v9, s4, v9
-; GFX8-NEXT: v_min_i16_e32 v11, -1, v0
+; GFX8-NEXT: v_subrev_u16_e32 v9, 0x7fff, v9
+; GFX8-NEXT: v_min_i16_e32 v10, -1, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX8-NEXT: v_subrev_u16_e32 v11, s5, v11
+; GFX8-NEXT: v_subrev_u16_e32 v10, 0x8000, v10
; GFX8-NEXT: v_max_i16_e32 v9, v9, v3
-; GFX8-NEXT: v_min_i16_e32 v9, v9, v11
-; GFX8-NEXT: v_max_i16_e32 v11, -1, v6
-; GFX8-NEXT: v_subrev_u16_e32 v11, s4, v11
-; GFX8-NEXT: v_min_i16_e32 v13, -1, v6
-; GFX8-NEXT: v_subrev_u16_e32 v13, s5, v13
-; GFX8-NEXT: v_max_i16_sdwa v3, v11, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_max_i16_e32 v11, -1, v1
-; GFX8-NEXT: v_min_i16_e32 v3, v3, v13
-; GFX8-NEXT: v_subrev_u16_e32 v11, s4, v11
-; GFX8-NEXT: v_min_i16_e32 v13, -1, v1
+; GFX8-NEXT: v_min_i16_e32 v9, v9, v10
+; GFX8-NEXT: v_max_i16_e32 v10, -1, v6
+; GFX8-NEXT: v_subrev_u16_e32 v10, 0x7fff, v10
+; GFX8-NEXT: v_min_i16_e32 v11, -1, v6
+; GFX8-NEXT: v_subrev_u16_e32 v11, 0x8000, v11
+; GFX8-NEXT: v_max_i16_sdwa v3, v10, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_max_i16_e32 v10, -1, v1
+; GFX8-NEXT: v_min_i16_e32 v3, v3, v11
+; GFX8-NEXT: v_subrev_u16_e32 v10, 0x7fff, v10
+; GFX8-NEXT: v_min_i16_e32 v11, -1, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX8-NEXT: v_subrev_u16_e32 v13, s5, v13
-; GFX8-NEXT: v_max_i16_e32 v11, v11, v4
-; GFX8-NEXT: v_min_i16_e32 v11, v11, v13
-; GFX8-NEXT: v_max_i16_e32 v13, -1, v7
-; GFX8-NEXT: v_subrev_u16_e32 v13, s4, v13
-; GFX8-NEXT: v_min_i16_e32 v14, -1, v7
-; GFX8-NEXT: v_mov_b32_e32 v10, 0x7fff
-; GFX8-NEXT: v_subrev_u16_e32 v14, s5, v14
-; GFX8-NEXT: v_max_i16_sdwa v4, v13, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_max_i16_e32 v13, -1, v2
-; GFX8-NEXT: v_mov_b32_e32 v12, 0xffff8000
-; GFX8-NEXT: v_min_i16_e32 v4, v4, v14
-; GFX8-NEXT: v_sub_u16_e32 v13, v13, v10
-; GFX8-NEXT: v_min_i16_e32 v14, -1, v2
+; GFX8-NEXT: v_subrev_u16_e32 v11, 0x8000, v11
+; GFX8-NEXT: v_max_i16_e32 v10, v10, v4
+; GFX8-NEXT: v_min_i16_e32 v10, v10, v11
+; GFX8-NEXT: v_max_i16_e32 v11, -1, v7
+; GFX8-NEXT: v_subrev_u16_e32 v11, 0x7fff, v11
+; GFX8-NEXT: v_min_i16_e32 v12, -1, v7
+; GFX8-NEXT: v_subrev_u16_e32 v12, 0x8000, v12
+; GFX8-NEXT: v_max_i16_sdwa v4, v11, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_max_i16_e32 v11, -1, v2
+; GFX8-NEXT: v_min_i16_e32 v4, v4, v12
+; GFX8-NEXT: v_subrev_u16_e32 v11, 0x7fff, v11
+; GFX8-NEXT: v_min_i16_e32 v12, -1, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX8-NEXT: v_sub_u16_e32 v14, v14, v12
-; GFX8-NEXT: v_max_i16_e32 v13, v13, v5
-; GFX8-NEXT: v_min_i16_e32 v13, v13, v14
-; GFX8-NEXT: v_max_i16_e32 v14, -1, v8
-; GFX8-NEXT: v_sub_u16_e32 v10, v14, v10
-; GFX8-NEXT: v_min_i16_e32 v14, -1, v8
-; GFX8-NEXT: v_sub_u16_e32 v12, v14, v12
-; GFX8-NEXT: v_max_i16_sdwa v5, v10, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_subrev_u16_e32 v12, 0x8000, v12
+; GFX8-NEXT: v_max_i16_e32 v11, v11, v5
+; GFX8-NEXT: v_min_i16_e32 v11, v11, v12
+; GFX8-NEXT: v_max_i16_e32 v12, -1, v8
+; GFX8-NEXT: v_subrev_u16_e32 v12, 0x7fff, v12
+; GFX8-NEXT: v_min_i16_e32 v13, -1, v8
+; GFX8-NEXT: v_subrev_u16_e32 v13, 0x8000, v13
+; GFX8-NEXT: v_max_i16_sdwa v5, v12, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v9
; GFX8-NEXT: v_sub_u16_sdwa v3, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_min_i16_e32 v5, v5, v12
+; GFX8-NEXT: v_min_i16_e32 v5, v5, v13
; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
-; GFX8-NEXT: v_sub_u16_e32 v1, v1, v11
+; GFX8-NEXT: v_sub_u16_e32 v1, v1, v10
; GFX8-NEXT: v_sub_u16_sdwa v3, v7, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX8-NEXT: v_sub_u16_e32 v2, v2, v13
+; GFX8-NEXT: v_sub_u16_e32 v2, v2, v11
; GFX8-NEXT: v_sub_u16_sdwa v3, v8, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v15
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v17
; GFX6-NEXT: v_min_i32_e32 v10, -1, v7
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v19
; GFX6-NEXT: v_max_i32_e32 v8, v9, v8
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3
; GFX6-NEXT: v_min_i32_e32 v8, v8, v10
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v5, 16, v5
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v8
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v4, 16, v4
; GFX6-NEXT: v_ashrrev_i32_e32 v7, 16, v7
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_and_b32_e32 v3, s4, v5
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v5
; GFX6-NEXT: v_ashrrev_i32_e32 v6, 16, v6
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v4
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v7
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX6-NEXT: v_and_b32_e32 v3, s4, v6
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-LABEL: v_ssubsat_v8i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_max_i16_e32 v12, -1, v0
-; GFX8-NEXT: s_movk_i32 s5, 0x8000
-; GFX8-NEXT: v_subrev_u16_e32 v12, s4, v12
-; GFX8-NEXT: v_min_i16_e32 v14, -1, v0
+; GFX8-NEXT: v_subrev_u16_e32 v12, 0x7fff, v12
+; GFX8-NEXT: v_min_i16_e32 v13, -1, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX8-NEXT: v_subrev_u16_e32 v14, s5, v14
+; GFX8-NEXT: v_subrev_u16_e32 v13, 0x8000, v13
; GFX8-NEXT: v_max_i16_e32 v12, v12, v4
-; GFX8-NEXT: v_min_i16_e32 v12, v12, v14
-; GFX8-NEXT: v_max_i16_e32 v14, -1, v8
-; GFX8-NEXT: v_subrev_u16_e32 v14, s4, v14
-; GFX8-NEXT: v_min_i16_e32 v16, -1, v8
-; GFX8-NEXT: v_subrev_u16_e32 v16, s5, v16
-; GFX8-NEXT: v_max_i16_sdwa v4, v14, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_max_i16_e32 v14, -1, v1
-; GFX8-NEXT: v_min_i16_e32 v4, v4, v16
-; GFX8-NEXT: v_subrev_u16_e32 v14, s4, v14
-; GFX8-NEXT: v_min_i16_e32 v16, -1, v1
+; GFX8-NEXT: v_min_i16_e32 v12, v12, v13
+; GFX8-NEXT: v_max_i16_e32 v13, -1, v8
+; GFX8-NEXT: v_subrev_u16_e32 v13, 0x7fff, v13
+; GFX8-NEXT: v_min_i16_e32 v14, -1, v8
+; GFX8-NEXT: v_subrev_u16_e32 v14, 0x8000, v14
+; GFX8-NEXT: v_max_i16_sdwa v4, v13, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_max_i16_e32 v13, -1, v1
+; GFX8-NEXT: v_min_i16_e32 v4, v4, v14
+; GFX8-NEXT: v_subrev_u16_e32 v13, 0x7fff, v13
+; GFX8-NEXT: v_min_i16_e32 v14, -1, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX8-NEXT: v_subrev_u16_e32 v16, s5, v16
-; GFX8-NEXT: v_max_i16_e32 v14, v14, v5
-; GFX8-NEXT: v_min_i16_e32 v14, v14, v16
-; GFX8-NEXT: v_max_i16_e32 v16, -1, v9
-; GFX8-NEXT: v_subrev_u16_e32 v16, s4, v16
-; GFX8-NEXT: v_min_i16_e32 v17, -1, v9
-; GFX8-NEXT: v_mov_b32_e32 v13, 0x7fff
-; GFX8-NEXT: v_subrev_u16_e32 v17, s5, v17
-; GFX8-NEXT: v_max_i16_sdwa v5, v16, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_max_i16_e32 v16, -1, v2
-; GFX8-NEXT: v_mov_b32_e32 v15, 0xffff8000
-; GFX8-NEXT: v_min_i16_e32 v5, v5, v17
-; GFX8-NEXT: v_sub_u16_e32 v16, v16, v13
-; GFX8-NEXT: v_min_i16_e32 v17, -1, v2
+; GFX8-NEXT: v_subrev_u16_e32 v14, 0x8000, v14
+; GFX8-NEXT: v_max_i16_e32 v13, v13, v5
+; GFX8-NEXT: v_min_i16_e32 v13, v13, v14
+; GFX8-NEXT: v_max_i16_e32 v14, -1, v9
+; GFX8-NEXT: v_subrev_u16_e32 v14, 0x7fff, v14
+; GFX8-NEXT: v_min_i16_e32 v15, -1, v9
+; GFX8-NEXT: v_subrev_u16_e32 v15, 0x8000, v15
+; GFX8-NEXT: v_max_i16_sdwa v5, v14, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_max_i16_e32 v14, -1, v2
+; GFX8-NEXT: v_min_i16_e32 v5, v5, v15
+; GFX8-NEXT: v_subrev_u16_e32 v14, 0x7fff, v14
+; GFX8-NEXT: v_min_i16_e32 v15, -1, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX8-NEXT: v_sub_u16_e32 v17, v17, v15
-; GFX8-NEXT: v_max_i16_e32 v16, v16, v6
-; GFX8-NEXT: v_min_i16_e32 v16, v16, v17
-; GFX8-NEXT: v_max_i16_e32 v17, -1, v10
-; GFX8-NEXT: v_sub_u16_e32 v17, v17, v13
-; GFX8-NEXT: v_min_i16_e32 v18, -1, v10
-; GFX8-NEXT: v_sub_u16_e32 v18, v18, v15
-; GFX8-NEXT: v_max_i16_sdwa v6, v17, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_max_i16_e32 v17, -1, v3
-; GFX8-NEXT: v_min_i16_e32 v6, v6, v18
-; GFX8-NEXT: v_sub_u16_e32 v17, v17, v13
-; GFX8-NEXT: v_min_i16_e32 v18, -1, v3
+; GFX8-NEXT: v_subrev_u16_e32 v15, 0x8000, v15
+; GFX8-NEXT: v_max_i16_e32 v14, v14, v6
+; GFX8-NEXT: v_min_i16_e32 v14, v14, v15
+; GFX8-NEXT: v_max_i16_e32 v15, -1, v10
+; GFX8-NEXT: v_subrev_u16_e32 v15, 0x7fff, v15
+; GFX8-NEXT: v_min_i16_e32 v16, -1, v10
+; GFX8-NEXT: v_subrev_u16_e32 v16, 0x8000, v16
+; GFX8-NEXT: v_max_i16_sdwa v6, v15, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_max_i16_e32 v15, -1, v3
+; GFX8-NEXT: v_min_i16_e32 v6, v6, v16
+; GFX8-NEXT: v_subrev_u16_e32 v15, 0x7fff, v15
+; GFX8-NEXT: v_min_i16_e32 v16, -1, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX8-NEXT: v_sub_u16_e32 v18, v18, v15
-; GFX8-NEXT: v_max_i16_e32 v17, v17, v7
-; GFX8-NEXT: v_min_i16_e32 v17, v17, v18
-; GFX8-NEXT: v_max_i16_e32 v18, -1, v11
-; GFX8-NEXT: v_sub_u16_e32 v13, v18, v13
-; GFX8-NEXT: v_min_i16_e32 v18, -1, v11
+; GFX8-NEXT: v_subrev_u16_e32 v16, 0x8000, v16
+; GFX8-NEXT: v_max_i16_e32 v15, v15, v7
+; GFX8-NEXT: v_min_i16_e32 v15, v15, v16
+; GFX8-NEXT: v_max_i16_e32 v16, -1, v11
+; GFX8-NEXT: v_subrev_u16_e32 v16, 0x7fff, v16
+; GFX8-NEXT: v_min_i16_e32 v17, -1, v11
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v12
; GFX8-NEXT: v_sub_u16_sdwa v4, v8, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_sub_u16_e32 v15, v18, v15
-; GFX8-NEXT: v_max_i16_sdwa v7, v13, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_subrev_u16_e32 v17, 0x8000, v17
+; GFX8-NEXT: v_max_i16_sdwa v7, v16, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX8-NEXT: v_sub_u16_e32 v1, v1, v14
+; GFX8-NEXT: v_sub_u16_e32 v1, v1, v13
; GFX8-NEXT: v_sub_u16_sdwa v4, v9, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_min_i16_e32 v7, v7, v15
+; GFX8-NEXT: v_min_i16_e32 v7, v7, v17
; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX8-NEXT: v_sub_u16_e32 v2, v2, v16
+; GFX8-NEXT: v_sub_u16_e32 v2, v2, v14
; GFX8-NEXT: v_sub_u16_sdwa v4, v10, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX8-NEXT: v_sub_u16_e32 v3, v3, v17
+; GFX8-NEXT: v_sub_u16_e32 v3, v3, v15
; GFX8-NEXT: v_sub_u16_sdwa v4, v11, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX7-LABEL: v_usubo_i8:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_movk_i32 s4, 0xff
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v0
; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX8-LABEL: v_usubo_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s4, 0xff
-; GFX8-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX8-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
-; GFX8-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v0
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
; GFX7-LABEL: v_usubo_i7:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_movk_i32 s4, 0x7f
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0x7f, v0
; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX8-LABEL: v_usubo_i7:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s4, 0x7f
-; GFX8-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX8-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
-; GFX8-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v0
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
; GFX9-LABEL: v_usubo_i7:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_movk_i32 s4, 0x7f
-; GFX9-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX9-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1
-; GFX9-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v0
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1
; GFX7-LABEL: s_usubo_i8:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_movk_i32 s4, 0xff
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v0
; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX8-LABEL: s_usubo_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s4, 0xff
-; GFX8-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX8-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
-; GFX8-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v0
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
; GFX7-LABEL: s_usubo_i7:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_movk_i32 s4, 0x7f
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0x7f, v0
; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX8-LABEL: s_usubo_i7:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_movk_i32 s4, 0x7f
-; GFX8-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX8-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
-; GFX8-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v0
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
; GFX9-LABEL: s_usubo_i7:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_movk_i32 s4, 0x7f
-; GFX9-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX9-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7f, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1
-; GFX9-NEXT: v_and_b32_e32 v1, s4, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v0
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1
define amdgpu_ps i16 @usubo_i16_sv(i16 inreg %a, i16 %b) {
; GFX7-LABEL: usubo_i16_sv:
; GFX7: ; %bb.0:
-; GFX7-NEXT: s_mov_b32 s1, 0xffff
; GFX7-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX7-NEXT: v_and_b32_e32 v0, s1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
-; GFX7-NEXT: v_and_b32_e32 v1, s1, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v0
; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
;
; GFX8-LABEL: usubo_i16_sv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_mov_b32 s1, 0xffff
; GFX8-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX8-NEXT: v_and_b32_e32 v0, s1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v0
-; GFX8-NEXT: v_and_b32_e32 v1, s1, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v0
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
; GFX7-LABEL: v_trunc_v4i32_to_v4i16:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_and_b32_e32 v0, v0, v4
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v3
-; GFX7-NEXT: v_and_b32_e32 v2, v2, v4
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-NEXT: v_or_b32_e32 v1, v1, v2
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v2
-; GFX9-NEXT: v_and_b32_e32 v2, s4, v1
+; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: s_mov_b32 s5, 24
; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v2
-; GFX9-NEXT: v_and_b32_e32 v2, s0, v1
+; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_or3_b32 v0, v0, v2, v1
; GISEL-LABEL: v_udiv_v2i32_pow2_shl_denom:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_movk_i32 s4, 0x1000
-; GISEL-NEXT: v_lshl_b32_e32 v2, s4, v2
-; GISEL-NEXT: v_lshl_b32_e32 v3, s4, v3
+; GISEL-NEXT: v_lshl_b32_e32 v2, 0x1000, v2
+; GISEL-NEXT: v_lshl_b32_e32 v3, 0x1000, v3
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v2
; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v2
; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3
; CGP-LABEL: v_udiv_v2i32_pow2_shl_denom:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_movk_i32 s4, 0x1000
-; CGP-NEXT: v_lshl_b32_e32 v2, s4, v2
-; CGP-NEXT: v_lshl_b32_e32 v3, s4, v3
+; CGP-NEXT: v_lshl_b32_e32 v2, 0x1000, v2
+; CGP-NEXT: v_lshl_b32_e32 v3, 0x1000, v3
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2
; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3
; GISEL-LABEL: v_udiv_i32_24bit:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s4, 0xffffff
-; GISEL-NEXT: v_and_b32_e32 v0, s4, v0
-; GISEL-NEXT: v_and_b32_e32 v1, s4, v1
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GISEL-NEXT: v_cvt_f32_u32_e32 v2, v1
; GISEL-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
; GISEL-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-LABEL: v_udiv_i32_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s4, 0xffffff
-; CGP-NEXT: v_and_b32_e32 v0, s4, v0
-; CGP-NEXT: v_and_b32_e32 v1, s4, v1
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
; CGP-NEXT: v_rcp_f32_e32 v2, v2
; GISEL-LABEL: v_udiv_v2i32_24bit:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s4, 0xffffff
-; GISEL-NEXT: v_and_b32_e32 v0, s4, v0
-; GISEL-NEXT: v_and_b32_e32 v1, s4, v1
-; GISEL-NEXT: v_and_b32_e32 v2, s4, v2
-; GISEL-NEXT: v_and_b32_e32 v3, s4, v3
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GISEL-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GISEL-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v2
; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v2
; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3
; CGP-LABEL: v_udiv_v2i32_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s4, 0xffffff
-; CGP-NEXT: v_and_b32_e32 v0, s4, v0
-; CGP-NEXT: v_and_b32_e32 v1, s4, v1
-; CGP-NEXT: v_and_b32_e32 v2, s4, v2
-; CGP-NEXT: v_and_b32_e32 v3, s4, v3
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2
; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3
; GISEL-LABEL: v_udiv_i64_24bit:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s4, 0xffffff
-; GISEL-NEXT: v_and_b32_e32 v0, s4, v0
-; GISEL-NEXT: v_and_b32_e32 v1, s4, v2
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v2
; GISEL-NEXT: v_cvt_f32_u32_e32 v2, v1
; GISEL-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
; GISEL-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-LABEL: v_udiv_i64_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s4, 0xffffff
-; CGP-NEXT: v_and_b32_e32 v0, s4, v0
-; CGP-NEXT: v_and_b32_e32 v1, s4, v2
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v0
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v1
; CGP-NEXT: v_rcp_f32_e32 v2, v1
; GISEL-LABEL: v_udiv_v2i64_24bit:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s6, 0xffffff
-; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v7, 0
-; GISEL-NEXT: v_and_b32_e32 v1, s6, v4
-; GISEL-NEXT: v_and_b32_e32 v3, s6, v6
-; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v1
+; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v4
+; GISEL-NEXT: v_and_b32_e32 v3, 0xffffff, v6
+; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
+; GISEL-NEXT: v_cvt_f32_u32_e32 v7, v1
; GISEL-NEXT: v_sub_i32_e32 v4, vcc, 0, v1
; GISEL-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, vcc
; GISEL-NEXT: v_cvt_f32_u32_e32 v8, v3
; GISEL-NEXT: v_sub_i32_e32 v9, vcc, 0, v3
; GISEL-NEXT: v_subb_u32_e64 v10, s[4:5], 0, 0, vcc
-; GISEL-NEXT: v_mac_f32_e32 v6, 0x4f800000, v7
-; GISEL-NEXT: v_mac_f32_e32 v8, 0x4f800000, v7
-; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6
+; GISEL-NEXT: v_mac_f32_e32 v7, 0x4f800000, v6
+; GISEL-NEXT: v_mac_f32_e32 v8, 0x4f800000, v6
+; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v7
; GISEL-NEXT: v_rcp_iflag_f32_e32 v7, v8
; GISEL-NEXT: v_mul_f32_e32 v6, 0x5f7ffffc, v6
; GISEL-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
; GISEL-NEXT: v_cvt_u32_f32_e32 v8, v8
; GISEL-NEXT: v_mac_f32_e32 v7, 0xcf800000, v11
; GISEL-NEXT: v_cvt_u32_f32_e32 v11, v11
-; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GISEL-NEXT: v_mul_lo_u32 v12, v4, v8
+; GISEL-NEXT: v_cvt_u32_f32_e32 v12, v6
+; GISEL-NEXT: v_mul_lo_u32 v6, v4, v8
; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7
; GISEL-NEXT: v_mul_lo_u32 v13, v9, v11
-; GISEL-NEXT: v_mul_lo_u32 v14, v4, v6
-; GISEL-NEXT: v_mul_lo_u32 v15, v5, v6
-; GISEL-NEXT: v_mul_hi_u32 v16, v4, v6
+; GISEL-NEXT: v_mul_lo_u32 v14, v4, v12
+; GISEL-NEXT: v_mul_lo_u32 v15, v5, v12
+; GISEL-NEXT: v_mul_hi_u32 v16, v4, v12
; GISEL-NEXT: v_mul_lo_u32 v17, v9, v7
; GISEL-NEXT: v_mul_lo_u32 v18, v10, v7
; GISEL-NEXT: v_mul_hi_u32 v19, v9, v7
-; GISEL-NEXT: v_add_i32_e32 v12, vcc, v15, v12
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, v15, v6
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v18, v13
; GISEL-NEXT: v_mul_lo_u32 v15, v11, v17
; GISEL-NEXT: v_mul_hi_u32 v18, v7, v17
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v18
; GISEL-NEXT: v_mul_lo_u32 v15, v8, v14
-; GISEL-NEXT: v_mul_hi_u32 v18, v6, v14
+; GISEL-NEXT: v_mul_hi_u32 v18, v12, v14
; GISEL-NEXT: v_mul_hi_u32 v14, v8, v14
; GISEL-NEXT: v_mul_hi_u32 v17, v11, v17
-; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v16
-; GISEL-NEXT: v_mul_lo_u32 v16, v6, v12
-; GISEL-NEXT: v_add_i32_e64 v15, s[4:5], v15, v16
-; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v15, s[4:5], v15, v18
-; GISEL-NEXT: v_mul_lo_u32 v15, v8, v12
-; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v16, s[4:5], v16, v18
-; GISEL-NEXT: v_mul_hi_u32 v18, v6, v12
-; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v15, v14
+; GISEL-NEXT: v_add_i32_e64 v16, s[4:5], v6, v16
+; GISEL-NEXT: v_mul_lo_u32 v6, v12, v16
+; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v15, v6
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v18
+; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v18
+; GISEL-NEXT: v_mul_lo_u32 v6, v8, v16
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v15, s[4:5], v15, v18
-; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v18, vcc, v19, v18
-; GISEL-NEXT: v_mul_lo_u32 v19, v11, v13
-; GISEL-NEXT: v_add_i32_e32 v17, vcc, v19, v17
-; GISEL-NEXT: v_mul_hi_u32 v19, v7, v13
+; GISEL-NEXT: v_mul_hi_u32 v18, v12, v16
+; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v14
+; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v18, s[4:5], v6, v18
+; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v6
+; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v19, vcc, v19, v6
+; GISEL-NEXT: v_mul_lo_u32 v6, v11, v13
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v17
+; GISEL-NEXT: v_mul_hi_u32 v17, v7, v13
; GISEL-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v19
-; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v19, vcc, v20, v19
+; GISEL-NEXT: v_add_i32_e32 v17, vcc, v6, v17
+; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v20, vcc, v20, v6
+; GISEL-NEXT: v_and_b32_e32 v6, 0xffffff, v0
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v2
; GISEL-NEXT: s_bfe_i32 s4, -1, 0x10000
; GISEL-NEXT: s_bfe_i32 s5, -1, 0x10000
+; GISEL-NEXT: s_bfe_i32 s6, -1, 0x10000
; GISEL-NEXT: s_bfe_i32 s7, -1, 0x10000
-; GISEL-NEXT: s_bfe_i32 s8, -1, 0x10000
-; GISEL-NEXT: v_and_b32_e32 v0, s6, v0
-; GISEL-NEXT: v_and_b32_e32 v2, s6, v2
-; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16
-; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16
-; GISEL-NEXT: v_mov_b32_e32 v16, s4
-; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v18
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v18, v15
+; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v15
+; GISEL-NEXT: v_mov_b32_e32 v15, s4
+; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v19
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v18, vcc, v19, v18
+; GISEL-NEXT: v_add_i32_e32 v18, vcc, v20, v18
; GISEL-NEXT: v_mov_b32_e32 v19, s5
-; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12
-; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15
-; GISEL-NEXT: v_mov_b32_e32 v15, s7
+; GISEL-NEXT: v_mul_hi_u32 v16, v8, v16
+; GISEL-NEXT: v_add_i32_e32 v14, vcc, v16, v14
+; GISEL-NEXT: v_mov_b32_e32 v16, s6
; GISEL-NEXT: v_mul_hi_u32 v13, v11, v13
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v18
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v14
-; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v12, vcc
-; GISEL-NEXT: v_mul_lo_u32 v12, v4, v6
-; GISEL-NEXT: v_mul_lo_u32 v5, v5, v6
-; GISEL-NEXT: v_mul_hi_u32 v14, v4, v6
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v12, v2
+; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v14, vcc
+; GISEL-NEXT: v_mul_lo_u32 v12, v4, v2
+; GISEL-NEXT: v_mul_lo_u32 v5, v5, v2
+; GISEL-NEXT: v_mul_hi_u32 v14, v4, v2
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v17
; GISEL-NEXT: v_addc_u32_e32 v11, vcc, v11, v13, vcc
; GISEL-NEXT: v_mul_lo_u32 v13, v9, v7
; GISEL-NEXT: v_mul_lo_u32 v4, v4, v8
; GISEL-NEXT: v_mul_lo_u32 v18, v8, v12
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT: v_mul_hi_u32 v5, v6, v12
+; GISEL-NEXT: v_mul_hi_u32 v5, v2, v12
; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12
; GISEL-NEXT: v_mul_lo_u32 v9, v9, v11
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v17
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v14
-; GISEL-NEXT: v_mul_lo_u32 v10, v6, v4
+; GISEL-NEXT: v_mul_lo_u32 v10, v2, v4
; GISEL-NEXT: v_mul_lo_u32 v14, v8, v4
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v18, v10
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5
-; GISEL-NEXT: v_mul_hi_u32 v5, v6, v4
+; GISEL-NEXT: v_mul_hi_u32 v5, v2, v4
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v18, v10
; GISEL-NEXT: v_mul_lo_u32 v18, v11, v9
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v17
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v18, v17
-; GISEL-NEXT: v_mov_b32_e32 v18, s8
+; GISEL-NEXT: v_mov_b32_e32 v18, s7
; GISEL-NEXT: v_mul_hi_u32 v4, v8, v4
; GISEL-NEXT: v_mul_hi_u32 v9, v11, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v10
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v17, v14
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GISEL-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GISEL-NEXT: v_mul_lo_u32 v6, 0, v5
-; GISEL-NEXT: v_mul_hi_u32 v8, v0, v5
-; GISEL-NEXT: v_mul_hi_u32 v5, 0, v5
+; GISEL-NEXT: v_mul_lo_u32 v5, 0, v2
+; GISEL-NEXT: v_mul_hi_u32 v8, v6, v2
+; GISEL-NEXT: v_mul_hi_u32 v2, 0, v2
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v13
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v11, v9, vcc
; GISEL-NEXT: v_mul_lo_u32 v10, 0, v7
-; GISEL-NEXT: v_mul_hi_u32 v11, v2, v7
+; GISEL-NEXT: v_mul_hi_u32 v11, v0, v7
; GISEL-NEXT: v_mul_hi_u32 v7, 0, v7
-; GISEL-NEXT: v_mul_lo_u32 v12, v0, v4
+; GISEL-NEXT: v_mul_lo_u32 v12, v6, v4
; GISEL-NEXT: v_mul_lo_u32 v13, 0, v4
-; GISEL-NEXT: v_mul_hi_u32 v14, v0, v4
+; GISEL-NEXT: v_mul_hi_u32 v14, v6, v4
; GISEL-NEXT: v_mul_hi_u32 v4, 0, v4
-; GISEL-NEXT: v_mul_lo_u32 v17, v2, v9
+; GISEL-NEXT: v_mul_lo_u32 v17, v0, v9
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v17
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_mul_lo_u32 v10, 0, v9
-; GISEL-NEXT: v_mul_hi_u32 v11, v2, v9
+; GISEL-NEXT: v_mul_hi_u32 v11, v0, v9
; GISEL-NEXT: v_mul_hi_u32 v9, 0, v9
-; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v12
+; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v13, v5
+; GISEL-NEXT: v_add_i32_e64 v2, s[4:5], v13, v2
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v14
+; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v2, s[4:5], v2, v14
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v12, v6
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v12, v5
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v13, v8
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v17, v14
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v12
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v8, v6
-; GISEL-NEXT: v_mul_lo_u32 v8, v1, v5
-; GISEL-NEXT: v_mul_lo_u32 v12, 0, v5
-; GISEL-NEXT: v_mul_hi_u32 v13, v1, v5
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v8, v5
+; GISEL-NEXT: v_mul_lo_u32 v8, v1, v2
+; GISEL-NEXT: v_mul_lo_u32 v12, 0, v2
+; GISEL-NEXT: v_mul_hi_u32 v13, v1, v2
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_mul_lo_u32 v11, v3, v7
; GISEL-NEXT: v_mul_lo_u32 v14, 0, v7
; GISEL-NEXT: v_mul_hi_u32 v17, v3, v7
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v9, v10
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v9, v10
; GISEL-NEXT: v_mul_lo_u32 v9, v1, v4
-; GISEL-NEXT: v_mul_lo_u32 v10, v3, v6
+; GISEL-NEXT: v_mul_lo_u32 v10, v3, v5
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v12, v9
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v14, v10
-; GISEL-NEXT: v_add_i32_e32 v12, vcc, 1, v5
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, 1, v2
; GISEL-NEXT: v_addc_u32_e32 v14, vcc, 0, v4, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v13
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v17
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
+; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v6, v8
; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], 0, v9, vcc
-; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v1
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v1
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
; GISEL-NEXT: v_add_i32_e64 v8, s[6:7], 1, v7
-; GISEL-NEXT: v_addc_u32_e64 v17, s[6:7], 0, v6, s[6:7]
-; GISEL-NEXT: v_sub_i32_e64 v2, s[6:7], v2, v11
+; GISEL-NEXT: v_addc_u32_e64 v17, s[6:7], 0, v5, s[6:7]
+; GISEL-NEXT: v_sub_i32_e64 v0, s[6:7], v0, v11
; GISEL-NEXT: v_subb_u32_e64 v11, s[8:9], 0, v10, s[6:7]
-; GISEL-NEXT: v_cndmask_b32_e64 v13, v16, v13, s[4:5]
-; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v3
-; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, -1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v13, v15, v13, s[4:5]
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v3
+; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v11
-; GISEL-NEXT: v_cndmask_b32_e64 v11, v15, v16, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v11, v16, v15, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v15, s[4:5], 1, v12
; GISEL-NEXT: v_addc_u32_e64 v16, s[4:5], 0, v14, s[4:5]
; GISEL-NEXT: v_sub_i32_e64 v10, s[4:5], 0, v10
; GISEL-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v10, s[6:7]
-; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v3
+; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v3
; GISEL-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v10, s[4:5]
-; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v3
-; GISEL-NEXT: v_add_i32_e64 v2, s[6:7], 1, v8
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v3
+; GISEL-NEXT: v_add_i32_e64 v0, s[6:7], 1, v8
; GISEL-NEXT: v_addc_u32_e64 v3, s[6:7], 0, v17, s[6:7]
; GISEL-NEXT: v_sub_i32_e64 v9, s[6:7], 0, v9
; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
+; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v6, v1
; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc
-; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[4:5]
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v6, v1
+; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v19, v0, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10
-; GISEL-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v12, v15, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v1, v8, v2, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v12, v15, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6
+; GISEL-NEXT: v_cndmask_b32_e64 v6, v8, v0, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v8, v14, v16, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v3, v17, v3, s[4:5]
; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v11
-; GISEL-NEXT: v_cndmask_b32_e64 v2, v7, v1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v2, v7, v6, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v8, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v3, v6, v3, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; CGP-LABEL: v_udiv_v2i64_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s6, 0xffffff
-; CGP-NEXT: v_and_b32_e32 v0, s6, v0
-; CGP-NEXT: v_and_b32_e32 v1, s6, v2
-; CGP-NEXT: v_and_b32_e32 v2, s6, v4
-; CGP-NEXT: v_and_b32_e32 v3, s6, v6
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v2
+; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v4
+; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v6
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v0
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v1
; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e32 v0, vcc, v4, v0
; CGP-NEXT: v_add_i32_e32 v1, vcc, v5, v1
-; CGP-NEXT: v_and_b32_e32 v0, s6, v0
-; CGP-NEXT: v_and_b32_e32 v2, s6, v1
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v1
; CGP-NEXT: v_mov_b32_e32 v1, 0
; CGP-NEXT: v_mov_b32_e32 v3, 0
; CGP-NEXT: s_setpc_b64 s[30:31]
; GFX8-LABEL: udivrem_v4i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x4f7ffffe
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s12
; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX8-NEXT: v_mul_lo_u32 v3, s0, v0
+; GFX8-NEXT: v_mul_lo_u32 v2, s0, v0
; GFX8-NEXT: s_sub_i32 s0, 0, s13
-; GFX8-NEXT: v_mul_lo_u32 v4, s0, v1
-; GFX8-NEXT: v_mul_hi_u32 v3, v0, v3
-; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
+; GFX8-NEXT: v_mul_lo_u32 v3, s0, v1
+; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v0, s8, v0
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v4
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: v_mul_hi_u32 v1, s9, v1
-; GFX8-NEXT: v_mul_lo_u32 v3, v0, s12
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v0
+; GFX8-NEXT: v_mul_lo_u32 v2, v0, s12
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0
; GFX8-NEXT: v_mul_lo_u32 v5, v1, s13
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s8, v3
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s12, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v0
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s12, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s9, v5
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v5, v6
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, 1, v1
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s13, v3
-; GFX8-NEXT: v_mul_f32_e32 v5, v5, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX8-NEXT: v_cvt_u32_f32_e32 v5, v5
-; GFX8-NEXT: v_subrev_u32_e64 v6, s[0:1], s13, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, 1, v1
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s13, v3
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s8, v2
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s12, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s12, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s12, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX8-NEXT: v_subrev_u32_e64 v3, s[0:1], s12, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v6
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s9, v5
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 1, v1
+; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s13, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX8-NEXT: v_subrev_u32_e64 v5, s[0:1], s13, v2
; GFX8-NEXT: s_sub_i32 s0, 0, s14
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX8-NEXT: v_cvt_f32_u32_e32 v6, s15
-; GFX8-NEXT: v_mul_lo_u32 v7, s0, v5
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX8-NEXT: v_mul_hi_u32 v7, v5, v7
-; GFX8-NEXT: v_mul_f32_e32 v2, v6, v2
-; GFX8-NEXT: v_add_u32_e64 v5, s[0:1], v5, v7
-; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX8-NEXT: v_mul_hi_u32 v7, s10, v5
-; GFX8-NEXT: v_subrev_u32_e64 v5, s[0:1], s13, v3
+; GFX8-NEXT: v_mul_lo_u32 v6, s0, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 1, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s13, v2
+; GFX8-NEXT: v_mul_hi_u32 v6, v3, v6
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX8-NEXT: v_cvt_f32_u32_e32 v5, s15
+; GFX8-NEXT: v_add_u32_e64 v3, s[0:1], v3, v6
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v5
+; GFX8-NEXT: v_mul_hi_u32 v3, s10, v3
+; GFX8-NEXT: v_subrev_u32_e64 v5, s[0:1], s13, v2
+; GFX8-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
+; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX8-NEXT: s_sub_i32 s0, 0, s15
-; GFX8-NEXT: v_mul_lo_u32 v6, s0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc
-; GFX8-NEXT: v_mul_lo_u32 v3, v7, s14
-; GFX8-NEXT: v_add_u32_e32 v8, vcc, 1, v7
-; GFX8-NEXT: v_mul_hi_u32 v6, v2, v6
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s10, v3
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s14, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
-; GFX8-NEXT: v_subrev_u32_e64 v8, s[0:1], s14, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v2, v5, vcc
+; GFX8-NEXT: v_mul_lo_u32 v2, v3, s14
+; GFX8-NEXT: v_mul_lo_u32 v7, s0, v6
+; GFX8-NEXT: v_add_u32_e32 v8, vcc, 1, v3
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s10, v2
+; GFX8-NEXT: v_mul_hi_u32 v7, v6, v7
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s14, v2
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v6
-; GFX8-NEXT: v_mul_hi_u32 v8, s11, v2
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v7
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s14, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
-; GFX8-NEXT: v_mul_lo_u32 v7, v8, s15
-; GFX8-NEXT: v_subrev_u32_e64 v6, s[0:1], s14, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v6, v3, v6, vcc
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s11, v7
-; GFX8-NEXT: v_add_u32_e32 v7, vcc, 1, v8
+; GFX8-NEXT: v_subrev_u32_e64 v8, s[0:1], s14, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v2, v8, vcc
+; GFX8-NEXT: v_add_u32_e32 v2, vcc, v6, v7
+; GFX8-NEXT: v_mul_hi_u32 v7, s11, v2
+; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v3
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s14, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; GFX8-NEXT: v_mul_lo_u32 v3, v7, s15
+; GFX8-NEXT: v_subrev_u32_e64 v6, s[0:1], s14, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s11, v3
+; GFX8-NEXT: v_add_u32_e32 v8, vcc, 1, v7
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s15, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GFX8-NEXT: v_subrev_u32_e64 v8, s[0:1], s15, v3
; GFX8-NEXT: v_cndmask_b32_e32 v8, v3, v8, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v7
; GFX9-LABEL: udivrem_v4i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x10
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x4f7ffffe
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s12
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX9-NEXT: s_sub_i32 s1, 0, s13
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s14
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s14
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, v1, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5
-; GFX9-NEXT: v_mul_lo_u32 v3, s0, v0
-; GFX9-NEXT: v_mul_lo_u32 v4, s1, v1
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v4
+; GFX9-NEXT: v_mul_lo_u32 v2, s0, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, s1, v1
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3
; GFX9-NEXT: s_sub_i32 s4, 0, s14
-; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v0, s8, v0
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v4
; GFX9-NEXT: v_mul_hi_u32 v1, s9, v1
-; GFX9-NEXT: v_mul_f32_e32 v3, v5, v2
-; GFX9-NEXT: v_mul_lo_u32 v4, v0, s12
-; GFX9-NEXT: v_add_u32_e32 v6, 1, v0
-; GFX9-NEXT: v_mul_lo_u32 v5, v1, s13
-; GFX9-NEXT: v_add_u32_e32 v7, 1, v1
-; GFX9-NEXT: v_sub_u32_e32 v4, s8, v4
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v6, s12, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX9-NEXT: v_add_u32_e32 v6, 1, v0
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v4
-; GFX9-NEXT: v_sub_u32_e32 v5, s9, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v6, s12, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s13, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s15
+; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_mul_lo_u32 v3, v0, s12
+; GFX9-NEXT: v_mul_lo_u32 v4, v1, s13
+; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v1
+; GFX9-NEXT: v_sub_u32_e32 v3, s8, v3
+; GFX9-NEXT: v_sub_u32_e32 v7, s9, v4
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
+; GFX9-NEXT: v_subrev_u32_e32 v4, s12, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v4, s12, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, s4, v2
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s15
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s13, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5
+; GFX9-NEXT: v_subrev_u32_e32 v6, s13, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v3
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v5
+; GFX9-NEXT: v_mul_hi_u32 v2, s10, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT: v_subrev_u32_e32 v8, s13, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v7
-; GFX9-NEXT: v_mul_lo_u32 v6, s4, v3
+; GFX9-NEXT: v_add_u32_e32 v7, 1, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s13, v6
; GFX9-NEXT: s_sub_i32 s4, 0, s15
-; GFX9-NEXT: v_add_u32_e32 v8, 1, v1
-; GFX9-NEXT: v_mul_f32_e32 v2, v7, v2
-; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX9-NEXT: v_mul_hi_u32 v6, v3, v6
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s13, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
-; GFX9-NEXT: v_mul_lo_u32 v7, s4, v2
-; GFX9-NEXT: v_add_u32_e32 v3, v3, v6
-; GFX9-NEXT: v_mul_hi_u32 v3, s10, v3
-; GFX9-NEXT: v_subrev_u32_e32 v8, s13, v5
-; GFX9-NEXT: v_mul_hi_u32 v7, v2, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
-; GFX9-NEXT: v_mul_lo_u32 v6, v3, s14
-; GFX9-NEXT: v_add_u32_e32 v8, 1, v3
-; GFX9-NEXT: v_add_u32_e32 v2, v2, v7
-; GFX9-NEXT: v_mul_hi_u32 v7, s11, v2
-; GFX9-NEXT: v_sub_u32_e32 v6, s10, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
+; GFX9-NEXT: v_mul_lo_u32 v7, v2, s14
+; GFX9-NEXT: v_mul_lo_u32 v8, s4, v3
+; GFX9-NEXT: v_subrev_u32_e32 v5, s13, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
+; GFX9-NEXT: v_sub_u32_e32 v6, s10, v7
+; GFX9-NEXT: v_mul_hi_u32 v7, v3, v8
+; GFX9-NEXT: v_add_u32_e32 v8, 1, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v2, s14, v6
-; GFX9-NEXT: v_mul_lo_u32 v8, v7, s15
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc
-; GFX9-NEXT: v_add_u32_e32 v2, 1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v7
+; GFX9-NEXT: v_mul_hi_u32 v3, s11, v3
+; GFX9-NEXT: v_subrev_u32_e32 v7, s14, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; GFX9-NEXT: v_add_u32_e32 v7, 1, v2
+; GFX9-NEXT: v_mul_lo_u32 v8, v3, s15
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v3, s14, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v3, vcc
-; GFX9-NEXT: v_sub_u32_e32 v3, s11, v8
-; GFX9-NEXT: v_add_u32_e32 v8, 1, v7
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v7, s14, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; GFX9-NEXT: v_sub_u32_e32 v7, s11, v8
+; GFX9-NEXT: v_add_u32_e32 v8, 1, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v8, s15, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
+; GFX9-NEXT: v_add_u32_e32 v8, 1, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v8, s15, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v8, s15, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v3, v8, vcc
-; GFX9-NEXT: v_add_u32_e32 v3, 1, v7
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v8
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v7, s15, v8
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1]
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s3, v3
-; GFX8-NEXT: s_movk_i32 s0, 0xff
-; GFX8-NEXT: v_and_b32_e32 v1, s0, v1
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: v_or_b32_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: flat_store_short v[0:1], v4
-; GFX8-NEXT: v_and_b32_e32 v0, s0, v3
+; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v3
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX8-NEXT: v_or_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: v_mul_hi_u32 v1, s8, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v0, s9, v0
-; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_mul_lo_u32 v3, v1, s6
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_mul_lo_u32 v2, v0, s7
; GFX9-NEXT: v_add_u32_e32 v4, 1, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX9-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX9-NEXT: v_subrev_u32_e32 v4, s7, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_short v1, v0, s[0:1]
-; GFX9-NEXT: v_and_b32_e32 v0, s4, v2
+; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: global_store_short v1, v0, s[2:3]
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x10
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
-; GFX8-NEXT: s_mov_b32 s8, 0xffff
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_and_b32 s2, s1, 0xffff
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s3
; GFX8-NEXT: s_sub_i32 s1, 0, s2
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX8-NEXT: s_lshr_b32 s9, s0, 16
+; GFX8-NEXT: s_lshr_b32 s8, s0, 16
; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX8-NEXT: s_and_b32 s0, s0, 0xffff
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
-; GFX8-NEXT: v_mul_hi_u32 v1, s9, v1
+; GFX8-NEXT: v_mul_hi_u32 v1, s8, v1
; GFX8-NEXT: v_mul_lo_u32 v2, v0, s2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v0
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s0, v2
; GFX8-NEXT: v_mul_lo_u32 v3, v1, s3
; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s9, v3
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s8, v3
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s3, v3
-; GFX8-NEXT: v_and_b32_e32 v1, s8, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX8-NEXT: v_or_b32_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v0, s8, v3
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_or_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mul_lo_u32 v1, s0, v0
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX8-NEXT: s_and_b32 s4, s6, 0x7ffffff
-; GFX8-NEXT: s_mov_b32 s5, 0x7ffffff
; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; GFX8-NEXT: v_mul_hi_u32 v2, s4, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s7, v3
-; GFX8-NEXT: v_and_b32_e32 v2, s5, v2
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7ffffff, v2
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v0, s2
-; GFX8-NEXT: v_and_b32_e32 v2, s5, v3
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7ffffff, v3
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_lo_u32 v1, s1, v0
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s4, 0x7ffffff
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, s6, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX9-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7ffffff, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
-; GFX9-NEXT: v_and_b32_e32 v0, s4, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7ffffff, v1
; GFX9-NEXT: global_store_dword v2, v0, s[2:3]
; GFX9-NEXT: s_endpgm
;
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v2
-; GISEL-NEXT: s_mov_b32 s4, 0x4f7ffffe
; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v2
; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3
; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v3
; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GISEL-NEXT: v_mul_f32_e32 v4, s4, v4
-; GISEL-NEXT: v_mul_f32_e32 v6, s4, v6
+; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
+; GISEL-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
; GISEL-NEXT: v_mul_lo_u32 v5, v5, v4
; CHECK-LABEL: v_urem_v2i32_pow2k_denom:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: s_movk_i32 s4, 0xfff
-; CHECK-NEXT: v_and_b32_e32 v0, s4, v0
-; CHECK-NEXT: v_and_b32_e32 v1, s4, v1
+; CHECK-NEXT: v_and_b32_e32 v0, 0xfff, v0
+; CHECK-NEXT: v_and_b32_e32 v1, 0xfff, v1
; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = urem <2 x i32> %num, <i32 4096, i32 4096>
ret <2 x i32> %result
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: s_mov_b32 s4, 0x12d8fb
; GISEL-NEXT: v_mov_b32_e32 v2, 0x12d8fb
-; GISEL-NEXT: v_mov_b32_e32 v3, 0xffed2705
-; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s4
-; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
-; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
-; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
-; GISEL-NEXT: v_mul_lo_u32 v3, v3, v4
-; GISEL-NEXT: v_mul_hi_u32 v3, v4, v3
-; GISEL-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; GISEL-NEXT: v_cvt_f32_u32_e32 v3, 0x12d8fb
+; GISEL-NEXT: v_mov_b32_e32 v4, 0xffed2705
+; GISEL-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GISEL-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GISEL-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GISEL-NEXT: v_mul_lo_u32 v4, v4, v3
+; GISEL-NEXT: v_mul_hi_u32 v4, v3, v4
+; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GISEL-NEXT: v_mul_hi_u32 v4, v0, v3
; GISEL-NEXT: v_mul_hi_u32 v3, v1, v3
; GISEL-NEXT: v_mul_lo_u32 v4, v4, s4
; GISEL-LABEL: v_urem_v2i32_pow2_shl_denom:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_movk_i32 s4, 0x1000
-; GISEL-NEXT: s_mov_b32 s5, 0x4f7ffffe
-; GISEL-NEXT: v_lshl_b32_e32 v2, s4, v2
-; GISEL-NEXT: v_lshl_b32_e32 v3, s4, v3
+; GISEL-NEXT: v_lshl_b32_e32 v2, 0x1000, v2
+; GISEL-NEXT: v_lshl_b32_e32 v3, 0x1000, v3
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v2
; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v2
; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3
; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v3
; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GISEL-NEXT: v_mul_f32_e32 v4, s5, v4
-; GISEL-NEXT: v_mul_f32_e32 v6, s5, v6
+; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
+; GISEL-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
; GISEL-NEXT: v_mul_lo_u32 v5, v5, v4
; CGP-LABEL: v_urem_v2i32_pow2_shl_denom:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_movk_i32 s4, 0x1000
-; CGP-NEXT: v_lshl_b32_e32 v2, s4, v2
-; CGP-NEXT: v_lshl_b32_e32 v3, s4, v3
+; CGP-NEXT: v_lshl_b32_e32 v2, 0x1000, v2
+; CGP-NEXT: v_lshl_b32_e32 v3, 0x1000, v3
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2
; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3
; GISEL-LABEL: v_urem_i32_24bit:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s4, 0xffffff
-; GISEL-NEXT: v_and_b32_e32 v0, s4, v0
-; GISEL-NEXT: v_and_b32_e32 v1, s4, v1
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GISEL-NEXT: v_cvt_f32_u32_e32 v2, v1
; GISEL-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
; GISEL-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-LABEL: v_urem_i32_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s4, 0xffffff
-; CGP-NEXT: v_and_b32_e32 v0, s4, v0
-; CGP-NEXT: v_and_b32_e32 v1, s4, v1
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
; CGP-NEXT: v_rcp_f32_e32 v2, v2
; GISEL-LABEL: v_urem_v2i32_24bit:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s4, 0xffffff
-; GISEL-NEXT: s_mov_b32 s5, 0x4f7ffffe
-; GISEL-NEXT: v_and_b32_e32 v0, s4, v0
-; GISEL-NEXT: v_and_b32_e32 v1, s4, v1
-; GISEL-NEXT: v_and_b32_e32 v2, s4, v2
-; GISEL-NEXT: v_and_b32_e32 v3, s4, v3
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GISEL-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GISEL-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v2
; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v2
; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3
; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v3
; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GISEL-NEXT: v_mul_f32_e32 v4, s5, v4
-; GISEL-NEXT: v_mul_f32_e32 v6, s5, v6
+; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
+; GISEL-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
; GISEL-NEXT: v_mul_lo_u32 v5, v5, v4
; CGP-LABEL: v_urem_v2i32_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s4, 0xffffff
-; CGP-NEXT: v_and_b32_e32 v0, s4, v0
-; CGP-NEXT: v_and_b32_e32 v1, s4, v1
-; CGP-NEXT: v_and_b32_e32 v2, s4, v2
-; CGP-NEXT: v_and_b32_e32 v3, s4, v3
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2
; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3
; CHECK-LABEL: v_urem_v2i64_pow2k_denom:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: s_movk_i32 s4, 0xfff
-; CHECK-NEXT: v_and_b32_e32 v0, s4, v0
-; CHECK-NEXT: v_and_b32_e32 v2, s4, v2
+; CHECK-NEXT: v_and_b32_e32 v0, 0xfff, v0
+; CHECK-NEXT: v_and_b32_e32 v2, 0xfff, v2
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: s_setpc_b64 s[30:31]
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s4, 0x12d8fb
; CHECK-NEXT: v_mov_b32_e32 v2, 0x12d8fb
-; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0
+; CHECK-NEXT: v_cvt_f32_u32_e32 v3, 0x12d8fb
+; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0
; CHECK-NEXT: s_mov_b32 s5, 0xffed2705
; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000
; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000
-; CHECK-NEXT: v_cvt_f32_u32_e32 v4, s4
-; CHECK-NEXT: v_mov_b32_e32 v5, s6
-; CHECK-NEXT: v_mov_b32_e32 v6, s7
-; CHECK-NEXT: v_mac_f32_e32 v4, 0x4f800000, v3
-; CHECK-NEXT: v_rcp_iflag_f32_e32 v3, v4
+; CHECK-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4
+; CHECK-NEXT: v_mov_b32_e32 v4, s6
+; CHECK-NEXT: v_mov_b32_e32 v5, s7
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v3, v3
; CHECK-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3
-; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
-; CHECK-NEXT: v_trunc_f32_e32 v4, v4
-; CHECK-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4
-; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
+; CHECK-NEXT: v_mul_f32_e32 v6, 0x2f800000, v3
+; CHECK-NEXT: v_trunc_f32_e32 v6, v6
+; CHECK-NEXT: v_mac_f32_e32 v3, 0xcf800000, v6
+; CHECK-NEXT: v_cvt_u32_f32_e32 v6, v6
; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3
-; CHECK-NEXT: v_mul_lo_u32 v7, s5, v4
+; CHECK-NEXT: v_mul_lo_u32 v7, s5, v6
; CHECK-NEXT: v_mul_lo_u32 v8, s5, v3
; CHECK-NEXT: v_mul_lo_u32 v9, -1, v3
; CHECK-NEXT: v_mul_hi_u32 v10, s5, v3
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7
-; CHECK-NEXT: v_mul_lo_u32 v9, v4, v8
+; CHECK-NEXT: v_mul_lo_u32 v9, v6, v8
; CHECK-NEXT: v_mul_hi_u32 v11, v3, v8
-; CHECK-NEXT: v_mul_hi_u32 v8, v4, v8
+; CHECK-NEXT: v_mul_hi_u32 v8, v6, v8
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CHECK-NEXT: v_mul_lo_u32 v10, v3, v7
-; CHECK-NEXT: v_mul_lo_u32 v12, v4, v7
+; CHECK-NEXT: v_mul_lo_u32 v12, v6, v7
; CHECK-NEXT: v_mul_hi_u32 v13, v3, v7
-; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
+; CHECK-NEXT: v_mul_hi_u32 v7, v6, v7
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v12, v8
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v8
-; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v7, vcc
+; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, s5, v3
; CHECK-NEXT: v_mul_lo_u32 v8, -1, v3
; CHECK-NEXT: v_mul_hi_u32 v9, s5, v3
-; CHECK-NEXT: v_mul_lo_u32 v10, s5, v4
-; CHECK-NEXT: v_mul_lo_u32 v11, v4, v7
+; CHECK-NEXT: v_mul_lo_u32 v10, s5, v6
+; CHECK-NEXT: v_mul_lo_u32 v11, v6, v7
; CHECK-NEXT: v_mul_hi_u32 v12, v3, v7
-; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
+; CHECK-NEXT: v_mul_hi_u32 v7, v6, v7
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CHECK-NEXT: v_mul_lo_u32 v9, v3, v8
-; CHECK-NEXT: v_mul_lo_u32 v10, v4, v8
+; CHECK-NEXT: v_mul_lo_u32 v10, v6, v8
; CHECK-NEXT: v_mul_hi_u32 v13, v3, v8
-; CHECK-NEXT: v_mul_hi_u32 v8, v4, v8
+; CHECK-NEXT: v_mul_hi_u32 v8, v6, v8
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v7
-; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v8, vcc
+; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, v1, v3
; CHECK-NEXT: v_mul_hi_u32 v8, v0, v3
; CHECK-NEXT: v_mul_hi_u32 v3, v1, v3
-; CHECK-NEXT: v_mul_lo_u32 v9, v0, v4
-; CHECK-NEXT: v_mul_lo_u32 v10, v1, v4
-; CHECK-NEXT: v_mul_hi_u32 v11, v0, v4
-; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4
+; CHECK-NEXT: v_mul_lo_u32 v9, v0, v6
+; CHECK-NEXT: v_mul_lo_u32 v10, v1, v6
+; CHECK-NEXT: v_mul_hi_u32 v11, v0, v6
+; CHECK-NEXT: v_mul_hi_u32 v6, v1, v6
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v10, v3
; CHECK-NEXT: v_mul_lo_u32 v8, s4, v3
; CHECK-NEXT: v_mul_lo_u32 v9, 0, v3
; CHECK-NEXT: v_mul_hi_u32 v3, s4, v3
-; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7
-; CHECK-NEXT: v_mul_lo_u32 v4, s4, v4
-; CHECK-NEXT: v_add_i32_e32 v4, vcc, v9, v4
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; CHECK-NEXT: v_mul_lo_u32 v6, s4, v6
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v9, v6
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, v6, v3
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
-; CHECK-NEXT: v_subb_u32_e64 v4, s[4:5], v1, v3, vcc
+; CHECK-NEXT: v_subb_u32_e64 v6, s[4:5], v1, v3, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v3
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v2
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5]
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
-; CHECK-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5]
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
+; CHECK-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT: v_sub_i32_e32 v5, vcc, v0, v2
+; CHECK-NEXT: v_sub_i32_e32 v4, vcc, v0, v2
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v5, v2
+; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
-; CHECK-NEXT: v_sub_i32_e32 v2, vcc, v5, v2
+; CHECK-NEXT: v_sub_i32_e32 v2, vcc, v4, v2
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
-; CHECK-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[4:5]
+; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v1, vcc
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; CHECK-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
+; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
+; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
+; CHECK-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = urem i64 %num, 1235195
ret i64 %result
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: s_mov_b32 s8, 0x12d8fb
; GISEL-NEXT: v_mov_b32_e32 v4, 0x12d8fb
-; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v7, 0
+; GISEL-NEXT: v_cvt_f32_u32_e32 v7, 0x12d8fb
+; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
; GISEL-NEXT: s_sub_u32 s6, 0, 0x12d8fb
-; GISEL-NEXT: v_cvt_f32_u32_e32 v8, s8
+; GISEL-NEXT: v_madmk_f32 v6, v5, 0x4f800000, v7
; GISEL-NEXT: s_subb_u32 s7, 0, 0
; GISEL-NEXT: s_bfe_i32 s4, -1, 0x10000
; GISEL-NEXT: s_bfe_i32 s5, -1, 0x10000
-; GISEL-NEXT: v_madmk_f32 v9, v7, 0x4f800000, v8
+; GISEL-NEXT: v_mac_f32_e32 v7, 0x4f800000, v5
+; GISEL-NEXT: v_rcp_iflag_f32_e32 v8, v6
; GISEL-NEXT: v_mov_b32_e32 v6, s4
; GISEL-NEXT: v_mov_b32_e32 v5, s5
-; GISEL-NEXT: v_mac_f32_e32 v8, 0x4f800000, v7
+; GISEL-NEXT: v_rcp_iflag_f32_e32 v7, v7
; GISEL-NEXT: s_sub_u32 s9, 0, 0x12d8fb
-; GISEL-NEXT: v_rcp_iflag_f32_e32 v7, v9
-; GISEL-NEXT: v_rcp_iflag_f32_e32 v8, v8
+; GISEL-NEXT: v_mul_f32_e32 v8, 0x5f7ffffc, v8
+; GISEL-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
; GISEL-NEXT: s_subb_u32 s10, 0, 0
; GISEL-NEXT: s_bfe_i32 s11, -1, 0x10000
; GISEL-NEXT: s_bfe_i32 s12, -1, 0x10000
-; GISEL-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
-; GISEL-NEXT: v_mul_f32_e32 v8, 0x5f7ffffc, v8
-; GISEL-NEXT: v_mul_f32_e32 v9, 0x2f800000, v7
-; GISEL-NEXT: v_mul_f32_e32 v10, 0x2f800000, v8
+; GISEL-NEXT: v_mul_f32_e32 v9, 0x2f800000, v8
+; GISEL-NEXT: v_mul_f32_e32 v10, 0x2f800000, v7
; GISEL-NEXT: v_trunc_f32_e32 v9, v9
; GISEL-NEXT: v_trunc_f32_e32 v10, v10
-; GISEL-NEXT: v_mac_f32_e32 v7, 0xcf800000, v9
+; GISEL-NEXT: v_mac_f32_e32 v8, 0xcf800000, v9
; GISEL-NEXT: v_cvt_u32_f32_e32 v9, v9
-; GISEL-NEXT: v_mac_f32_e32 v8, 0xcf800000, v10
+; GISEL-NEXT: v_mac_f32_e32 v7, 0xcf800000, v10
; GISEL-NEXT: v_cvt_u32_f32_e32 v10, v10
-; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7
-; GISEL-NEXT: v_mul_lo_u32 v11, s6, v9
; GISEL-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GISEL-NEXT: v_mul_lo_u32 v11, s6, v9
+; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7
; GISEL-NEXT: v_mul_lo_u32 v12, s9, v10
-; GISEL-NEXT: v_mul_lo_u32 v13, s6, v7
-; GISEL-NEXT: v_mul_lo_u32 v14, s7, v7
-; GISEL-NEXT: v_mul_hi_u32 v15, s6, v7
-; GISEL-NEXT: v_mul_lo_u32 v16, s9, v8
-; GISEL-NEXT: v_mul_lo_u32 v17, s10, v8
-; GISEL-NEXT: v_mul_hi_u32 v18, s9, v8
+; GISEL-NEXT: v_mul_lo_u32 v13, s6, v8
+; GISEL-NEXT: v_mul_lo_u32 v14, s7, v8
+; GISEL-NEXT: v_mul_hi_u32 v15, s6, v8
+; GISEL-NEXT: v_mul_lo_u32 v16, s9, v7
+; GISEL-NEXT: v_mul_lo_u32 v17, s10, v7
+; GISEL-NEXT: v_mul_hi_u32 v18, s9, v7
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v14, v11
; GISEL-NEXT: v_mul_lo_u32 v14, v9, v13
-; GISEL-NEXT: v_mul_hi_u32 v19, v7, v13
+; GISEL-NEXT: v_mul_hi_u32 v19, v8, v13
; GISEL-NEXT: v_mul_hi_u32 v13, v9, v13
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v17, v12
; GISEL-NEXT: v_mul_lo_u32 v17, v10, v16
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v15
-; GISEL-NEXT: v_mul_hi_u32 v15, v8, v16
+; GISEL-NEXT: v_mul_hi_u32 v15, v7, v16
; GISEL-NEXT: v_mul_hi_u32 v16, v10, v16
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v18
-; GISEL-NEXT: v_mul_lo_u32 v18, v8, v12
+; GISEL-NEXT: v_mul_lo_u32 v18, v7, v12
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v18
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v17, v15
-; GISEL-NEXT: v_mul_lo_u32 v15, v7, v11
+; GISEL-NEXT: v_mul_lo_u32 v15, v8, v11
; GISEL-NEXT: v_mul_lo_u32 v17, v9, v11
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v15
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v19
-; GISEL-NEXT: v_mul_hi_u32 v14, v7, v11
+; GISEL-NEXT: v_mul_hi_u32 v14, v8, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v9, v11
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v15, s[4:5], v15, v19
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v17, v14
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v18, v17
-; GISEL-NEXT: v_mul_hi_u32 v18, v8, v12
+; GISEL-NEXT: v_mul_hi_u32 v18, v7, v12
; GISEL-NEXT: v_mul_hi_u32 v12, v10, v12
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v19, v16
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v18, v17
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v13
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v13
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v11, vcc
-; GISEL-NEXT: v_mul_lo_u32 v11, s6, v7
-; GISEL-NEXT: v_mul_lo_u32 v13, s7, v7
-; GISEL-NEXT: v_mul_hi_u32 v14, s6, v7
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v16
+; GISEL-NEXT: v_mul_lo_u32 v11, s6, v8
+; GISEL-NEXT: v_mul_lo_u32 v13, s7, v8
+; GISEL-NEXT: v_mul_hi_u32 v14, s6, v8
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v16
; GISEL-NEXT: v_addc_u32_e32 v10, vcc, v10, v12, vcc
-; GISEL-NEXT: v_mul_lo_u32 v12, s9, v8
-; GISEL-NEXT: v_mul_lo_u32 v15, s10, v8
-; GISEL-NEXT: v_mul_hi_u32 v16, s9, v8
+; GISEL-NEXT: v_mul_lo_u32 v12, s9, v7
+; GISEL-NEXT: v_mul_lo_u32 v15, s10, v7
+; GISEL-NEXT: v_mul_hi_u32 v16, s9, v7
; GISEL-NEXT: v_mul_lo_u32 v17, s6, v9
; GISEL-NEXT: v_mul_lo_u32 v18, v9, v11
-; GISEL-NEXT: v_mul_hi_u32 v19, v7, v11
+; GISEL-NEXT: v_mul_hi_u32 v19, v8, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v9, v11
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v17
; GISEL-NEXT: v_mul_lo_u32 v17, s9, v10
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v17
; GISEL-NEXT: v_mul_lo_u32 v17, v10, v12
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
-; GISEL-NEXT: v_mul_hi_u32 v14, v8, v12
+; GISEL-NEXT: v_mul_hi_u32 v14, v7, v12
; GISEL-NEXT: v_mul_hi_u32 v12, v10, v12
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16
-; GISEL-NEXT: v_mul_lo_u32 v16, v8, v15
+; GISEL-NEXT: v_mul_lo_u32 v16, v7, v15
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v16, v14
-; GISEL-NEXT: v_mul_lo_u32 v14, v7, v13
+; GISEL-NEXT: v_mul_lo_u32 v14, v8, v13
; GISEL-NEXT: v_mul_lo_u32 v16, v9, v13
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v18, v14
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v19
-; GISEL-NEXT: v_mul_hi_u32 v14, v7, v13
+; GISEL-NEXT: v_mul_hi_u32 v14, v8, v13
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v18, s[4:5], v18, v19
; GISEL-NEXT: v_mul_lo_u32 v19, v10, v15
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v16, v14
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v17, v16
-; GISEL-NEXT: v_mul_hi_u32 v17, v8, v15
+; GISEL-NEXT: v_mul_hi_u32 v17, v7, v15
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v19, v12
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v17
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v16
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v13, vcc
-; GISEL-NEXT: v_mul_lo_u32 v11, v1, v7
-; GISEL-NEXT: v_mul_hi_u32 v13, v0, v7
-; GISEL-NEXT: v_mul_hi_u32 v7, v1, v7
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT: v_mul_lo_u32 v11, v1, v8
+; GISEL-NEXT: v_mul_hi_u32 v13, v0, v8
+; GISEL-NEXT: v_mul_hi_u32 v8, v1, v8
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v12
; GISEL-NEXT: v_addc_u32_e32 v10, vcc, v10, v14, vcc
-; GISEL-NEXT: v_mul_lo_u32 v12, v3, v8
-; GISEL-NEXT: v_mul_hi_u32 v14, v2, v8
-; GISEL-NEXT: v_mul_hi_u32 v8, v3, v8
+; GISEL-NEXT: v_mul_lo_u32 v12, v3, v7
+; GISEL-NEXT: v_mul_hi_u32 v14, v2, v7
+; GISEL-NEXT: v_mul_hi_u32 v7, v3, v7
; GISEL-NEXT: v_mul_lo_u32 v15, v0, v9
; GISEL-NEXT: v_mul_lo_u32 v16, v1, v9
; GISEL-NEXT: v_mul_hi_u32 v17, v0, v9
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14
; GISEL-NEXT: v_mul_hi_u32 v11, v2, v10
; GISEL-NEXT: v_mul_hi_u32 v10, v3, v10
-; GISEL-NEXT: v_add_i32_e64 v7, s[6:7], v16, v7
+; GISEL-NEXT: v_add_i32_e64 v8, s[6:7], v16, v8
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[6:7]
-; GISEL-NEXT: v_add_i32_e64 v8, s[6:7], v13, v8
+; GISEL-NEXT: v_add_i32_e64 v7, s[6:7], v13, v7
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[6:7]
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v17
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v17
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v17
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v16
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v13, v11
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v15
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v15
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
-; GISEL-NEXT: v_mul_lo_u32 v14, s8, v7
-; GISEL-NEXT: v_mul_lo_u32 v15, 0, v7
-; GISEL-NEXT: v_mul_hi_u32 v7, s8, v7
-; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
-; GISEL-NEXT: v_mul_lo_u32 v12, s8, v8
-; GISEL-NEXT: v_mul_lo_u32 v16, 0, v8
+; GISEL-NEXT: v_mul_lo_u32 v14, s8, v8
+; GISEL-NEXT: v_mul_lo_u32 v15, 0, v8
; GISEL-NEXT: v_mul_hi_u32 v8, s8, v8
+; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT: v_mul_lo_u32 v12, s8, v7
+; GISEL-NEXT: v_mul_lo_u32 v16, 0, v7
+; GISEL-NEXT: v_mul_hi_u32 v7, s8, v7
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v13
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_mul_lo_u32 v9, s8, v9
; GISEL-NEXT: v_mul_lo_u32 v10, s8, v10
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v15, v9
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v16, v10
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v9, v7
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v14
-; GISEL-NEXT: v_subb_u32_e64 v9, s[4:5], v1, v7, vcc
-; GISEL-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v7
+; GISEL-NEXT: v_subb_u32_e64 v9, s[4:5], v1, v8, vcc
+; GISEL-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v8
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v12
-; GISEL-NEXT: v_subb_u32_e64 v10, s[6:7], v3, v8, s[4:5]
-; GISEL-NEXT: v_sub_i32_e64 v3, s[6:7], v3, v8
+; GISEL-NEXT: v_subb_u32_e64 v10, s[6:7], v3, v7, s[4:5]
+; GISEL-NEXT: v_sub_i32_e64 v3, s[6:7], v3, v7
; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v2, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[6:7]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e64 v6, v6, v8, s[6:7]
; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10
-; GISEL-NEXT: v_cndmask_b32_e32 v7, v19, v8, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v7, v19, v7, vcc
; GISEL-NEXT: v_subbrev_u32_e64 v3, vcc, 0, v3, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v8, vcc, v0, v4
; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_mov_b32 s8, 0x12d8fb
; CGP-NEXT: v_mov_b32_e32 v4, 0x12d8fb
-; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
+; CGP-NEXT: v_cvt_f32_u32_e32 v5, 0x12d8fb
+; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
; CGP-NEXT: s_mov_b32 s6, 0xffed2705
; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000
; CGP-NEXT: s_bfe_i32 s5, -1, 0x10000
-; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
+; CGP-NEXT: v_cvt_f32_u32_e32 v7, 0x12d8fb
+; CGP-NEXT: v_cvt_f32_ubyte0_e32 v8, 0
; CGP-NEXT: s_bfe_i32 s7, -1, 0x10000
; CGP-NEXT: s_bfe_i32 s9, -1, 0x10000
-; CGP-NEXT: v_cvt_f32_u32_e32 v7, s8
-; CGP-NEXT: v_mov_b32_e32 v8, s4
+; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
+; CGP-NEXT: v_mov_b32_e32 v6, s4
; CGP-NEXT: v_mov_b32_e32 v9, s5
-; CGP-NEXT: v_cvt_f32_u32_e32 v10, v4
-; CGP-NEXT: v_mac_f32_e32 v7, 0x4f800000, v5
-; CGP-NEXT: v_mac_f32_e32 v10, 0x4f800000, v6
-; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v7
-; CGP-NEXT: v_rcp_iflag_f32_e32 v6, v10
+; CGP-NEXT: v_mac_f32_e32 v7, 0x4f800000, v8
+; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v5
+; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7
; CGP-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
-; CGP-NEXT: v_mul_f32_e32 v6, 0x5f7ffffc, v6
-; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5
-; CGP-NEXT: v_mul_f32_e32 v10, 0x2f800000, v6
-; CGP-NEXT: v_trunc_f32_e32 v7, v7
+; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
+; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v5
+; CGP-NEXT: v_mul_f32_e32 v10, 0x2f800000, v7
+; CGP-NEXT: v_trunc_f32_e32 v8, v8
; CGP-NEXT: v_trunc_f32_e32 v10, v10
-; CGP-NEXT: v_mac_f32_e32 v5, 0xcf800000, v7
-; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT: v_mac_f32_e32 v6, 0xcf800000, v10
+; CGP-NEXT: v_mac_f32_e32 v5, 0xcf800000, v8
+; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
+; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v10
; CGP-NEXT: v_cvt_u32_f32_e32 v10, v10
; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5
-; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
-; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6
+; CGP-NEXT: v_mul_lo_u32 v11, s6, v8
+; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_mul_lo_u32 v12, s6, v10
; CGP-NEXT: v_mul_lo_u32 v13, s6, v5
; CGP-NEXT: v_mul_lo_u32 v14, -1, v5
; CGP-NEXT: v_mul_hi_u32 v15, s6, v5
-; CGP-NEXT: v_mul_lo_u32 v16, s6, v6
-; CGP-NEXT: v_mul_lo_u32 v17, -1, v6
-; CGP-NEXT: v_mul_hi_u32 v18, s6, v6
+; CGP-NEXT: v_mul_lo_u32 v16, s6, v7
+; CGP-NEXT: v_mul_lo_u32 v17, -1, v7
+; CGP-NEXT: v_mul_hi_u32 v18, s6, v7
; CGP-NEXT: v_add_i32_e32 v11, vcc, v14, v11
-; CGP-NEXT: v_mul_lo_u32 v14, v7, v13
+; CGP-NEXT: v_mul_lo_u32 v14, v8, v13
; CGP-NEXT: v_mul_hi_u32 v19, v5, v13
-; CGP-NEXT: v_mul_hi_u32 v13, v7, v13
+; CGP-NEXT: v_mul_hi_u32 v13, v8, v13
; CGP-NEXT: v_add_i32_e32 v12, vcc, v17, v12
; CGP-NEXT: v_mul_lo_u32 v17, v10, v16
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v15
-; CGP-NEXT: v_mul_hi_u32 v15, v6, v16
+; CGP-NEXT: v_mul_hi_u32 v15, v7, v16
; CGP-NEXT: v_mul_hi_u32 v16, v10, v16
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v18
-; CGP-NEXT: v_mul_lo_u32 v18, v6, v12
+; CGP-NEXT: v_mul_lo_u32 v18, v7, v12
; CGP-NEXT: v_add_i32_e32 v17, vcc, v17, v18
; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v15
; CGP-NEXT: v_mul_lo_u32 v15, v5, v11
-; CGP-NEXT: v_mul_lo_u32 v17, v7, v11
+; CGP-NEXT: v_mul_lo_u32 v17, v8, v11
; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v14, v15
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v14, v19
; CGP-NEXT: v_mul_hi_u32 v14, v5, v11
-; CGP-NEXT: v_mul_hi_u32 v11, v7, v11
+; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v15, s[4:5], v15, v19
; CGP-NEXT: v_mul_lo_u32 v19, v10, v12
; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v17, v14
; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v17, vcc, v18, v17
-; CGP-NEXT: v_mul_hi_u32 v18, v6, v12
+; CGP-NEXT: v_mul_hi_u32 v18, v7, v12
; CGP-NEXT: v_mul_hi_u32 v12, v10, v12
; CGP-NEXT: v_add_i32_e32 v16, vcc, v19, v16
; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v15
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v13
-; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v11, vcc
+; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v11, vcc
; CGP-NEXT: v_mul_lo_u32 v11, s6, v5
; CGP-NEXT: v_mul_lo_u32 v13, -1, v5
; CGP-NEXT: v_mul_hi_u32 v14, s6, v5
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v16
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v16
; CGP-NEXT: v_addc_u32_e32 v10, vcc, v10, v12, vcc
-; CGP-NEXT: v_mul_lo_u32 v12, s6, v6
-; CGP-NEXT: v_mul_lo_u32 v15, -1, v6
-; CGP-NEXT: v_mul_hi_u32 v16, s6, v6
-; CGP-NEXT: v_mul_lo_u32 v17, s6, v7
-; CGP-NEXT: v_mul_lo_u32 v18, v7, v11
+; CGP-NEXT: v_mul_lo_u32 v12, s6, v7
+; CGP-NEXT: v_mul_lo_u32 v15, -1, v7
+; CGP-NEXT: v_mul_hi_u32 v16, s6, v7
+; CGP-NEXT: v_mul_lo_u32 v17, s6, v8
+; CGP-NEXT: v_mul_lo_u32 v18, v8, v11
; CGP-NEXT: v_mul_hi_u32 v19, v5, v11
-; CGP-NEXT: v_mul_hi_u32 v11, v7, v11
+; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v17
; CGP-NEXT: v_mul_lo_u32 v17, s6, v10
; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v17
; CGP-NEXT: v_mul_lo_u32 v17, v10, v12
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
-; CGP-NEXT: v_mul_hi_u32 v14, v6, v12
+; CGP-NEXT: v_mul_hi_u32 v14, v7, v12
; CGP-NEXT: v_mul_hi_u32 v12, v10, v12
; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v16
-; CGP-NEXT: v_mul_lo_u32 v16, v6, v15
+; CGP-NEXT: v_mul_lo_u32 v16, v7, v15
; CGP-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v16, v14
; CGP-NEXT: v_mul_lo_u32 v14, v5, v13
-; CGP-NEXT: v_mul_lo_u32 v16, v7, v13
+; CGP-NEXT: v_mul_lo_u32 v16, v8, v13
; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v18, v14
; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v14, v19
; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v16, v14
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v16, vcc, v17, v16
-; CGP-NEXT: v_mul_hi_u32 v17, v6, v15
+; CGP-NEXT: v_mul_hi_u32 v17, v7, v15
; CGP-NEXT: v_add_i32_e32 v12, vcc, v19, v12
; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v17
; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v18
; CGP-NEXT: v_mov_b32_e32 v18, s9
-; CGP-NEXT: v_mul_hi_u32 v13, v7, v13
+; CGP-NEXT: v_mul_hi_u32 v13, v8, v13
; CGP-NEXT: v_mul_hi_u32 v15, v10, v15
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v16
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v16
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v11
-; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v13, vcc
+; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v13, vcc
; CGP-NEXT: v_mul_lo_u32 v11, v1, v5
; CGP-NEXT: v_mul_hi_u32 v13, v0, v5
; CGP-NEXT: v_mul_hi_u32 v5, v1, v5
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v12
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v12
; CGP-NEXT: v_addc_u32_e32 v10, vcc, v10, v14, vcc
-; CGP-NEXT: v_mul_lo_u32 v12, v3, v6
-; CGP-NEXT: v_mul_hi_u32 v14, v2, v6
-; CGP-NEXT: v_mul_hi_u32 v6, v3, v6
-; CGP-NEXT: v_mul_lo_u32 v15, v0, v7
-; CGP-NEXT: v_mul_lo_u32 v16, v1, v7
-; CGP-NEXT: v_mul_hi_u32 v17, v0, v7
-; CGP-NEXT: v_mul_hi_u32 v7, v1, v7
+; CGP-NEXT: v_mul_lo_u32 v12, v3, v7
+; CGP-NEXT: v_mul_hi_u32 v14, v2, v7
+; CGP-NEXT: v_mul_hi_u32 v7, v3, v7
+; CGP-NEXT: v_mul_lo_u32 v15, v0, v8
+; CGP-NEXT: v_mul_lo_u32 v16, v1, v8
+; CGP-NEXT: v_mul_hi_u32 v17, v0, v8
+; CGP-NEXT: v_mul_hi_u32 v8, v1, v8
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v15
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; CGP-NEXT: v_mul_hi_u32 v10, v3, v10
; CGP-NEXT: v_add_i32_e64 v5, s[6:7], v16, v5
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[6:7]
-; CGP-NEXT: v_add_i32_e64 v6, s[6:7], v13, v6
+; CGP-NEXT: v_add_i32_e64 v7, s[6:7], v13, v7
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[6:7]
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v17
; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v16
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v11
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v11
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v17
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v16
; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v15
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v12
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_mul_lo_u32 v14, s8, v5
; CGP-NEXT: v_mul_lo_u32 v15, 0, v5
; CGP-NEXT: v_mul_hi_u32 v5, s8, v5
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT: v_mul_lo_u32 v12, s8, v6
-; CGP-NEXT: v_mul_lo_u32 v16, 0, v6
-; CGP-NEXT: v_mul_hi_u32 v6, s8, v6
-; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v13
+; CGP-NEXT: v_mul_lo_u32 v12, s8, v7
+; CGP-NEXT: v_mul_lo_u32 v16, 0, v7
+; CGP-NEXT: v_mul_hi_u32 v7, s8, v7
+; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v13
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11
-; CGP-NEXT: v_mul_lo_u32 v7, s8, v7
+; CGP-NEXT: v_mul_lo_u32 v8, s8, v8
; CGP-NEXT: v_mul_lo_u32 v10, s8, v10
-; CGP-NEXT: v_add_i32_e32 v7, vcc, v15, v7
+; CGP-NEXT: v_add_i32_e32 v8, vcc, v15, v8
; CGP-NEXT: v_add_i32_e32 v10, vcc, v16, v10
-; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v10, v6
+; CGP-NEXT: v_add_i32_e32 v5, vcc, v8, v5
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v14
-; CGP-NEXT: v_subb_u32_e64 v7, s[4:5], v1, v5, vcc
+; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v5, vcc
; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v5
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v4
; CGP-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; CGP-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v12
-; CGP-NEXT: v_subb_u32_e64 v10, s[6:7], v3, v6, s[4:5]
-; CGP-NEXT: v_sub_i32_e64 v3, s[6:7], v3, v6
+; CGP-NEXT: v_subb_u32_e64 v10, s[6:7], v3, v7, s[4:5]
+; CGP-NEXT: v_sub_i32_e64 v3, s[6:7], v3, v7
; CGP-NEXT: v_cmp_ge_u32_e64 s[6:7], v2, v4
-; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[6:7]
-; CGP-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v7
-; CGP-NEXT: v_cndmask_b32_e64 v5, v8, v5, s[6:7]
+; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[6:7]
+; CGP-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v8
+; CGP-NEXT: v_cndmask_b32_e64 v5, v6, v5, s[6:7]
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10
-; CGP-NEXT: v_cndmask_b32_e32 v6, v19, v6, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v6, v19, v7, vcc
; CGP-NEXT: v_subbrev_u32_e64 v3, vcc, 0, v3, s[4:5]
-; CGP-NEXT: v_sub_i32_e32 v8, vcc, v0, v4
+; CGP-NEXT: v_sub_i32_e32 v7, vcc, v0, v4
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v8, v4
+; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v7, v4
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
; CGP-NEXT: v_sub_i32_e32 v12, vcc, v2, v4
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
-; CGP-NEXT: v_sub_i32_e32 v11, vcc, v8, v4
+; CGP-NEXT: v_sub_i32_e32 v11, vcc, v7, v4
; CGP-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v1, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e32 v13, v18, v13, vcc
; CGP-NEXT: v_sub_i32_e32 v4, vcc, v12, v4
; CGP-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v3, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
-; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v13
; CGP-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[4:5]
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v14, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
-; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; CGP-NEXT: v_cndmask_b32_e64 v3, v3, v15, s[4:5]
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6
; CGP-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[4:5]
-; CGP-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v3, v10, v3, s[4:5]
; CGP-NEXT: s_setpc_b64 s[30:31]
%result = urem <2 x i64> %num, <i64 1235195, i64 1235195>
; GISEL-LABEL: v_urem_i64_24bit:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s4, 0xffffff
-; GISEL-NEXT: v_and_b32_e32 v0, s4, v0
-; GISEL-NEXT: v_and_b32_e32 v1, s4, v2
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v2
; GISEL-NEXT: v_cvt_f32_u32_e32 v2, v1
; GISEL-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
; GISEL-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-LABEL: v_urem_i64_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s4, 0xffffff
-; CGP-NEXT: v_and_b32_e32 v0, s4, v0
-; CGP-NEXT: v_and_b32_e32 v1, s4, v2
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v0
; CGP-NEXT: v_cvt_f32_u32_e32 v3, v1
; CGP-NEXT: v_rcp_f32_e32 v4, v3
; GISEL-LABEL: v_urem_v2i64_24bit:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s6, 0xffffff
-; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v7, 0
-; GISEL-NEXT: v_and_b32_e32 v3, s6, v4
-; GISEL-NEXT: v_and_b32_e32 v1, s6, v6
-; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3
+; GISEL-NEXT: v_and_b32_e32 v3, 0xffffff, v4
+; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v6
+; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
+; GISEL-NEXT: v_cvt_f32_u32_e32 v7, v3
; GISEL-NEXT: v_sub_i32_e32 v4, vcc, 0, v3
; GISEL-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, vcc
; GISEL-NEXT: v_cvt_f32_u32_e32 v8, v1
; GISEL-NEXT: v_sub_i32_e32 v9, vcc, 0, v1
; GISEL-NEXT: v_subb_u32_e64 v10, s[4:5], 0, 0, vcc
-; GISEL-NEXT: v_mac_f32_e32 v6, 0x4f800000, v7
-; GISEL-NEXT: v_mac_f32_e32 v8, 0x4f800000, v7
-; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6
+; GISEL-NEXT: v_mac_f32_e32 v7, 0x4f800000, v6
+; GISEL-NEXT: v_mac_f32_e32 v8, 0x4f800000, v6
+; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v7
; GISEL-NEXT: v_rcp_iflag_f32_e32 v7, v8
; GISEL-NEXT: v_mul_f32_e32 v6, 0x5f7ffffc, v6
; GISEL-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
; GISEL-NEXT: v_cvt_u32_f32_e32 v8, v8
; GISEL-NEXT: v_mac_f32_e32 v7, 0xcf800000, v11
; GISEL-NEXT: v_cvt_u32_f32_e32 v11, v11
-; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GISEL-NEXT: v_mul_lo_u32 v12, v4, v8
+; GISEL-NEXT: v_cvt_u32_f32_e32 v12, v6
+; GISEL-NEXT: v_mul_lo_u32 v6, v4, v8
; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7
; GISEL-NEXT: v_mul_lo_u32 v13, v9, v11
-; GISEL-NEXT: v_mul_lo_u32 v14, v4, v6
-; GISEL-NEXT: v_mul_lo_u32 v15, v5, v6
-; GISEL-NEXT: v_mul_hi_u32 v16, v4, v6
+; GISEL-NEXT: v_mul_lo_u32 v14, v4, v12
+; GISEL-NEXT: v_mul_lo_u32 v15, v5, v12
+; GISEL-NEXT: v_mul_hi_u32 v16, v4, v12
; GISEL-NEXT: v_mul_lo_u32 v17, v9, v7
; GISEL-NEXT: v_mul_lo_u32 v18, v10, v7
; GISEL-NEXT: v_mul_hi_u32 v19, v9, v7
-; GISEL-NEXT: v_add_i32_e32 v12, vcc, v15, v12
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, v15, v6
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v18, v13
; GISEL-NEXT: v_mul_lo_u32 v15, v11, v17
; GISEL-NEXT: v_mul_hi_u32 v18, v7, v17
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v18
; GISEL-NEXT: v_mul_lo_u32 v15, v8, v14
-; GISEL-NEXT: v_mul_hi_u32 v18, v6, v14
+; GISEL-NEXT: v_mul_hi_u32 v18, v12, v14
; GISEL-NEXT: v_mul_hi_u32 v14, v8, v14
; GISEL-NEXT: v_mul_hi_u32 v17, v11, v17
-; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v16
-; GISEL-NEXT: v_mul_lo_u32 v16, v6, v12
-; GISEL-NEXT: v_add_i32_e64 v15, s[4:5], v15, v16
-; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v15, s[4:5], v15, v18
-; GISEL-NEXT: v_mul_lo_u32 v15, v8, v12
-; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v16, s[4:5], v16, v18
-; GISEL-NEXT: v_mul_hi_u32 v18, v6, v12
-; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v15, v14
+; GISEL-NEXT: v_add_i32_e64 v16, s[4:5], v6, v16
+; GISEL-NEXT: v_mul_lo_u32 v6, v12, v16
+; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v15, v6
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v18
+; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v18
+; GISEL-NEXT: v_mul_lo_u32 v6, v8, v16
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v15, s[4:5], v15, v18
-; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v18, vcc, v19, v18
-; GISEL-NEXT: v_mul_lo_u32 v19, v11, v13
-; GISEL-NEXT: v_add_i32_e32 v17, vcc, v19, v17
-; GISEL-NEXT: v_mul_hi_u32 v19, v7, v13
+; GISEL-NEXT: v_mul_hi_u32 v18, v12, v16
+; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v14
+; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v18, s[4:5], v6, v18
+; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v6
+; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v19, vcc, v19, v6
+; GISEL-NEXT: v_mul_lo_u32 v6, v11, v13
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v17
+; GISEL-NEXT: v_mul_hi_u32 v17, v7, v13
; GISEL-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v19
-; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v19, vcc, v20, v19
+; GISEL-NEXT: v_add_i32_e32 v17, vcc, v6, v17
+; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v20, vcc, v20, v6
+; GISEL-NEXT: v_and_b32_e32 v6, 0xffffff, v0
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v2
; GISEL-NEXT: s_bfe_i32 s4, -1, 0x10000
; GISEL-NEXT: s_bfe_i32 s5, -1, 0x10000
+; GISEL-NEXT: s_bfe_i32 s6, -1, 0x10000
; GISEL-NEXT: s_bfe_i32 s7, -1, 0x10000
-; GISEL-NEXT: s_bfe_i32 s8, -1, 0x10000
-; GISEL-NEXT: v_and_b32_e32 v0, s6, v0
-; GISEL-NEXT: v_and_b32_e32 v2, s6, v2
-; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16
-; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16
-; GISEL-NEXT: v_mov_b32_e32 v16, s4
-; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v18
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v18, v15
+; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v15
+; GISEL-NEXT: v_mov_b32_e32 v15, s4
+; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v19
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v18, vcc, v19, v18
+; GISEL-NEXT: v_add_i32_e32 v18, vcc, v20, v18
; GISEL-NEXT: v_mov_b32_e32 v19, s5
-; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12
-; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15
-; GISEL-NEXT: v_mov_b32_e32 v15, s7
+; GISEL-NEXT: v_mul_hi_u32 v16, v8, v16
+; GISEL-NEXT: v_add_i32_e32 v14, vcc, v16, v14
+; GISEL-NEXT: v_mov_b32_e32 v16, s6
; GISEL-NEXT: v_mul_hi_u32 v13, v11, v13
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v18
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v14
-; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v12, vcc
-; GISEL-NEXT: v_mul_lo_u32 v12, v4, v6
-; GISEL-NEXT: v_mul_lo_u32 v5, v5, v6
-; GISEL-NEXT: v_mul_hi_u32 v14, v4, v6
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v12, v2
+; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v14, vcc
+; GISEL-NEXT: v_mul_lo_u32 v12, v4, v2
+; GISEL-NEXT: v_mul_lo_u32 v5, v5, v2
+; GISEL-NEXT: v_mul_hi_u32 v14, v4, v2
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v17
; GISEL-NEXT: v_addc_u32_e32 v11, vcc, v11, v13, vcc
; GISEL-NEXT: v_mul_lo_u32 v13, v9, v7
; GISEL-NEXT: v_mul_lo_u32 v4, v4, v8
; GISEL-NEXT: v_mul_lo_u32 v18, v8, v12
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT: v_mul_hi_u32 v5, v6, v12
+; GISEL-NEXT: v_mul_hi_u32 v5, v2, v12
; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12
; GISEL-NEXT: v_mul_lo_u32 v9, v9, v11
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v17
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v14
-; GISEL-NEXT: v_mul_lo_u32 v10, v6, v4
+; GISEL-NEXT: v_mul_lo_u32 v10, v2, v4
; GISEL-NEXT: v_mul_lo_u32 v14, v8, v4
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v18, v10
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5
-; GISEL-NEXT: v_mul_hi_u32 v5, v6, v4
+; GISEL-NEXT: v_mul_hi_u32 v5, v2, v4
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v18, v10
; GISEL-NEXT: v_mul_lo_u32 v18, v11, v9
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v17
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v18, v17
-; GISEL-NEXT: v_mov_b32_e32 v18, s8
+; GISEL-NEXT: v_mov_b32_e32 v18, s7
; GISEL-NEXT: v_mul_hi_u32 v4, v8, v4
; GISEL-NEXT: v_mul_hi_u32 v9, v11, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v10
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v17, v14
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GISEL-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GISEL-NEXT: v_mul_lo_u32 v6, 0, v5
-; GISEL-NEXT: v_mul_hi_u32 v8, v0, v5
-; GISEL-NEXT: v_mul_hi_u32 v5, 0, v5
+; GISEL-NEXT: v_mul_lo_u32 v5, 0, v2
+; GISEL-NEXT: v_mul_hi_u32 v8, v6, v2
+; GISEL-NEXT: v_mul_hi_u32 v2, 0, v2
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v13
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v11, v9, vcc
; GISEL-NEXT: v_mul_lo_u32 v10, 0, v7
-; GISEL-NEXT: v_mul_hi_u32 v11, v2, v7
+; GISEL-NEXT: v_mul_hi_u32 v11, v0, v7
; GISEL-NEXT: v_mul_hi_u32 v7, 0, v7
-; GISEL-NEXT: v_mul_lo_u32 v12, v0, v4
+; GISEL-NEXT: v_mul_lo_u32 v12, v6, v4
; GISEL-NEXT: v_mul_lo_u32 v13, 0, v4
-; GISEL-NEXT: v_mul_hi_u32 v14, v0, v4
+; GISEL-NEXT: v_mul_hi_u32 v14, v6, v4
; GISEL-NEXT: v_mul_hi_u32 v4, 0, v4
-; GISEL-NEXT: v_mul_lo_u32 v17, v2, v9
+; GISEL-NEXT: v_mul_lo_u32 v17, v0, v9
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v17
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_mul_lo_u32 v10, 0, v9
-; GISEL-NEXT: v_mul_hi_u32 v11, v2, v9
+; GISEL-NEXT: v_mul_hi_u32 v11, v0, v9
; GISEL-NEXT: v_mul_hi_u32 v9, 0, v9
-; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v12
+; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v13, v5
+; GISEL-NEXT: v_add_i32_e64 v2, s[4:5], v13, v2
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v14
+; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v2, s[4:5], v2, v14
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v12, v6
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v12, v5
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v13, v8
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v17, v14
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v12
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v8, v6
-; GISEL-NEXT: v_mul_lo_u32 v8, v3, v5
-; GISEL-NEXT: v_mul_lo_u32 v12, 0, v5
-; GISEL-NEXT: v_mul_hi_u32 v5, v3, v5
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v8, v5
+; GISEL-NEXT: v_mul_lo_u32 v8, v3, v2
+; GISEL-NEXT: v_mul_lo_u32 v12, 0, v2
+; GISEL-NEXT: v_mul_hi_u32 v2, v3, v2
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_mul_lo_u32 v11, v1, v7
; GISEL-NEXT: v_mul_lo_u32 v13, 0, v7
; GISEL-NEXT: v_mul_hi_u32 v7, v1, v7
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v9, v10
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v9, v10
; GISEL-NEXT: v_mul_lo_u32 v4, v3, v4
-; GISEL-NEXT: v_mul_lo_u32 v6, v1, v6
+; GISEL-NEXT: v_mul_lo_u32 v5, v1, v5
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v12, v4
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v13, v6
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v7
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
-; GISEL-NEXT: v_subb_u32_e64 v6, s[4:5], 0, v4, vcc
-; GISEL-NEXT: v_sub_i32_e64 v4, s[4:5], 0, v4
-; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v3
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v13, v5
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v4, v2
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v7
+; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v6, v8
+; GISEL-NEXT: v_subb_u32_e64 v6, s[4:5], 0, v2, vcc
+; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], 0, v2
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v3
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v11
-; GISEL-NEXT: v_subb_u32_e64 v8, s[6:7], 0, v5, s[4:5]
-; GISEL-NEXT: v_sub_i32_e64 v5, s[6:7], 0, v5
-; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v2, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[6:7]
+; GISEL-NEXT: v_sub_i32_e64 v8, s[4:5], v0, v11
+; GISEL-NEXT: v_subb_u32_e64 v9, s[6:7], 0, v4, s[4:5]
+; GISEL-NEXT: v_sub_i32_e64 v0, s[6:7], 0, v4
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v8, v1
+; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[6:7]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v7, v16, v7, s[6:7]
-; GISEL-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8
-; GISEL-NEXT: v_cndmask_b32_e32 v9, v15, v9, vcc
-; GISEL-NEXT: v_subbrev_u32_e64 v5, vcc, 0, v5, s[4:5]
-; GISEL-NEXT: v_sub_i32_e32 v10, vcc, v0, v3
-; GISEL-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v7, v15, v7, s[6:7]
+; GISEL-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
+; GISEL-NEXT: v_cndmask_b32_e32 v4, v16, v4, vcc
+; GISEL-NEXT: v_subbrev_u32_e64 v0, vcc, 0, v0, s[4:5]
+; GISEL-NEXT: v_sub_i32_e32 v10, vcc, v5, v3
+; GISEL-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v10, v3
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
-; GISEL-NEXT: v_sub_i32_e32 v12, vcc, v2, v1
-; GISEL-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
+; GISEL-NEXT: v_sub_i32_e32 v12, vcc, v8, v1
+; GISEL-NEXT: v_subbrev_u32_e32 v13, vcc, 0, v0, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v12, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GISEL-NEXT: v_cndmask_b32_e32 v11, v19, v11, vcc
; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v10, v3
-; GISEL-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v4, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
-; GISEL-NEXT: v_cndmask_b32_e32 v13, v18, v13, vcc
+; GISEL-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v2, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v13
+; GISEL-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v12, v1
-; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v5, vcc
+; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v13, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v13
+; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
; GISEL-NEXT: v_cndmask_b32_e64 v1, v12, v1, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v10, v2, v14, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v3, v5, v15, s[4:5]
-; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v1, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v4, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v3, v13, v15, s[4:5]
+; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v4
+; GISEL-NEXT: v_cndmask_b32_e64 v2, v8, v1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v10, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v3, v9, v3, s[4:5]
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; CGP-LABEL: v_urem_v2i64_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s6, 0xffffff
-; CGP-NEXT: v_and_b32_e32 v0, s6, v0
-; CGP-NEXT: v_and_b32_e32 v1, s6, v2
-; CGP-NEXT: v_and_b32_e32 v2, s6, v4
-; CGP-NEXT: v_and_b32_e32 v3, s6, v6
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v2
+; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v4
+; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v6
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v0
; CGP-NEXT: v_cvt_f32_u32_e32 v5, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v6, v1
; CGP-NEXT: v_mul_lo_u32 v3, v5, v3
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
-; CGP-NEXT: v_and_b32_e32 v0, s6, v0
-; CGP-NEXT: v_and_b32_e32 v2, s6, v1
+; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v1
; CGP-NEXT: v_mov_b32_e32 v1, 0
; CGP-NEXT: v_mov_b32_e32 v3, 0
; CGP-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v2
-; GFX9-NEXT: v_and_b32_e32 v2, s4, v1
+; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: s_mov_b32 s5, 24
; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v2
-; GFX9-NEXT: v_and_b32_e32 v2, s0, v1
+; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX9PLUS: global_load_dword [[B:v[0-9]+]]
; GFX9PLUS: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]]
-; GFX9-DAG: v_and_b32_e32 v[[ELT0:[0-9]+]], [[MASK]], [[ADD]]
-; GFX10-DAG: v_and_b32_e32 v[[ELT0:[0-9]+]], 0xffff, [[ADD]]
+; GFX9PLUS-DAG: v_and_b32_e32 v[[ELT0:[0-9]+]], 0xffff, [[ADD]]
; GFX9PLUS-DAG: v_and_b32_sdwa v{{[0-9]+}}, [[MASK]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9PLUS: buffer_store_dwordx4
; GFX6-LABEL: udiv_v4i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
-; GFX6-NEXT: s_mov_b32 s3, 0x4f7ffffe
; GFX6-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s15, 0xf000
; GFX6-NEXT: s_mov_b32 s14, -1
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s11
-; GFX6-NEXT: v_mul_f32_e32 v0, s3, v0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, s3, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_mul_lo_u32 v2, s2, v0
; GFX6-NEXT: s_sub_i32 s2, 0, s9
; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v4
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s5, v5
-; GFX6-NEXT: v_mul_f32_e32 v2, s3, v2
+; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v1
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v3
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX6-NEXT: v_mul_hi_u32 v2, s6, v2
-; GFX6-NEXT: v_mul_f32_e32 v4, s3, v4
+; GFX6-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX6-NEXT: v_mul_lo_u32 v3, v2, s10
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v2
; GFX9-LABEL: udiv_v4i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
-; GFX9-NEXT: s_mov_b32 s12, 0x4f7ffffe
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s10
-; GFX9-NEXT: v_mul_f32_e32 v0, s12, v0
+; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s11
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, s12, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0
; GFX9-NEXT: s_sub_i32 s2, 0, s10
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT: v_mul_f32_e32 v3, s12, v5
-; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
-; GFX9-NEXT: v_mul_lo_u32 v5, v0, s8
-; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s11
-; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_mul_lo_u32 v3, v0, s8
; GFX9-NEXT: v_add_u32_e32 v7, 1, v0
-; GFX9-NEXT: v_sub_u32_e32 v5, s4, v5
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v7, s8, v5
-; GFX9-NEXT: v_mul_lo_u32 v6, v1, s9
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v7, s8, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
+; GFX9-NEXT: v_mul_lo_u32 v3, s2, v2
+; GFX9-NEXT: s_sub_i32 s2, 0, s11
+; GFX9-NEXT: v_mul_lo_u32 v5, v1, s9
; GFX9-NEXT: v_add_u32_e32 v7, 1, v0
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3
+; GFX9-NEXT: v_add_u32_e32 v8, 1, v1
+; GFX9-NEXT: v_sub_u32_e32 v5, s5, v5
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
-; GFX9-NEXT: v_mul_lo_u32 v7, s2, v3
-; GFX9-NEXT: v_sub_u32_e32 v6, s5, v6
-; GFX9-NEXT: v_add_u32_e32 v5, 1, v1
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v6
-; GFX9-NEXT: v_mul_f32_e32 v2, s12, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX9-NEXT: v_mul_hi_u32 v5, v3, v7
-; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX9-NEXT: s_sub_i32 s2, 0, s11
-; GFX9-NEXT: v_subrev_u32_e32 v7, s9, v6
-; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
-; GFX9-NEXT: v_mul_lo_u32 v5, s2, v2
-; GFX9-NEXT: v_mul_hi_u32 v3, s6, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v3
+; GFX9-NEXT: v_mul_lo_u32 v3, s2, v6
+; GFX9-NEXT: v_mul_hi_u32 v2, s6, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
+; GFX9-NEXT: v_mul_hi_u32 v3, v6, v3
+; GFX9-NEXT: v_mul_lo_u32 v8, v2, s10
+; GFX9-NEXT: v_subrev_u32_e32 v7, s9, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX9-NEXT: v_add_u32_e32 v3, v6, v3
+; GFX9-NEXT: v_mul_hi_u32 v3, s7, v3
; GFX9-NEXT: v_add_u32_e32 v7, 1, v1
-; GFX9-NEXT: v_mul_hi_u32 v5, v2, v5
-; GFX9-NEXT: v_mul_lo_u32 v8, v3, s10
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v6
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5
+; GFX9-NEXT: v_sub_u32_e32 v5, s6, v8
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
-; GFX9-NEXT: v_mul_hi_u32 v5, s7, v2
-; GFX9-NEXT: v_sub_u32_e32 v6, s6, v8
-; GFX9-NEXT: v_add_u32_e32 v7, 1, v3
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v3, s10, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
-; GFX9-NEXT: v_mul_lo_u32 v6, v5, s11
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v5
+; GFX9-NEXT: v_subrev_u32_e32 v6, s10, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v6, v3, s11
; GFX9-NEXT: v_add_u32_e32 v7, 1, v2
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v3
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
-; GFX9-NEXT: v_sub_u32_e32 v3, s7, v6
-; GFX9-NEXT: v_add_u32_e32 v6, 1, v5
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
+; GFX9-NEXT: v_add_u32_e32 v7, 1, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v5
+; GFX9-NEXT: v_sub_u32_e32 v5, s7, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v6, s11, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v6, s11, v3
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v5
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
-; GFX9-NEXT: v_add_u32_e32 v6, 1, v5
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm
%r = udiv <4 x i32> %x, %y
; GFX6-LABEL: urem_v4i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
-; GFX6-NEXT: s_mov_b32 s13, 0x4f7ffffe
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
-; GFX6-NEXT: s_sub_i32 s2, 0, s8
-; GFX6-NEXT: s_sub_i32 s12, 0, s9
+; GFX6-NEXT: s_sub_i32 s12, 0, s8
+; GFX6-NEXT: s_sub_i32 s13, 0, s9
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s10
; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s11
-; GFX6-NEXT: v_mul_f32_e32 v0, s13, v0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, s13, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX6-NEXT: v_mul_lo_u32 v2, s2, v0
-; GFX6-NEXT: s_mov_b32 s2, -1
-; GFX6-NEXT: v_mul_lo_u32 v4, s12, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, s12, v0
+; GFX6-NEXT: v_mul_lo_u32 v4, s13, v1
; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v4, v1
; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s8
-; GFX6-NEXT: v_mul_f32_e32 v2, s13, v3
+; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s9
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v5
; GFX6-NEXT: s_sub_i32 s4, 0, s11
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT: v_mul_f32_e32 v3, s13, v4
+; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v4
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s9, v1
; GFX6-NEXT: v_mul_hi_u32 v2, s6, v2
; GFX9-LABEL: urem_v4i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
-; GFX9-NEXT: s_mov_b32 s12, 0x4f7ffffe
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX9-NEXT: s_sub_i32 s2, 0, s8
-; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s10
+; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s10
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: s_sub_i32 s3, 0, s9
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5
-; GFX9-NEXT: v_mul_f32_e32 v0, s12, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, s12, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s11
-; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0
-; GFX9-NEXT: s_sub_i32 s2, 0, s10
-; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1
-; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
-; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
-; GFX9-NEXT: v_mul_f32_e32 v2, s12, v5
+; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
+; GFX9-NEXT: v_mul_lo_u32 v3, s2, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v6
-; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX9-NEXT: v_mul_lo_u32 v5, s3, v1
+; GFX9-NEXT: s_sub_i32 s2, 0, s10
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3
+; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s11
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v5, s2, v2
; GFX9-NEXT: s_sub_i32 s2, 0, s11
-; GFX9-NEXT: v_mul_f32_e32 v3, s12, v3
-; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX9-NEXT: v_mul_hi_u32 v5, v2, v5
; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
-; GFX9-NEXT: v_mul_lo_u32 v0, v0, s8
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
-; GFX9-NEXT: v_mul_lo_u32 v5, s2, v3
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s8
; GFX9-NEXT: v_mul_hi_u32 v2, s6, v2
+; GFX9-NEXT: v_mul_lo_u32 v5, s2, v3
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s9
; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
-; GFX9-NEXT: v_mul_hi_u32 v5, v3, v5
; GFX9-NEXT: v_subrev_u32_e32 v6, s8, v0
+; GFX9-NEXT: v_mul_hi_u32 v5, v3, v5
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, s10
; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
; GFX9-NEXT: v_mul_hi_u32 v3, s7, v3
-; GFX9-NEXT: v_mul_lo_u32 v2, v2, s10
; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
; GFX9-NEXT: v_subrev_u32_e32 v6, s8, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; GFX6-LABEL: sdiv_v4i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
-; GFX6-NEXT: s_mov_b32 s16, 0x4f7ffffe
; GFX6-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s15, 0xf000
; GFX6-NEXT: s_mov_b32 s14, -1
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX6-NEXT: s_sub_i32 s1, 0, s3
; GFX6-NEXT: s_ashr_i32 s0, s4, 31
-; GFX6-NEXT: v_mul_f32_e32 v0, s16, v0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: s_xor_b32 s2, s0, s2
; GFX6-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX6-NEXT: s_add_i32 s1, s4, s0
-; GFX6-NEXT: v_mul_f32_e32 v1, s16, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX6-NEXT: s_xor_b32 s1, s1, s0
; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX6-NEXT: v_mul_lo_u32 v2, v1, s9
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v1
-; GFX6-NEXT: v_mul_f32_e32 v3, s16, v3
+; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s1, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v2
; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GFX6-NEXT: v_mul_lo_u32 v3, v2, s4
; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v2
-; GFX6-NEXT: v_mul_f32_e32 v4, s16, v4
+; GFX6-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s1, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s4, v3
; GFX9-LABEL: sdiv_v4i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
-; GFX9-NEXT: s_mov_b32 s15, 0x4f7ffffe
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s2, s8, 31
; GFX9-NEXT: s_add_i32 s3, s8, s2
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX9-NEXT: s_sub_i32 s14, 0, s3
; GFX9-NEXT: s_ashr_i32 s8, s4, 31
-; GFX9-NEXT: v_mul_f32_e32 v0, s15, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: s_add_i32 s4, s4, s8
; GFX9-NEXT: s_xor_b32 s4, s4, s8
; GFX9-NEXT: v_mul_lo_u32 v2, s14, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, s15, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_sub_i32 s14, 0, s9
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: v_sub_u32_e32 v2, s5, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v2
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX9-NEXT: v_mul_f32_e32 v3, s15, v3
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: v_subrev_u32_e32 v5, s9, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX9-NEXT: s_xor_b32 s6, s6, s5
; GFX9-NEXT: v_mul_hi_u32 v2, s6, v2
; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
-; GFX9-NEXT: v_mul_f32_e32 v3, s15, v3
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: v_subrev_u32_e32 v0, s2, v0
; GFX9-NEXT: s_xor_b32 s2, s13, s12
; GFX6-LABEL: srem_v4i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
-; GFX6-NEXT: s_mov_b32 s14, 0x4f7ffffe
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_add_i32 s8, s8, s2
; GFX6-NEXT: s_xor_b32 s8, s8, s2
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8
-; GFX6-NEXT: s_ashr_i32 s12, s9, 31
-; GFX6-NEXT: s_add_i32 s9, s9, s12
-; GFX6-NEXT: s_xor_b32 s9, s9, s12
+; GFX6-NEXT: s_ashr_i32 s13, s9, 31
+; GFX6-NEXT: s_add_i32 s9, s9, s13
+; GFX6-NEXT: s_xor_b32 s9, s9, s13
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: s_sub_i32 s13, 0, s8
+; GFX6-NEXT: s_sub_i32 s14, 0, s8
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX6-NEXT: s_ashr_i32 s12, s4, 31
-; GFX6-NEXT: v_mul_f32_e32 v0, s14, v0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: s_add_i32 s4, s4, s12
; GFX6-NEXT: s_xor_b32 s4, s4, s12
-; GFX6-NEXT: v_mul_lo_u32 v2, s13, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, s14, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, s14, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: s_sub_i32 s13, 0, s9
+; GFX6-NEXT: s_sub_i32 s14, 0, s9
; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
-; GFX6-NEXT: s_mov_b32 s2, -1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
-; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
-; GFX6-NEXT: v_mul_lo_u32 v2, s13, v1
; GFX6-NEXT: s_ashr_i32 s13, s5, 31
; GFX6-NEXT: s_add_i32 s5, s5, s13
+; GFX6-NEXT: s_xor_b32 s5, s5, s13
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT: v_mul_lo_u32 v2, s14, v1
+; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s8
; GFX6-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s8, v0
-; GFX6-NEXT: s_xor_b32 s4, s5, s13
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; GFX6-NEXT: s_ashr_i32 s5, s10, 31
+; GFX6-NEXT: s_ashr_i32 s4, s10, 31
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
-; GFX6-NEXT: s_add_i32 s8, s10, s5
-; GFX6-NEXT: s_xor_b32 s5, s8, s5
-; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s5
-; GFX6-NEXT: v_mul_hi_u32 v1, s4, v1
+; GFX6-NEXT: s_add_i32 s8, s10, s4
+; GFX6-NEXT: s_xor_b32 s4, s8, s4
+; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s4
+; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, s12, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s9
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0
-; GFX6-NEXT: v_mul_f32_e32 v2, s14, v2
+; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s4, v1
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s9, v1
-; GFX6-NEXT: s_sub_i32 s4, 0, s5
+; GFX6-NEXT: s_sub_i32 s5, 0, s4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
-; GFX6-NEXT: v_mul_lo_u32 v4, s4, v2
+; GFX6-NEXT: v_mul_lo_u32 v4, s5, v2
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s9, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
; GFX6-NEXT: v_mul_hi_u32 v3, v2, v4
; GFX6-NEXT: s_ashr_i32 s8, s11, 31
; GFX6-NEXT: s_add_i32 s9, s11, s8
-; GFX6-NEXT: s_ashr_i32 s4, s6, 31
+; GFX6-NEXT: s_ashr_i32 s5, s6, 31
; GFX6-NEXT: s_xor_b32 s8, s9, s8
-; GFX6-NEXT: s_add_i32 s6, s6, s4
+; GFX6-NEXT: s_add_i32 s6, s6, s5
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s8
-; GFX6-NEXT: s_xor_b32 s6, s6, s4
+; GFX6-NEXT: s_xor_b32 s6, s6, s5
; GFX6-NEXT: v_mul_hi_u32 v2, s6, v2
; GFX6-NEXT: v_xor_b32_e32 v1, s13, v1
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s13, v1
-; GFX6-NEXT: v_mul_lo_u32 v2, v2, s5
-; GFX6-NEXT: v_mul_f32_e32 v3, s14, v3
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, s4
+; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s6, v2
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v2
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s5, v2
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s4, v2
; GFX6-NEXT: s_sub_i32 s6, 0, s8
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s6, v3
; GFX6-NEXT: s_add_i32 s7, s7, s6
; GFX6-NEXT: s_xor_b32 s7, s7, s6
; GFX6-NEXT: v_mul_hi_u32 v4, v3, v4
-; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v2
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s4, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GFX6-NEXT: v_mul_hi_u32 v3, s7, v3
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s5, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s4, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
-; GFX6-NEXT: v_xor_b32_e32 v2, s4, v2
+; GFX6-NEXT: v_xor_b32_e32 v2, s5, v2
; GFX6-NEXT: v_mul_lo_u32 v3, v3, s8
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s4, v2
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s5, v2
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s7, v3
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s8, v3
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
; GFX9-LABEL: srem_v4i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
-; GFX9-NEXT: s_mov_b32 s13, 0x4f7ffffe
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s2, s8, 31
; GFX9-NEXT: s_add_i32 s8, s8, s2
; GFX9-NEXT: s_xor_b32 s2, s8, s2
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX9-NEXT: s_ashr_i32 s3, s9, 31
-; GFX9-NEXT: s_sub_i32 s12, 0, s2
; GFX9-NEXT: s_add_i32 s8, s9, s3
+; GFX9-NEXT: s_sub_i32 s12, 0, s2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_xor_b32 s3, s8, s3
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s3
; GFX9-NEXT: s_ashr_i32 s8, s4, 31
-; GFX9-NEXT: v_mul_f32_e32 v0, s13, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: s_add_i32 s4, s4, s8
; GFX9-NEXT: s_xor_b32 s4, s4, s8
; GFX9-NEXT: v_mul_lo_u32 v2, s12, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, s13, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_sub_i32 s12, 0, s3
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: s_ashr_i32 s9, s5, 31
; GFX9-NEXT: v_mul_lo_u32 v3, s12, v1
-; GFX9-NEXT: s_add_i32 s5, s5, s9
+; GFX9-NEXT: s_ashr_i32 s12, s10, 31
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: s_add_i32 s5, s5, s9
; GFX9-NEXT: s_xor_b32 s5, s5, s9
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s2
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_subrev_u32_e32 v2, s2, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
-; GFX9-NEXT: s_ashr_i32 s2, s10, 31
-; GFX9-NEXT: s_add_i32 s4, s10, s2
-; GFX9-NEXT: s_xor_b32 s2, s4, s2
+; GFX9-NEXT: s_add_i32 s2, s10, s12
+; GFX9-NEXT: s_xor_b32 s2, s2, s12
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s2
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s3
; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
; GFX9-NEXT: v_subrev_u32_e32 v3, s3, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
-; GFX9-NEXT: v_mul_f32_e32 v2, s13, v2
+; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, s3, v1
; GFX9-NEXT: v_add_u32_e32 v2, v2, v3
; GFX9-NEXT: s_xor_b32 s5, s5, s4
; GFX9-NEXT: v_mul_hi_u32 v2, s5, v2
-; GFX9-NEXT: v_mul_f32_e32 v3, s13, v5
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v5
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: s_sub_i32 s6, 0, s3
; GFX9-NEXT: v_mul_lo_u32 v2, v2, s2
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_and_b32 s8, s6, 0xffff
-; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8
-; GFX6-NEXT: s_and_b32 s9, s4, 0xffff
+; GFX6-NEXT: s_and_b32 s9, s6, 0xffff
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX6-NEXT: s_lshr_b32 s6, s6, 16
-; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s6
+; GFX6-NEXT: s_and_b32 s8, s4, 0xffff
+; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s6
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s8
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v0
; GFX6-NEXT: s_lshr_b32 s4, s4, 16
; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s4
-; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v3
-; GFX6-NEXT: v_trunc_f32_e32 v2, v2
-; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v2
+; GFX6-NEXT: v_mul_f32_e32 v3, v1, v3
+; GFX6-NEXT: v_trunc_f32_e32 v3, v3
+; GFX6-NEXT: v_mad_f32 v1, -v3, v0, v1
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
; GFX6-NEXT: v_mul_f32_e32 v1, v4, v5
; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: s_and_b32 s4, s7, 0xffff
-; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GFX6-NEXT: v_mad_f32 v2, -v1, v3, v4
+; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v3
+; GFX6-NEXT: v_mad_f32 v3, -v1, v2, v4
; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s4
; GFX6-NEXT: s_and_b32 s4, s5, 0xffff
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v6, vcc
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s4
; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v4
-; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v1, vcc
; GFX6-NEXT: v_mul_f32_e32 v1, v5, v6
; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v5
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v4
-; GFX6-NEXT: s_mov_b32 s8, 0xffff
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX6-NEXT: v_mul_f32_e32 v3, v6, v7
; GFX6-NEXT: v_trunc_f32_e32 v3, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v3
; GFX6-NEXT: v_mad_f32 v3, -v3, v5, v6
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v5
-; GFX6-NEXT: v_and_b32_e32 v1, s8, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_and_b32_e32 v0, s8, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX9-NEXT: v_mad_f32 v3, -v3, v5, v7
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v5
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
-; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
-; GFX9-NEXT: v_and_b32_e32 v1, v4, v1
-; GFX9-NEXT: v_and_b32_e32 v0, v4, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[0:1]
; GFX6-NEXT: s_and_b32 s8, s6, 0xffff
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX6-NEXT: v_mov_b32_e32 v4, s6
-; GFX6-NEXT: s_mov_b32 s8, 0xffff
; GFX6-NEXT: v_alignbit_b32 v4, s7, v4, 16
-; GFX6-NEXT: s_and_b32 s9, s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v5, s8, v4
-; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: s_and_b32 s8, s4, 0xffff
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v4
+; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s8
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v0
; GFX6-NEXT: v_cvt_f32_u32_e32 v5, v5
-; GFX6-NEXT: v_mov_b32_e32 v3, s4
-; GFX6-NEXT: v_alignbit_b32 v3, s5, v3, 16
-; GFX6-NEXT: v_and_b32_e32 v6, s8, v3
-; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_mov_b32_e32 v1, s4
+; GFX6-NEXT: v_alignbit_b32 v1, s5, v1, 16
+; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v1
+; GFX6-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX6-NEXT: v_cvt_f32_u32_e32 v6, v6
; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v5
+; GFX6-NEXT: v_trunc_f32_e32 v3, v3
+; GFX6-NEXT: v_mad_f32 v2, -v3, v0, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0
+; GFX6-NEXT: v_mul_f32_e32 v2, v6, v7
; GFX6-NEXT: v_trunc_f32_e32 v2, v2
-; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, v6, v7
-; GFX6-NEXT: v_trunc_f32_e32 v1, v1
-; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v1
-; GFX6-NEXT: v_mad_f32 v1, -v1, v5, v6
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GFX6-NEXT: v_mad_f32 v2, -v2, v5, v6
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
-; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v5
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v5
; GFX6-NEXT: s_and_b32 s6, s7, 0xffff
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
-; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s6
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s6
; GFX6-NEXT: s_and_b32 s6, s5, 0xffff
-; GFX6-NEXT: v_mul_lo_u32 v1, v1, v4
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s6
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v3
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GFX6-NEXT: s_lshr_b32 s4, s7, 16
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v1
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v1, v2
; GFX6-NEXT: v_mul_f32_e32 v1, v4, v5
; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s4
; GFX6-NEXT: s_lshr_b32 s6, s5, 16
; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s6
; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v5
-; GFX6-NEXT: v_mad_f32 v4, -v1, v2, v4
+; GFX6-NEXT: v_mad_f32 v4, -v1, v3, v4
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v2
-; GFX6-NEXT: v_mul_f32_e32 v2, v6, v7
-; GFX6-NEXT: v_trunc_f32_e32 v2, v2
-; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v3
+; GFX6-NEXT: v_mul_f32_e32 v3, v6, v7
+; GFX6-NEXT: v_trunc_f32_e32 v3, v3
+; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v3
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT: v_mad_f32 v2, -v2, v5, v6
-; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v5
-; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
+; GFX6-NEXT: v_mad_f32 v3, -v3, v5, v6
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v5
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s7
-; GFX6-NEXT: v_mul_lo_u32 v2, v2, s4
-; GFX6-NEXT: v_and_b32_e32 v0, s8, v0
-; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s6, v2
+; GFX6-NEXT: v_mul_lo_u32 v3, v3, s4
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_and_b32_e32 v1, s8, v1
-; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s6, v3
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_endpgm
; GFX9-NEXT: v_mul_lo_u32 v3, v3, s6
; GFX9-NEXT: v_sub_u32_e32 v4, s4, v1
; GFX9-NEXT: v_sub_u32_e32 v1, s8, v2
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-NEXT: v_sub_u32_e32 v2, s5, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, 0xffff
-; GFX9-NEXT: v_and_b32_e32 v1, v3, v1
-; GFX9-NEXT: v_and_b32_e32 v0, v3, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_lshl_or_b32 v0, v4, 16, v0
; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[0:1]
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v2|
; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_endpgm
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, |v0|
; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cselect_b32 s0, s4, 0
-; GFX9-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX9-NEXT: v_add_u32_e32 v0, s0, v6
-; GFX9-NEXT: v_and_b32_e32 v1, v5, v1
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-NEXT: v_lshl_or_b32 v1, v0, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v0, v5, v3
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GFX9-NEXT: v_lshl_or_b32 v0, v4, 16, v0
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm
; GFX6-NEXT: s_lshr_b32 s4, s5, 16
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s5, v2
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v3
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_endpgm
; GFX9-NEXT: v_mul_lo_u32 v4, v4, s7
; GFX9-NEXT: v_sub_u32_e32 v5, s9, v1
; GFX9-NEXT: v_sub_u32_e32 v1, s6, v3
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-NEXT: v_sub_u32_e32 v3, s5, v4
-; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
-; GFX9-NEXT: v_and_b32_e32 v1, v4, v1
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v3, v4, v5
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v5
; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v3
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX6-NEXT: s_mov_b32 s8, 0xffff
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_and_b32 s9, s6, 0xffff
-; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s9
+; GFX6-NEXT: s_and_b32 s8, s6, 0xffff
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s8
; GFX6-NEXT: s_and_b32 s2, s4, 0xffff
; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s2
; GFX6-NEXT: v_mov_b32_e32 v2, s6
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v1
; GFX6-NEXT: v_alignbit_b32 v2, s7, v2, 16
-; GFX6-NEXT: v_and_b32_e32 v5, s8, v2
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v2
; GFX6-NEXT: v_cvt_f32_u32_e32 v5, v5
; GFX6-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX6-NEXT: v_trunc_f32_e32 v4, v4
; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v4
-; GFX6-NEXT: v_mad_f32 v3, -v4, v0, v3
-; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v0
-; GFX6-NEXT: v_mov_b32_e32 v1, s4
-; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v6, vcc
-; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
-; GFX6-NEXT: v_alignbit_b32 v1, s5, v1, 16
-; GFX6-NEXT: v_and_b32_e32 v3, s8, v1
+; GFX6-NEXT: v_mad_f32 v3, -v4, v1, v3
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v1
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v6, vcc
+; GFX6-NEXT: v_alignbit_b32 v0, s5, v0, 16
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s6
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v0
; GFX6-NEXT: v_cvt_f32_u32_e32 v3, v3
; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v5
-; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s4, v1
; GFX6-NEXT: s_and_b32 s4, s7, 0xffff
; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s4
; GFX6-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v3, v3, s7
-; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s5, v3
-; GFX6-NEXT: v_and_b32_e32 v0, s8, v0
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
; GFX6-NEXT: buffer_store_short v2, off, s[0:3], 0 offset:4
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_and_b32 s8, s2, 0x7fff
-; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s8
-; GFX6-NEXT: s_and_b32 s9, s0, 0x7fff
-; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NEXT: v_alignbit_b32 v0, s3, v0, 30
+; GFX6-NEXT: s_and_b32 s8, s0, 0x7fff
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s8
+; GFX6-NEXT: s_and_b32 s3, s2, 0x7fff
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: s_bfe_u32 s0, s0, 0xf000f
-; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s0
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s3
; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v1
-; GFX6-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s0
; GFX6-NEXT: s_bfe_u32 s2, s2, 0xf000f
-; GFX6-NEXT: v_alignbit_b32 v0, s3, v0, 30
-; GFX6-NEXT: s_movk_i32 s3, 0x7fff
; GFX6-NEXT: v_alignbit_b32 v2, s1, v2, 30
; GFX6-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s2
; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v5
-; GFX6-NEXT: v_and_b32_e32 v2, s3, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; GFX6-NEXT: v_trunc_f32_e32 v4, v4
; GFX6-NEXT: v_mad_f32 v3, -v4, v1, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX6-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v1
; GFX6-NEXT: v_mul_f32_e32 v1, v6, v7
-; GFX6-NEXT: v_and_b32_e32 v0, s3, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
; GFX6-NEXT: v_mad_f32 v4, -v1, v5, v6
; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v1
; GFX6-NEXT: v_mad_f32 v0, -v1, v2, v0
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s3, v3
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fff, v3
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v5, vcc
-; GFX6-NEXT: v_and_b32_e32 v3, s3, v4
+; GFX6-NEXT: v_and_b32_e32 v3, 0x7fff, v4
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 30
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 15, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
-; GFX9-NEXT: s_movk_i32 s6, 0x7fff
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_alignbit_b32 v0, s3, v0, 30
-; GFX9-NEXT: s_and_b32 s3, s2, 0x7fff
-; GFX9-NEXT: s_and_b32 s7, s0, 0x7fff
-; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7
+; GFX9-NEXT: s_and_b32 s6, s2, 0x7fff
+; GFX9-NEXT: s_and_b32 s3, s0, 0x7fff
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s3
; GFX9-NEXT: v_mov_b32_e32 v3, s0
; GFX9-NEXT: s_bfe_u32 s0, s0, 0xf000f
-; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s6
; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v1
; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s0
; GFX9-NEXT: s_bfe_u32 s2, s2, 0xf000f
; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v6
-; GFX9-NEXT: v_and_b32_e32 v3, s6, v3
+; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v3
; GFX9-NEXT: v_trunc_f32_e32 v5, v5
; GFX9-NEXT: v_mad_f32 v4, -v5, v1, v4
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v3
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v1
; GFX9-NEXT: v_mul_f32_e32 v1, v7, v8
-; GFX9-NEXT: v_and_b32_e32 v0, s6, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
; GFX9-NEXT: v_mad_f32 v5, -v1, v6, v7
; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v1
; GFX9-NEXT: v_mad_f32 v0, -v1, v3, v0
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v3
-; GFX9-NEXT: v_and_b32_e32 v3, s6, v4
+; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v6, vcc
-; GFX9-NEXT: v_and_b32_e32 v4, s6, v5
+; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v5
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_and_b32 s9, s2, 0x7fff
-; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s9
-; GFX6-NEXT: s_and_b32 s10, s0, 0x7fff
-; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s10
+; GFX6-NEXT: s_and_b32 s8, s2, 0x7fff
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s8
+; GFX6-NEXT: s_and_b32 s9, s0, 0x7fff
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: v_alignbit_b32 v2, s1, v2, 30
; GFX6-NEXT: s_bfe_u32 s1, s0, 0xf000f
; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v1
; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s1
-; GFX6-NEXT: s_bfe_u32 s10, s2, 0xf000f
-; GFX6-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NEXT: s_bfe_u32 s9, s2, 0xf000f
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; GFX6-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX6-NEXT: v_trunc_f32_e32 v4, v4
; GFX6-NEXT: v_mad_f32 v3, -v4, v1, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v1
-; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s10
-; GFX6-NEXT: v_alignbit_b32 v0, s3, v0, 30
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s9
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v5
-; GFX6-NEXT: s_movk_i32 s3, 0x7fff
-; GFX6-NEXT: v_and_b32_e32 v2, s3, v2
+; GFX6-NEXT: v_alignbit_b32 v0, s3, v0, 30
+; GFX6-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s2, v1
; GFX6-NEXT: v_mul_f32_e32 v1, v3, v4
; GFX6-NEXT: v_cvt_f32_u32_e32 v4, v2
-; GFX6-NEXT: v_and_b32_e32 v0, s3, v0
; GFX6-NEXT: v_cvt_f32_u32_e32 v7, v0
; GFX6-NEXT: v_trunc_f32_e32 v1, v1
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v8, v4
; GFX6-NEXT: v_mad_f32 v3, -v1, v5, v3
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v8, v4
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v5
+; GFX6-NEXT: s_lshr_b32 s0, s0, 15
; GFX6-NEXT: v_mul_f32_e32 v3, v7, v8
; GFX6-NEXT: v_trunc_f32_e32 v3, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v3
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX6-NEXT: v_mad_f32 v3, -v3, v4, v7
-; GFX6-NEXT: s_lshr_b32 s0, s0, 15
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v4
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s0
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v3, v2
-; GFX6-NEXT: s_lshr_b32 s8, s2, 15
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s8, v1
+; GFX6-NEXT: s_lshr_b32 s3, s2, 15
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s3, v1
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v3, s3, v3
+; GFX6-NEXT: v_and_b32_e32 v3, 0x7fff, v3
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 30
-; GFX6-NEXT: v_and_b32_e32 v2, s3, v6
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fff, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 15, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
-; GFX9-NEXT: s_movk_i32 s6, 0x7fff
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_and_b32 s6, s2, 0x7fff
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s6
; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_alignbit_b32 v0, s3, v0, 30
-; GFX9-NEXT: s_and_b32 s3, s2, 0x7fff
-; GFX9-NEXT: s_and_b32 s8, s0, 0x7fff
-; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s8
-; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s3
-; GFX9-NEXT: s_bfe_u32 s3, s0, 0xf000f
-; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s3
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v1
+; GFX9-NEXT: s_and_b32 s7, s0, 0x7fff
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7
+; GFX9-NEXT: s_bfe_u32 s6, s0, 0xf000f
+; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s6
; GFX9-NEXT: v_mov_b32_e32 v3, s0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v1
; GFX9-NEXT: v_alignbit_b32 v3, s1, v3, 30
-; GFX9-NEXT: s_bfe_u32 s7, s2, 0xf000f
+; GFX9-NEXT: v_alignbit_b32 v0, s3, v0, 30
+; GFX9-NEXT: s_bfe_u32 s3, s2, 0xf000f
; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX9-NEXT: v_trunc_f32_e32 v5, v5
; GFX9-NEXT: v_mad_f32 v4, -v5, v1, v4
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
-; GFX9-NEXT: v_and_b32_e32 v3, s6, v3
+; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v3
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v1
-; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s7
+; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v6
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v5, vcc
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3
-; GFX9-NEXT: v_and_b32_e32 v0, s6, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX9-NEXT: v_mul_f32_e32 v4, v7, v8
; GFX9-NEXT: v_cvt_f32_u32_e32 v8, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v9, v5
; GFX9-NEXT: v_sub_u32_e32 v4, s0, v4
; GFX9-NEXT: v_sub_u32_e32 v5, s2, v1
; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3
-; GFX9-NEXT: v_and_b32_e32 v4, s6, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v4
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
-; GFX9-NEXT: v_and_b32_e32 v3, s6, v5
+; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v5
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
; GFX6-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, |v4|
; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX6-NEXT: s_movk_i32 s0, 0x7fff
+; GFX6-NEXT: v_and_b32_e32 v3, 0x7fff, v3
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v3, s0, v3
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 30
-; GFX6-NEXT: v_and_b32_e32 v2, s0, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 15, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
; GFX9-NEXT: v_mad_f32 v1, -v1, v3, v6
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v3|
; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX9-NEXT: s_movk_i32 s0, 0x7fff
; GFX9-NEXT: v_add_u32_e32 v0, v7, v0
-; GFX9-NEXT: v_and_b32_e32 v3, s0, v4
-; GFX9-NEXT: v_and_b32_e32 v4, s0, v5
+; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v5
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_bfe_i32 s10, s2, 0xf0000
-; GFX6-NEXT: v_cvt_f32_i32_e32 v5, s10
+; GFX6-NEXT: s_bfe_i32 s9, s2, 0xf0000
+; GFX6-NEXT: v_cvt_f32_i32_e32 v5, s9
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: v_alignbit_b32 v2, s1, v2, 30
; GFX6-NEXT: s_bfe_i32 s1, s0, 0xf0000
; GFX6-NEXT: v_cvt_f32_i32_e32 v4, s1
-; GFX6-NEXT: s_xor_b32 s1, s10, s1
+; GFX6-NEXT: s_xor_b32 s1, s9, s1
; GFX6-NEXT: s_ashr_i32 s1, s1, 30
; GFX6-NEXT: s_or_b32 s1, s1, 1
; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v4
; GFX6-NEXT: v_mov_b32_e32 v7, s1
-; GFX6-NEXT: s_lshr_b32 s9, s0, 15
+; GFX6-NEXT: s_lshr_b32 s8, s0, 15
; GFX6-NEXT: s_bfe_i32 s1, s2, 0xf000f
; GFX6-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX6-NEXT: v_trunc_f32_e32 v6, v6
; GFX6-NEXT: v_cvt_i32_f32_e32 v6, v6
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, |v4|
; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v7, vcc
-; GFX6-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NEXT: v_and_b32_e32 v3, 0x7fff, v2
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_mul_lo_u32 v4, v4, s0
; GFX6-NEXT: s_bfe_i32 s0, s0, 0xf000f
; GFX6-NEXT: v_cvt_f32_i32_e32 v5, s0
; GFX6-NEXT: v_cvt_f32_i32_e32 v6, s1
-; GFX6-NEXT: v_alignbit_b32 v0, s3, v0, 30
-; GFX6-NEXT: s_movk_i32 s3, 0x7fff
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v5
-; GFX6-NEXT: v_and_b32_e32 v3, s3, v2
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s2, v4
-; GFX6-NEXT: v_mul_f32_e32 v7, v6, v7
-; GFX6-NEXT: v_trunc_f32_e32 v7, v7
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v5
; GFX6-NEXT: s_xor_b32 s0, s1, s0
-; GFX6-NEXT: v_mad_f32 v6, -v7, v5, v6
; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 15
; GFX6-NEXT: s_ashr_i32 s0, s0, 30
+; GFX6-NEXT: v_mul_f32_e32 v7, v6, v7
+; GFX6-NEXT: v_trunc_f32_e32 v7, v7
+; GFX6-NEXT: v_mad_f32 v6, -v7, v5, v6
; GFX6-NEXT: v_cvt_i32_f32_e32 v7, v7
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v6|, |v5|
; GFX6-NEXT: v_cvt_f32_i32_e32 v6, v2
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: s_or_b32 s0, s0, 1
+; GFX6-NEXT: v_alignbit_b32 v0, s3, v0, 30
; GFX6-NEXT: v_mov_b32_e32 v8, s0
-; GFX6-NEXT: v_and_b32_e32 v1, s3, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 15
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v7|, |v6|
; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX6-NEXT: v_mul_lo_u32 v5, v5, s9
+; GFX6-NEXT: v_mul_lo_u32 v5, v5, s8
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_mul_lo_u32 v0, v0, v3
-; GFX6-NEXT: s_lshr_b32 s8, s2, 15
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s8, v5
+; GFX6-NEXT: s_lshr_b32 s3, s2, 15
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s3, v5
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v2, s3, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 30
-; GFX6-NEXT: v_and_b32_e32 v3, s3, v4
+; GFX6-NEXT: v_and_b32_e32 v3, 0x7fff, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 15, v2
; GFX6-NEXT: v_or_b32_e32 v2, v3, v2
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
-; GFX9-NEXT: s_movk_i32 s8, 0x7fff
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
+; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x34
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_bfe_i32 s6, s2, 0xf0000
-; GFX9-NEXT: v_cvt_f32_i32_e32 v5, s6
+; GFX9-NEXT: s_bfe_i32 s1, s2, 0xf0000
+; GFX9-NEXT: v_cvt_f32_i32_e32 v5, s1
+; GFX9-NEXT: s_bfe_i32 s0, s6, 0xf0000
+; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s0
+; GFX9-NEXT: s_xor_b32 s0, s1, s0
; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s0
-; GFX9-NEXT: v_alignbit_b32 v1, s1, v1, 30
-; GFX9-NEXT: s_bfe_i32 s1, s0, 0xf0000
-; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s1
-; GFX9-NEXT: s_xor_b32 s1, s6, s1
-; GFX9-NEXT: s_ashr_i32 s1, s1, 30
-; GFX9-NEXT: v_alignbit_b32 v0, s3, v0, 30
+; GFX9-NEXT: v_mov_b32_e32 v1, s6
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v4
-; GFX9-NEXT: s_lshr_b32 s3, s2, 15
-; GFX9-NEXT: s_lshr_b32 s9, s0, 15
-; GFX9-NEXT: s_or_b32 s1, s1, 1
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: s_lshr_b32 s8, s2, 15
+; GFX9-NEXT: v_alignbit_b32 v0, s3, v0, 30
; GFX9-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX9-NEXT: v_trunc_f32_e32 v6, v6
; GFX9-NEXT: v_mad_f32 v5, -v6, v4, v5
; GFX9-NEXT: v_cvt_i32_f32_e32 v6, v6
-; GFX9-NEXT: v_cmp_ge_f32_e64 s[6:7], |v5|, |v4|
-; GFX9-NEXT: s_and_b64 s[6:7], s[6:7], exec
-; GFX9-NEXT: s_cselect_b32 s1, s1, 0
-; GFX9-NEXT: v_add_u32_e32 v4, s1, v6
-; GFX9-NEXT: s_bfe_i32 s1, s0, 0xf000f
-; GFX9-NEXT: v_cvt_f32_i32_e32 v5, s1
-; GFX9-NEXT: v_mul_lo_u32 v4, v4, s0
-; GFX9-NEXT: s_bfe_i32 s0, s2, 0xf000f
-; GFX9-NEXT: v_cvt_f32_i32_e32 v6, s0
+; GFX9-NEXT: v_alignbit_b32 v1, s7, v1, 30
+; GFX9-NEXT: s_lshr_b32 s3, s6, 15
+; GFX9-NEXT: s_or_b32 s7, s0, 1
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, |v4|
+; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX9-NEXT: s_cselect_b32 s0, s7, 0
+; GFX9-NEXT: v_add_u32_e32 v4, s0, v6
+; GFX9-NEXT: s_bfe_i32 s0, s6, 0xf000f
+; GFX9-NEXT: v_cvt_f32_i32_e32 v5, s0
+; GFX9-NEXT: s_bfe_i32 s1, s2, 0xf000f
+; GFX9-NEXT: v_cvt_f32_i32_e32 v6, s1
+; GFX9-NEXT: s_xor_b32 s0, s1, s0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v5
-; GFX9-NEXT: s_xor_b32 s0, s0, s1
-; GFX9-NEXT: v_and_b32_e32 v3, s8, v1
+; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v1
; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 15
; GFX9-NEXT: v_mul_f32_e32 v7, v6, v7
; GFX9-NEXT: v_trunc_f32_e32 v7, v7
; GFX9-NEXT: v_mad_f32 v6, -v7, v5, v6
; GFX9-NEXT: v_cvt_i32_f32_e32 v7, v7
-; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 15
+; GFX9-NEXT: v_mul_lo_u32 v4, v4, s6
; GFX9-NEXT: s_or_b32 s6, s0, 1
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v6|, |v5|
; GFX9-NEXT: v_cvt_f32_i32_e32 v6, v1
; GFX9-NEXT: v_mad_f32 v7, -v7, v6, v8
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v7|, |v6|
; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX9-NEXT: v_mul_lo_u32 v5, v5, s9
+; GFX9-NEXT: v_mul_lo_u32 v5, v5, s3
; GFX9-NEXT: v_add_u32_e32 v1, v9, v1
; GFX9-NEXT: v_mul_lo_u32 v1, v1, v3
-; GFX9-NEXT: v_and_b32_e32 v0, s8, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX9-NEXT: v_sub_u32_e32 v3, s2, v4
-; GFX9-NEXT: v_sub_u32_e32 v4, s3, v5
+; GFX9-NEXT: v_sub_u32_e32 v4, s8, v5
; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1
-; GFX9-NEXT: v_and_b32_e32 v4, s8, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v4
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
-; GFX9-NEXT: v_and_b32_e32 v3, s8, v3
+; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v3
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
-; GFX6-NEXT: s_mov_b32 s0, 0x4f7ffffe
; GFX6-NEXT: s_mov_b32 s11, 0xf000
; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX6-NEXT: s_lshl_b32 s3, 0x1000, s7
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s3
+; GFX6-NEXT: s_sub_i32 s0, 0, s2
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX6-NEXT: v_mul_f32_e32 v0, s0, v0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, s0, v1
-; GFX6-NEXT: s_sub_i32 s0, 0, s2
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_mul_lo_u32 v2, s0, v0
; GFX6-NEXT: s_sub_i32 s0, 0, s3
; GFX9-LABEL: udiv_v2i32_pow2_shl_denom:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
-; GFX9-NEXT: s_mov_b32 s2, 0x4f7ffffe
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s6, 0x1000, s6
; GFX9-NEXT: s_lshl_b32 s7, 0x1000, s7
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7
+; GFX9-NEXT: s_sub_i32 s2, 0, s6
; GFX9-NEXT: s_sub_i32 s3, 0, s7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX9-NEXT: v_mul_f32_e32 v0, s2, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, s2, v1
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: s_sub_i32 s2, 0, s6
; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: v_subrev_u32_e32 v6, s7, v4
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, v6, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
-; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm
; GFX6-LABEL: urem_v2i32_pow2_shl_denom:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
-; GFX6-NEXT: s_mov_b32 s2, 0x4f7ffffe
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX6-NEXT: s_lshl_b32 s7, 0x1000, s7
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s7
+; GFX6-NEXT: s_sub_i32 s2, 0, s6
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX6-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, s2, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: s_sub_i32 s2, 0, s6
; GFX6-NEXT: v_mul_lo_u32 v2, s2, v0
; GFX6-NEXT: s_sub_i32 s2, 0, s7
; GFX6-NEXT: v_mul_lo_u32 v3, s2, v1
; GFX9-NEXT: s_lshl_b32 s2, 0x1000, s7
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s2
-; GFX9-NEXT: s_mov_b32 s6, 0x4f7ffffe
+; GFX9-NEXT: s_sub_i32 s6, 0, s3
; GFX9-NEXT: s_sub_i32 s7, 0, s2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
-; GFX9-NEXT: v_mul_f32_e32 v0, s6, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, s6, v1
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: s_sub_i32 s6, 0, s3
; GFX9-NEXT: v_mul_lo_u32 v2, s6, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s7, v1
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT: s_mov_b32 s13, 0x4f7ffffe
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_xor_b32 s2, s0, s1
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX6-NEXT: s_lshl_b32 s0, 0x1000, s11
-; GFX6-NEXT: s_sub_i32 s11, 0, s2
-; GFX6-NEXT: s_ashr_i32 s10, s0, 31
+; GFX6-NEXT: s_ashr_i32 s3, s0, 31
+; GFX6-NEXT: s_add_i32 s0, s0, s3
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: s_add_i32 s0, s0, s10
-; GFX6-NEXT: s_ashr_i32 s3, s8, 31
-; GFX6-NEXT: s_add_i32 s8, s8, s3
-; GFX6-NEXT: v_mul_f32_e32 v0, s13, v0
+; GFX6-NEXT: s_sub_i32 s11, 0, s2
+; GFX6-NEXT: s_xor_b32 s10, s0, s3
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s10
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: s_xor_b32 s12, s3, s1
-; GFX6-NEXT: v_mul_lo_u32 v1, s11, v0
-; GFX6-NEXT: s_xor_b32 s11, s0, s10
-; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s11
-; GFX6-NEXT: s_xor_b32 s0, s8, s3
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT: s_sub_i32 s3, 0, s11
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, s13, v2
+; GFX6-NEXT: s_ashr_i32 s0, s8, 31
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX6-NEXT: s_add_i32 s8, s8, s0
+; GFX6-NEXT: v_mul_lo_u32 v2, s11, v0
+; GFX6-NEXT: s_xor_b32 s8, s8, s0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s0, v2
-; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v2
-; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s2, v2
-; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GFX6-NEXT: v_mul_lo_u32 v3, s3, v1
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: s_xor_b32 s11, s0, s1
+; GFX6-NEXT: s_sub_i32 s0, 0, s10
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s8, v0
+; GFX6-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX6-NEXT: v_mul_lo_u32 v3, v0, s2
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0
+; GFX6-NEXT: v_mul_hi_u32 v2, v1, v2
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s8, v3
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s2, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
; GFX6-NEXT: s_ashr_i32 s0, s9, 31
; GFX6-NEXT: s_add_i32 s1, s9, s0
; GFX6-NEXT: s_xor_b32 s1, s1, s0
-; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v3
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, s10
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX6-NEXT: s_xor_b32 s2, s0, s10
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, s11
+; GFX6-NEXT: s_xor_b32 s2, s0, s3
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1
-; GFX6-NEXT: v_xor_b32_e32 v0, s12, v0
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s1, v2
-; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v2
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v2
+; GFX6-NEXT: v_xor_b32_e32 v0, s11, v0
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s11, v2
-; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s10, v2
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s11, v0
; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s11, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_xor_b32_e32 v1, s2, v1
; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s2, v1
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX9-NEXT: s_mov_b32 s11, 0x4f7ffffe
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s0, 0x1000, s6
; GFX9-NEXT: s_xor_b32 s0, s0, s1
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s0
; GFX9-NEXT: s_lshl_b32 s6, 0x1000, s7
-; GFX9-NEXT: s_ashr_i32 s9, s6, 31
-; GFX9-NEXT: s_add_i32 s6, s6, s9
+; GFX9-NEXT: s_ashr_i32 s8, s6, 31
+; GFX9-NEXT: s_add_i32 s6, s6, s8
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_xor_b32 s6, s6, s9
+; GFX9-NEXT: s_xor_b32 s6, s6, s8
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s6
; GFX9-NEXT: s_sub_i32 s10, 0, s0
-; GFX9-NEXT: v_mul_f32_e32 v0, s11, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: s_ashr_i32 s7, s4, 31
; GFX9-NEXT: s_add_i32 s4, s4, s7
; GFX9-NEXT: v_mul_lo_u32 v3, s10, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, s11, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: s_xor_b32 s4, s4, s7
-; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3
; GFX9-NEXT: s_sub_i32 s10, 0, s6
-; GFX9-NEXT: s_ashr_i32 s8, s5, 31
-; GFX9-NEXT: s_add_i32 s5, s5, s8
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3
+; GFX9-NEXT: s_xor_b32 s4, s4, s7
+; GFX9-NEXT: v_mul_lo_u32 v4, s10, v1
+; GFX9-NEXT: s_ashr_i32 s9, s5, 31
; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
-; GFX9-NEXT: v_mul_lo_u32 v3, s10, v1
-; GFX9-NEXT: s_xor_b32 s5, s5, s8
-; GFX9-NEXT: s_xor_b32 s1, s7, s1
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v4
+; GFX9-NEXT: s_add_i32 s5, s5, s9
+; GFX9-NEXT: s_xor_b32 s5, s5, s9
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s0
-; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
-; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
-; GFX9-NEXT: v_sub_u32_e32 v4, s4, v4
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v4
; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v5, s0, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_sub_u32_e32 v4, s4, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v4
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, s0, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v3
; GFX9-NEXT: v_mul_lo_u32 v3, v1, s6
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
-; GFX9-NEXT: s_xor_b32 s0, s8, s9
-; GFX9-NEXT: v_xor_b32_e32 v0, s1, v0
; GFX9-NEXT: v_sub_u32_e32 v3, s5, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
+; GFX9-NEXT: s_xor_b32 s1, s7, s1
+; GFX9-NEXT: s_xor_b32 s0, s9, s8
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s1, v0
; GFX9-NEXT: v_xor_b32_e32 v1, s0, v1
; GFX9-NEXT: v_subrev_u32_e32 v0, s1, v0
; GFX9-NEXT: v_subrev_u32_e32 v1, s0, v1
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX6-NEXT: s_mov_b32 s9, 0x4f7ffffe
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b32 s2, 0x1000, s6
; GFX6-NEXT: s_ashr_i32 s3, s2, 31
; GFX6-NEXT: s_add_i32 s2, s2, s3
; GFX6-NEXT: s_xor_b32 s6, s2, s3
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GFX6-NEXT: s_lshl_b32 s2, 0x1000, s7
-; GFX6-NEXT: s_ashr_i32 s7, s2, 31
-; GFX6-NEXT: s_add_i32 s2, s2, s7
+; GFX6-NEXT: s_lshl_b32 s7, 0x1000, s7
+; GFX6-NEXT: s_ashr_i32 s8, s7, 31
+; GFX6-NEXT: s_add_i32 s7, s7, s8
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: s_xor_b32 s7, s2, s7
+; GFX6-NEXT: s_xor_b32 s7, s7, s8
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s7
-; GFX6-NEXT: s_sub_i32 s2, 0, s6
-; GFX6-NEXT: v_mul_f32_e32 v0, s9, v0
+; GFX6-NEXT: s_sub_i32 s9, 0, s6
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: s_ashr_i32 s8, s4, 31
-; GFX6-NEXT: s_mov_b32 s3, 0xf000
-; GFX6-NEXT: v_mul_lo_u32 v2, s2, v0
-; GFX6-NEXT: s_add_i32 s2, s4, s8
-; GFX6-NEXT: v_mul_f32_e32 v1, s9, v1
-; GFX6-NEXT: s_xor_b32 s4, s2, s8
-; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: s_add_i32 s4, s4, s8
+; GFX6-NEXT: v_mul_lo_u32 v2, s9, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX6-NEXT: s_xor_b32 s4, s4, s8
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: s_sub_i32 s2, 0, s7
-; GFX6-NEXT: s_ashr_i32 s9, s5, 31
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: s_sub_i32 s9, 0, s7
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
-; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1
-; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_mul_lo_u32 v2, s9, v1
+; GFX6-NEXT: s_ashr_i32 s9, s5, 31
+; GFX6-NEXT: s_add_i32 s5, s5, s9
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
; GFX6-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s6, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
-; GFX6-NEXT: s_add_i32 s4, s5, s9
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT: s_xor_b32 s4, s4, s9
+; GFX6-NEXT: s_xor_b32 s4, s5, s9
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s6, v0
; GFX9-LABEL: srem_v2i32_pow2_shl_denom:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
-; GFX9-NEXT: s_mov_b32 s9, 0x4f7ffffe
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s3, 0x1000, s6
; GFX9-NEXT: s_ashr_i32 s6, s3, 31
; GFX9-NEXT: s_sub_i32 s8, 0, s3
; GFX9-NEXT: s_ashr_i32 s6, s4, 31
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX9-NEXT: v_mul_f32_e32 v0, s9, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_add_i32 s4, s4, s6
-; GFX9-NEXT: v_mul_f32_e32 v1, s9, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mul_lo_u32 v2, s8, v0
; GFX9-NEXT: s_sub_i32 s8, 0, s2
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s2
; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
; GFX9-NEXT: v_xor_b32_e32 v1, s7, v1
; GFX9-NEXT: v_subrev_u32_e32 v0, s6, v0
; GFX9-NEXT: v_subrev_u32_e32 v1, s7, v1
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
; GFX6-NEXT: s_mov_b64 s[12:13], 0x1000
-; GFX6-NEXT: s_mov_b32 s18, 0x4f800000
-; GFX6-NEXT: s_mov_b32 s19, 0x5f7ffffc
-; GFX6-NEXT: s_mov_b32 s20, 0x2f800000
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b64 s[8:9], s[12:13], s8
; GFX6-NEXT: s_lshl_b64 s[2:3], s[12:13], s10
; GFX6-NEXT: s_xor_b64 s[12:13], s[8:9], s[14:15]
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s13
-; GFX6-NEXT: s_mov_b32 s21, 0xcf800000
; GFX6-NEXT: s_sub_u32 s10, 0, s12
; GFX6-NEXT: s_subb_u32 s11, 0, s13
-; GFX6-NEXT: v_mac_f32_e32 v0, s18, v1
-; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_ashr_i32 s16, s5, 31
+; GFX6-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
; GFX6-NEXT: s_add_u32 s0, s4, s16
-; GFX6-NEXT: v_mul_f32_e32 v0, s19, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, s20, v0
+; GFX6-NEXT: s_mov_b32 s17, s16
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX6-NEXT: v_trunc_f32_e32 v1, v1
-; GFX6-NEXT: v_mac_f32_e32 v0, s21, v1
+; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: s_mov_b32 s17, s16
; GFX6-NEXT: s_addc_u32 s1, s5, s16
+; GFX6-NEXT: s_xor_b64 s[4:5], s[0:1], s[16:17]
; GFX6-NEXT: v_mul_lo_u32 v2, s10, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s10, v0
-; GFX6-NEXT: v_mul_lo_u32 v4, s11, v0
-; GFX6-NEXT: v_mul_lo_u32 v5, s10, v0
-; GFX6-NEXT: s_xor_b64 s[4:5], s[0:1], s[16:17]
+; GFX6-NEXT: v_mul_lo_u32 v5, s11, v0
+; GFX6-NEXT: v_mul_lo_u32 v4, s10, v0
+; GFX6-NEXT: s_xor_b64 s[14:15], s[16:17], s[14:15]
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; GFX6-NEXT: v_mul_lo_u32 v3, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v4, v0, v5
-; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GFX6-NEXT: v_mul_hi_u32 v3, v0, v4
+; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v7, v0, v2
+; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
+; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
-; GFX6-NEXT: v_mul_lo_u32 v6, v1, v5
-; GFX6-NEXT: v_mul_hi_u32 v5, v1, v5
-; GFX6-NEXT: s_xor_b64 s[14:15], s[16:17], s[14:15]
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s13, v2
-; GFX6-NEXT: v_mac_f32_e32 v8, s18, v9
+; GFX6-NEXT: v_mac_f32_e32 v8, 0x4f800000, v9
; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
; GFX6-NEXT: v_rcp_f32_e32 v3, v8
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1]
-; GFX6-NEXT: v_mul_f32_e32 v3, s19, v3
-; GFX6-NEXT: v_mul_f32_e32 v4, s20, v3
+; GFX6-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3
+; GFX6-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
; GFX6-NEXT: v_trunc_f32_e32 v4, v4
-; GFX6-NEXT: v_mac_f32_e32 v3, s21, v4
+; GFX6-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX6-NEXT: s_sub_u32 s0, 0, s2
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX9-NEXT: s_mov_b64 s[2:3], 0x1000
-; GFX9-NEXT: s_mov_b32 s16, 0x4f800000
-; GFX9-NEXT: s_mov_b32 s17, 0x5f7ffffc
-; GFX9-NEXT: s_mov_b32 s18, 0x2f800000
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b64 s[10:11], s[2:3], s10
; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s8
; GFX9-NEXT: s_xor_b64 s[8:9], s[2:3], s[12:13]
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9
-; GFX9-NEXT: s_mov_b32 s19, 0xcf800000
; GFX9-NEXT: s_sub_u32 s2, 0, s8
; GFX9-NEXT: s_subb_u32 s3, 0, s9
-; GFX9-NEXT: v_mac_f32_e32 v0, s16, v1
-; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_ashr_i32 s14, s5, 31
+; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_mov_b32 s15, s14
-; GFX9-NEXT: v_mul_f32_e32 v0, s17, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, s18, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1
-; GFX9-NEXT: v_mac_f32_e32 v0, s19, v1
+; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_lo_u32 v2, s2, v1
; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4
; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2
-; GFX9-NEXT: v_mul_hi_u32 v6, v0, v2
-; GFX9-NEXT: v_mul_hi_u32 v7, v1, v2
-; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v6, v1, v4
+; GFX9-NEXT: v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
-; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
-; GFX9-NEXT: v_mul_lo_u32 v6, v1, v4
-; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
-; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v7, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v6, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v8, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v4
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3
-; GFX9-NEXT: v_mac_f32_e32 v9, s16, v10
+; GFX9-NEXT: v_mac_f32_e32 v9, 0x4f800000, v10
; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v4, vcc
; GFX9-NEXT: v_rcp_f32_e32 v4, v9
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v3, v8, v6, s[0:1]
-; GFX9-NEXT: v_mul_f32_e32 v4, s17, v4
-; GFX9-NEXT: v_mul_f32_e32 v5, s18, v4
+; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
+; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
; GFX9-NEXT: v_trunc_f32_e32 v5, v5
-; GFX9-NEXT: v_mac_f32_e32 v4, s19, v5
+; GFX9-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX9-NEXT: s_sub_u32 s0, 0, s10
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
; GFX6-NEXT: s_mov_b64 s[2:3], 0x1000
-; GFX6-NEXT: s_mov_b32 s18, 0x4f800000
-; GFX6-NEXT: s_mov_b32 s19, 0x5f7ffffc
-; GFX6-NEXT: s_mov_b32 s20, 0x2f800000
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s11, 0xf000
; GFX6-NEXT: s_lshl_b64 s[14:15], s[2:3], s10
; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s8
; GFX6-NEXT: s_ashr_i32 s8, s3, 31
; GFX6-NEXT: s_xor_b64 s[16:17], s[2:3], s[8:9]
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s16
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s17
-; GFX6-NEXT: s_mov_b32 s21, 0xcf800000
; GFX6-NEXT: s_sub_u32 s2, 0, s16
; GFX6-NEXT: s_subb_u32 s3, 0, s17
-; GFX6-NEXT: v_mac_f32_e32 v0, s18, v1
-; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_ashr_i32 s12, s5, 31
+; GFX6-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
; GFX6-NEXT: s_add_u32 s0, s4, s12
-; GFX6-NEXT: v_mul_f32_e32 v0, s19, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, s20, v0
+; GFX6-NEXT: s_mov_b32 s13, s12
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX6-NEXT: v_trunc_f32_e32 v1, v1
-; GFX6-NEXT: v_mac_f32_e32 v0, s21, v1
+; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: s_mov_b32 s13, s12
; GFX6-NEXT: s_addc_u32 s1, s5, s12
+; GFX6-NEXT: s_xor_b64 s[4:5], s[0:1], s[12:13]
; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0
-; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0
-; GFX6-NEXT: v_mul_lo_u32 v5, s2, v0
-; GFX6-NEXT: s_xor_b64 s[4:5], s[0:1], s[12:13]
+; GFX6-NEXT: v_mul_lo_u32 v5, s3, v0
+; GFX6-NEXT: v_mul_lo_u32 v4, s2, v0
+; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; GFX6-NEXT: v_mul_lo_u32 v3, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v4, v0, v5
-; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GFX6-NEXT: v_mul_hi_u32 v3, v0, v4
+; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v7, v0, v2
+; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
+; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
-; GFX6-NEXT: v_mul_lo_u32 v6, v1, v5
-; GFX6-NEXT: v_mul_hi_u32 v5, v1, v5
-; GFX6-NEXT: s_mov_b32 s11, 0xf000
-; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
; GFX6-NEXT: v_cvt_f32_u32_e32 v7, s5
; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v5, v1, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s17, v1
-; GFX6-NEXT: v_mac_f32_e32 v6, s18, v7
+; GFX6-NEXT: v_mac_f32_e32 v6, 0x4f800000, v7
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s16, v0
; GFX6-NEXT: v_rcp_f32_e32 v6, v6
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[0:1]
-; GFX6-NEXT: v_mul_f32_e32 v3, s19, v6
-; GFX6-NEXT: v_mul_f32_e32 v4, s20, v3
+; GFX6-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v6
+; GFX6-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
; GFX6-NEXT: v_trunc_f32_e32 v4, v4
-; GFX6-NEXT: v_mac_f32_e32 v3, s21, v4
+; GFX6-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX6-NEXT: s_sub_u32 s0, 0, s4
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX9-NEXT: s_mov_b64 s[2:3], 0x1000
-; GFX9-NEXT: s_mov_b32 s16, 0x4f800000
-; GFX9-NEXT: s_mov_b32 s17, 0x5f7ffffc
-; GFX9-NEXT: s_mov_b32 s18, 0x2f800000
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b64 s[10:11], s[2:3], s10
; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s8
; GFX9-NEXT: s_xor_b64 s[12:13], s[2:3], s[8:9]
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s12
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s13
-; GFX9-NEXT: s_mov_b32 s19, 0xcf800000
; GFX9-NEXT: s_sub_u32 s2, 0, s12
; GFX9-NEXT: s_subb_u32 s3, 0, s13
-; GFX9-NEXT: v_mac_f32_e32 v0, s16, v1
-; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_ashr_i32 s8, s5, 31
+; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_mov_b32 s9, s8
-; GFX9-NEXT: v_mul_f32_e32 v0, s17, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, s18, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1
-; GFX9-NEXT: v_mac_f32_e32 v0, s19, v1
+; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_lo_u32 v2, s2, v1
; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4
; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2
-; GFX9-NEXT: v_mul_hi_u32 v6, v0, v2
-; GFX9-NEXT: v_mul_hi_u32 v7, v1, v2
-; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v6, v1, v4
+; GFX9-NEXT: v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
-; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
-; GFX9-NEXT: v_mul_lo_u32 v6, v1, v4
-; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
-; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v7, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v6, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v8, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_mov_b32_e32 v6, s15
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v6, v2, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s13, v2
-; GFX9-NEXT: v_mac_f32_e32 v7, s16, v8
+; GFX9-NEXT: v_mac_f32_e32 v7, 0x4f800000, v8
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v1
; GFX9-NEXT: v_rcp_f32_e32 v7, v7
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[0:1]
-; GFX9-NEXT: v_mul_f32_e32 v4, s17, v7
-; GFX9-NEXT: v_mul_f32_e32 v5, s18, v4
+; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v7
+; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
; GFX9-NEXT: v_trunc_f32_e32 v5, v5
-; GFX9-NEXT: v_mac_f32_e32 v4, s19, v5
+; GFX9-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX9-NEXT: s_sub_u32 s0, 0, s10
; GCN-LABEL: f:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s4, 0xffff80
-; GCN-NEXT: v_or_b32_e32 v0, s4, v0
-; GCN-NEXT: v_or_b32_e32 v1, s4, v1
+; GCN-NEXT: v_or_b32_e32 v0, 0xffff80, v0
+; GCN-NEXT: v_or_b32_e32 v1, 0xffff80, v1
; GCN-NEXT: v_mul_i32_i24_e32 v0, v0, v1
; GCN-NEXT: v_lshrrev_b32_e32 v0, 14, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
; FUNC-LABEL: {{^}}v_and_multi_use_constant_i64:
; SI-DAG: buffer_load_dwordx2 v[[[LO0:[0-9]+]]:[[HI0:[0-9]+]]]
; SI-DAG: buffer_load_dwordx2 v[[[LO1:[0-9]+]]:[[HI1:[0-9]+]]]
-; SI-DAG: s_movk_i32 [[KHI:s[0-9]+]], 0x11e{{$}}
-; SI-DAG: s_mov_b32 [[KLO:s[0-9]+]], 0xab19b207{{$}}
-; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO0]]
-; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI0]]
-; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO1]]
-; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI1]]
+; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0xab19b207, v[[LO0]]
+; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0x11e, v[[HI0]]
+; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0xab19b207, v[[LO1]]
+; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0x11e, v[[HI1]]
; SI: buffer_store_dwordx2
; SI: buffer_store_dwordx2
define amdgpu_kernel void @v_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
; SI-NEXT: v_alignbit_b32 v4, v1, v1, 8
; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24
; SI-NEXT: s_mov_b32 s4, 0xff00ff
-; SI-NEXT: s_mov_b32 s5, 0xffff0000
; SI-NEXT: v_alignbit_b32 v5, v0, v0, 8
; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24
; SI-NEXT: v_alignbit_b32 v6, v3, v3, 8
; SI-NEXT: v_bfi_b32 v0, s4, v0, v5
; SI-NEXT: v_bfi_b32 v3, s4, v3, v6
; SI-NEXT: v_bfi_b32 v2, s4, v2, v7
-; SI-NEXT: v_and_b32_e32 v4, s5, v1
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_and_b32_e32 v3, s5, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; SI-NEXT: v_or_b32_e32 v0, v0, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; SI-NEXT: s_mov_b32 s12, 0xff00
-; SI-NEXT: s_movk_i32 s13, 0xff
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s10, s2
+; SI-NEXT: s_mov_b32 s11, s3
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5
-; SI-NEXT: s_mov_b32 s11, s3
; SI-NEXT: s_mov_b32 s8, s6
; SI-NEXT: s_mov_b32 s9, s7
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; SI-NEXT: v_add_i32_e32 v3, vcc, 9, v0
-; SI-NEXT: v_and_b32_e32 v2, s12, v0
-; SI-NEXT: v_and_b32_e32 v4, s12, v1
-; SI-NEXT: v_and_b32_e32 v3, s13, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xff00, v0
+; SI-NEXT: v_and_b32_e32 v4, 0xff00, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, 9, v1
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v1, s13, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x900, v2
; SI-NEXT: v_or_b32_e32 v1, v4, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; VI-NEXT: s_movk_i32 s12, 0xff00
-; VI-NEXT: s_movk_i32 s13, 0xff
-; VI-NEXT: s_movk_i32 s14, 0x900
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_mov_b32 s10, s6
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s7, 0xf000
-; VI-NEXT: s_mov_b32 s6, -1
-; VI-NEXT: s_mov_b32 s10, s6
; VI-NEXT: s_mov_b32 s11, s7
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s9, s3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; VI-NEXT: v_and_b32_e32 v4, s12, v1
+; VI-NEXT: v_and_b32_e32 v4, 0xffffff00, v1
; VI-NEXT: v_add_u16_e32 v1, 9, v1
; VI-NEXT: v_add_u16_e32 v3, 9, v0
-; VI-NEXT: v_and_b32_e32 v1, s13, v1
-; VI-NEXT: v_and_b32_e32 v2, s12, v0
-; VI-NEXT: v_and_b32_e32 v3, s13, v3
+; VI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; VI-NEXT: v_and_b32_e32 v2, 0xffffff00, v0
+; VI-NEXT: v_and_b32_e32 v3, 0xff, v3
; VI-NEXT: v_or_b32_e32 v1, v4, v1
; VI-NEXT: v_or_b32_e32 v2, v2, v3
-; VI-NEXT: v_add_u16_e32 v1, s14, v1
-; VI-NEXT: v_add_u16_e32 v2, s14, v2
+; VI-NEXT: v_add_u16_e32 v1, 0x900, v1
+; VI-NEXT: v_add_u16_e32 v2, 0x900, v2
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_mov_b64 s[12:13], s[6:7]
; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
-; SI-NEXT: s_mov_b32 s16, 0xff00
-; SI-NEXT: s_movk_i32 s17, 0xff
; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_mov_b32 s14, s10
; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; SI-NEXT: v_add_i32_e32 v3, vcc, 9, v0
-; SI-NEXT: v_and_b32_e32 v2, s16, v0
-; SI-NEXT: v_and_b32_e32 v4, s16, v1
-; SI-NEXT: v_and_b32_e32 v3, s17, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xff00, v0
+; SI-NEXT: v_and_b32_e32 v4, 0xff00, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, 9, v1
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v1, s17, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x900, v2
; SI-NEXT: v_or_b32_e32 v1, v4, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; VI-NEXT: s_movk_i32 s16, 0xff00
-; VI-NEXT: s_movk_i32 s17, 0xff
-; VI-NEXT: s_movk_i32 s18, 0x900
+; VI-NEXT: s_mov_b32 s11, 0xf000
+; VI-NEXT: s_mov_b32 s10, -1
+; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1]
-; VI-NEXT: s_mov_b32 s11, 0xf000
-; VI-NEXT: s_mov_b32 s10, -1
-; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_mov_b32 s15, s11
; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; VI-NEXT: v_and_b32_e32 v4, s16, v1
+; VI-NEXT: v_and_b32_e32 v4, 0xffffff00, v1
; VI-NEXT: v_add_u16_e32 v1, 9, v1
; VI-NEXT: v_add_u16_e32 v3, 9, v0
-; VI-NEXT: v_and_b32_e32 v1, s17, v1
-; VI-NEXT: v_and_b32_e32 v2, s16, v0
-; VI-NEXT: v_and_b32_e32 v3, s17, v3
+; VI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; VI-NEXT: v_and_b32_e32 v2, 0xffffff00, v0
+; VI-NEXT: v_and_b32_e32 v3, 0xff, v3
; VI-NEXT: v_or_b32_e32 v1, v4, v1
; VI-NEXT: v_or_b32_e32 v2, v2, v3
-; VI-NEXT: v_add_u16_e32 v1, s18, v1
-; VI-NEXT: v_add_u16_e32 v2, s18, v2
+; VI-NEXT: v_add_u16_e32 v1, 0x900, v1
+; VI-NEXT: v_add_u16_e32 v2, 0x900, v2
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-NEXT: s_mov_b32 s4, 0xffff
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v2, s4, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_and_b32_e32 v3, s4, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v1
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_bcnt_u32_b32_e64 v1, v1, 0
; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, 0
; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s4, 0xffff
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; VI-NEXT: v_and_b32_e32 v1, s4, v1
-; VI-NEXT: v_and_b32_e32 v0, s4, v0
+; VI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; VI-NEXT: v_bcnt_u32_b32 v2, v2, 0
; VI-NEXT: v_bcnt_u32_b32 v3, v3, 0
; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-NEXT: s_mov_b32 s4, 0xffff
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v4, s4, v0
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_and_b32_e32 v5, s4, v1
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v1
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v6, s4, v2
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v2
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v7, s4, v3
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v3
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_bcnt_u32_b32_e64 v3, v3, 0
; SI-NEXT: v_bcnt_u32_b32_e64 v2, v2, 0
; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; VI-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s4, 0xffff
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; VI-NEXT: v_and_b32_e32 v3, s4, v3
-; VI-NEXT: v_and_b32_e32 v2, s4, v2
-; VI-NEXT: v_and_b32_e32 v1, s4, v1
-; VI-NEXT: v_and_b32_e32 v0, s4, v0
+; VI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; VI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; VI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; VI-NEXT: v_bcnt_u32_b32 v4, v4, 0
; VI-NEXT: v_bcnt_u32_b32 v5, v5, 0
; VI-NEXT: v_bcnt_u32_b32 v6, v6, 0
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64 offset:16
; SI-NEXT: buffer_load_dwordx4 v[4:7], v[4:5], s[4:7], 0 addr64
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-NEXT: s_mov_b32 s4, 0xffff
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v8, s4, v0
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_and_b32_e32 v9, s4, v1
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v1
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v10, s4, v2
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v2
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v11, s4, v3
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v3
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v12, s4, v4
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v4
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v13, s4, v5
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v5
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v14, s4, v6
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v6
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v15, s4, v7
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v7
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; SI-NEXT: v_bcnt_u32_b32_e64 v7, v7, 0
; SI-NEXT: v_bcnt_u32_b32_e64 v6, v6, 0
; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; VI-NEXT: v_lshlrev_b32_e32 v0, 5, v0
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s4, 0xffff
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v4, vcc, s2, v0
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v0
-; VI-NEXT: v_and_b32_e32 v3, s4, v3
-; VI-NEXT: v_and_b32_e32 v2, s4, v2
-; VI-NEXT: v_and_b32_e32 v1, s4, v1
-; VI-NEXT: v_and_b32_e32 v0, s4, v0
+; VI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; VI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; VI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v6
; VI-NEXT: v_bcnt_u32_b32 v9, v9, 0
; VI-NEXT: v_bcnt_u32_b32 v10, v10, 0
; VI-NEXT: v_bcnt_u32_b32 v11, v11, 0
-; VI-NEXT: v_and_b32_e32 v7, s4, v7
-; VI-NEXT: v_and_b32_e32 v6, s4, v6
-; VI-NEXT: v_and_b32_e32 v5, s4, v5
-; VI-NEXT: v_and_b32_e32 v4, s4, v4
+; VI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; VI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; VI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; VI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; VI-NEXT: v_bcnt_u32_b32 v3, v3, 0
; VI-NEXT: v_bcnt_u32_b32 v2, v2, 0
; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: s_movk_i32 s8, 0xff
; SI-NEXT: s_mov_b32 s6, s2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, s8, v4
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, 9, v5
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v6
; SI-NEXT: v_or_b32_e32 v0, v7, v0
-; SI-NEXT: v_and_b32_e32 v2, s8, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x900, v0
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v0, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v0, s4, v0
+; GFX9-NEXT: v_add_u16_e32 v0, 0x900, v0
; GFX9-NEXT: v_add_u16_sdwa v1, v1, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: global_store_dword v5, v0, s[2:3]
; GFX9-NEXT: v_pk_ashrrev_i16 v0, 15, v3 op_sel_hi:[0,0]
; GFX9-NEXT: s_movk_i32 s4, 0x8000
; GFX9-NEXT: v_or_b32_sdwa v1, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, s4, v0
+; GFX9-NEXT: v_or_b32_e32 v3, 0xffff8000, v0
; GFX9-NEXT: v_pk_ashrrev_i16 v0, 15, v2 op_sel_hi:[0,1]
; GFX9-NEXT: v_or_b32_sdwa v2, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, s4, v0
-; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
-; GFX9-NEXT: v_and_b32_e32 v0, v4, v0
+; GFX9-NEXT: v_or_b32_e32 v0, 0xffff8000, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
-; GFX9-NEXT: v_and_b32_e32 v2, v4, v3
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
br i1 undef, label %T, label %F
; GFX9-NEXT: v_pk_ashrrev_i16 v0, 15, v5 op_sel_hi:[0,1]
; GFX9-NEXT: s_movk_i32 s4, 0x8000
; GFX9-NEXT: v_or_b32_sdwa v1, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, s4, v0
+; GFX9-NEXT: v_or_b32_e32 v2, 0xffff8000, v0
; GFX9-NEXT: v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]
; GFX9-NEXT: v_or_b32_sdwa v3, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, s4, v0
-; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
-; GFX9-NEXT: v_and_b32_e32 v0, v4, v0
-; GFX9-NEXT: v_and_b32_e32 v2, v4, v2
+; GFX9-NEXT: v_or_b32_e32 v0, 0xffff8000, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX9-NEXT: v_lshl_or_b32 v0, v3, 16, v0
; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
}
; GCN-LABEL: test_fold_canonicalize_fmad_ftz_value_f32:
-; GCN: v_mov_b32_e32 [[V:v[0-9]+]], 0x41700000
-; GCN: v_mac_f32_e32 [[V]], v{{[0-9]+}}, v{{[0-9]+$}}
+; GCN: v_mac_f32_e32 [[V:v[0-9]+]], 0x41700000, v{{[0-9]+$}}
; GCN-NOT: v_mul
; GCN-NOT: v_max
; GCN: {{flat|global}}_store_dword v{{.+}}, [[V]]
}
; GCN-LABEL: test_fold_canonicalize_fmuladd_value_f32:
-; GCN-FLUSH: v_mac_f32_e32 [[V:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
+; GCN-FLUSH: v_mac_f32_e32 [[V:v[0-9]+]], 0x41700000, v{{[0-9]+}}
; GCN-DENORM: s_mov_b32 [[SREG:s[0-9]+]], 0x41700000
; GCN-DENORM: v_fma_f32 [[V:v[0-9]+]], v{{[0-9]+}}, [[SREG]], [[SREG]]
; GCN-NOT: v_mul
; GCN-LABEL: v_exp_v2f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s4, 0x3fb8aa3b
-; GCN-NEXT: v_mul_f32_e32 v0, s4, v0
-; GCN-NEXT: v_mul_f32_e32 v1, s4, v1
+; GCN-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
+; GCN-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1
; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: v_exp_f32_e32 v1, v1
; GCN-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: v_exp_v3f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s4, 0x3fb8aa3b
-; GCN-NEXT: v_mul_f32_e32 v0, s4, v0
-; GCN-NEXT: v_mul_f32_e32 v1, s4, v1
-; GCN-NEXT: v_mul_f32_e32 v2, s4, v2
+; GCN-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
+; GCN-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1
+; GCN-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v2
; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: v_exp_f32_e32 v1, v1
; GCN-NEXT: v_exp_f32_e32 v2, v2
; GCN-LABEL: v_exp_v4f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s4, 0x3fb8aa3b
-; GCN-NEXT: v_mul_f32_e32 v0, s4, v0
-; GCN-NEXT: v_mul_f32_e32 v1, s4, v1
-; GCN-NEXT: v_mul_f32_e32 v2, s4, v2
-; GCN-NEXT: v_mul_f32_e32 v3, s4, v3
+; GCN-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
+; GCN-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1
+; GCN-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v2
+; GCN-NEXT: v_mul_f32_e32 v3, 0x3fb8aa3b, v3
; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: v_exp_f32_e32 v1, v1
; GCN-NEXT: v_exp_f32_e32 v2, v2
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: v_mul_f32_e32 v0, s4, v0
-; SI-NEXT: v_mul_f32_e32 v1, s4, v1
+; SI-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
+; SI-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1
; SI-NEXT: v_exp_f32_e32 v0, v0
; SI-NEXT: v_exp_f32_e32 v1, v1
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: v_mul_f32_e32 v0, s4, v0
-; SI-NEXT: v_mul_f32_e32 v1, s4, v1
-; SI-NEXT: v_mul_f32_e32 v2, s4, v2
-; SI-NEXT: v_mul_f32_e32 v3, s4, v3
+; SI-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
+; SI-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1
+; SI-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v2
+; SI-NEXT: v_mul_f32_e32 v3, 0x3fb8aa3b, v3
; SI-NEXT: v_exp_f32_e32 v0, v0
; SI-NEXT: v_exp_f32_e32 v1, v1
; SI-NEXT: v_exp_f32_e32 v2, v2
; VI-LABEL: v_exp_v4f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_movk_i32 s4, 0x3dc5
; VI-NEXT: v_mov_b32_e32 v3, 0x3dc5
-; VI-NEXT: v_mul_f16_e32 v2, s4, v1
+; VI-NEXT: v_mul_f16_e32 v2, 0x3dc5, v1
; VI-NEXT: v_mul_f16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_mul_f16_e32 v4, s4, v0
+; VI-NEXT: v_mul_f16_e32 v4, 0x3dc5, v0
; VI-NEXT: v_mul_f16_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_exp_f16_e32 v2, v2
; VI-NEXT: v_exp_f16_e32 v4, v4
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_movk_i32 s4, 0x3dc5
-; GFX9-NEXT: v_mul_f16_e32 v2, s4, v1
+; GFX9-NEXT: v_mul_f16_e32 v2, 0x3dc5, v1
; GFX9-NEXT: v_mul_f16_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-NEXT: v_mul_f16_e32 v3, s4, v0
+; GFX9-NEXT: v_mul_f16_e32 v3, 0x3dc5, v0
; GFX9-NEXT: v_mul_f16_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_exp_f16_e32 v2, v2
; GFX9-NEXT: v_exp_f16_e32 v3, v3
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, 4
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
-; GFX9-NEXT: v_add_u32_e32 v2, v1, v0
-; GFX9-NEXT: v_mov_b32_e32 v3, 15
-; GFX9-NEXT: scratch_store_dword v2, v3, off
+; GFX9-NEXT: v_add_u32_e32 v1, 4, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 15
+; GFX9-NEXT: scratch_store_dword v1, v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0
+; GFX9-NEXT: v_sub_u32_e32 v0, 4, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
; GFX9-PAL-NEXT: s_mov_b32 s2, s0
; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 4
-; GFX9-PAL-NEXT: v_add_u32_e32 v2, v1, v0
-; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 15
+; GFX9-PAL-NEXT: v_add_u32_e32 v1, 4, v0
+; GFX9-PAL-NEXT: v_mov_b32_e32 v2, 15
+; GFX9-PAL-NEXT: v_sub_u32_e32 v0, 4, v0
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
-; GFX9-PAL-NEXT: scratch_store_dword v2, v3, off
+; GFX9-PAL-NEXT: scratch_store_dword v1, v2, off
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-PAL-NEXT: v_sub_u32_e32 v0, v1, v0
; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm
; GFX9-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x104
-; GFX9-NEXT: v_add_u32_e32 v2, v1, v0
-; GFX9-NEXT: v_mov_b32_e32 v3, 15
-; GFX9-NEXT: scratch_store_dword v2, v3, off
+; GFX9-NEXT: v_add_u32_e32 v1, 0x104, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 15
+; GFX9-NEXT: scratch_store_dword v1, v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0
+; GFX9-NEXT: v_sub_u32_e32 v0, 0x104, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 15
+; GFX9-PAL-NEXT: v_mov_b32_e32 v2, 15
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-PAL-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 0x104
-; GFX9-PAL-NEXT: v_add_u32_e32 v2, v1, v0
-; GFX9-PAL-NEXT: scratch_store_dword v2, v3, off
+; GFX9-PAL-NEXT: v_add_u32_e32 v1, 0x104, v0
+; GFX9-PAL-NEXT: scratch_store_dword v1, v2, off
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-PAL-NEXT: v_sub_u32_e32 v0, v1, v0
+; GFX9-PAL-NEXT: v_sub_u32_e32 v0, 0x104, v0
; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm
; GFX9-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x4004
-; GFX9-NEXT: v_add_u32_e32 v2, v1, v0
-; GFX9-NEXT: v_mov_b32_e32 v3, 15
-; GFX9-NEXT: scratch_store_dword v2, v3, off
+; GFX9-NEXT: v_add_u32_e32 v1, 0x4004, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 15
+; GFX9-NEXT: scratch_store_dword v1, v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0
+; GFX9-NEXT: v_sub_u32_e32 v0, 0x4004, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 15
+; GFX9-PAL-NEXT: v_mov_b32_e32 v2, 15
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-PAL-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 0x4004
-; GFX9-PAL-NEXT: v_add_u32_e32 v2, v1, v0
-; GFX9-PAL-NEXT: scratch_store_dword v2, v3, off
+; GFX9-PAL-NEXT: v_add_u32_e32 v1, 0x4004, v0
+; GFX9-PAL-NEXT: scratch_store_dword v1, v2, off
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-PAL-NEXT: v_sub_u32_e32 v0, v1, v0
+; GFX9-PAL-NEXT: v_sub_u32_e32 v0, 0x4004, v0
; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm
; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2
; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX9-SAFE-NEXT: v_mov_b32_e32 v2, 0xffff
-; GFX9-SAFE-NEXT: v_and_b32_e32 v0, v2, v0
-; GFX9-SAFE-NEXT: v_and_b32_e32 v1, v2, v1
+; GFX9-SAFE-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-SAFE-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-SAFE-NEXT: v_lshl_or_b32 v0, v4, 16, v0
; GFX9-SAFE-NEXT: v_lshl_or_b32 v1, v6, 16, v1
; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v4
; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; GFX9-SAFE-NEXT: v_mov_b32_e32 v4, 0xffff
-; GFX9-SAFE-NEXT: v_and_b32_e32 v0, v4, v0
-; GFX9-SAFE-NEXT: v_and_b32_e32 v1, v4, v1
-; GFX9-SAFE-NEXT: v_and_b32_e32 v2, v4, v2
-; GFX9-SAFE-NEXT: v_and_b32_e32 v3, v4, v3
+; GFX9-SAFE-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-SAFE-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-SAFE-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-SAFE-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX9-SAFE-NEXT: v_lshl_or_b32 v0, v8, 16, v0
; GFX9-SAFE-NEXT: v_lshl_or_b32 v1, v10, 16, v1
; GFX9-SAFE-NEXT: v_lshl_or_b32 v2, v12, 16, v2
; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v2
; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX9-SAFE-NEXT: v_mov_b32_e32 v2, 0xffff
-; GFX9-SAFE-NEXT: v_and_b32_e32 v0, v2, v0
-; GFX9-SAFE-NEXT: v_and_b32_e32 v1, v2, v1
+; GFX9-SAFE-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-SAFE-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-SAFE-NEXT: v_lshl_or_b32 v0, v4, 16, v0
; GFX9-SAFE-NEXT: v_lshl_or_b32 v1, v6, 16, v1
; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX9-SAFE-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v4
; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; GFX9-SAFE-NEXT: v_mov_b32_e32 v4, 0xffff
-; GFX9-SAFE-NEXT: v_and_b32_e32 v0, v4, v0
-; GFX9-SAFE-NEXT: v_and_b32_e32 v1, v4, v1
-; GFX9-SAFE-NEXT: v_and_b32_e32 v2, v4, v2
-; GFX9-SAFE-NEXT: v_and_b32_e32 v3, v4, v3
+; GFX9-SAFE-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-SAFE-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-SAFE-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-SAFE-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX9-SAFE-NEXT: v_lshl_or_b32 v0, v8, 16, v0
; GFX9-SAFE-NEXT: v_lshl_or_b32 v1, v10, 16, v1
; GFX9-SAFE-NEXT: v_lshl_or_b32 v2, v12, 16, v2
}
; GCN-LABEL: {{^}}v_fneg_add_store_use_fneg_x_f32:
-; GCN-SAFE-DAG: s_brev_b32 [[SIGNBIT:s[0-9]+]], 1{{$}}
; GCN-DAG: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN-DAG: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
-; GCN-SAFE: v_xor_b32_e32 [[NEG_A:v[0-9]+]], [[SIGNBIT]], [[A]]
+; GCN-SAFE: v_xor_b32_e32 [[NEG_A:v[0-9]+]], 0x80000000, [[A]]
; GCN-SAFE: v_sub_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]]
-; GCN-SAFE: v_xor_b32_e32 [[NEG_ADD:v[0-9]+]], [[SIGNBIT]], [[ADD]]
+; GCN-SAFE: v_xor_b32_e32 [[NEG_ADD:v[0-9]+]], 0x80000000, [[ADD]]
; GCN-NSZ-DAG: v_xor_b32_e32 [[NEG_A:v[0-9]+]], 0x80000000, [[A]]
; GCN-NSZ-DAG: v_sub_f32_e32 [[NEG_ADD:v[0-9]+]], [[A]], [[B]]
# operands
# CHECK-LABEL: name: add_f32_1.0_multi_f16_use
-# CHECK: %13:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
-# CHECK: %14:vgpr_32 = V_ADD_F16_e32 killed %11, %13, implicit $mode, implicit $exec
-# CHECK: %15:vgpr_32 = V_ADD_F16_e32 killed %12, killed %13, implicit $mode, implicit $exec
+# CHECK: %14:vgpr_32 = V_ADD_F16_e32 1065353216, killed %11, implicit $mode, implicit $exec
+# CHECK: %15:vgpr_32 = V_ADD_F16_e32 1065353216, killed %12, implicit $mode, implicit $exec
name: add_f32_1.0_multi_f16_use
# constant, and not folded as a multi-use literal for the f16 cases
# CHECK-LABEL: name: add_f32_1.0_one_f32_use_multi_f16_use
-# CHECK: %14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
-# CHECK: %15:vgpr_32 = V_ADD_F16_e32 %11, %14, implicit $mode, implicit $exec
-# CHECK: %16:vgpr_32 = V_ADD_F16_e32 %12, %14, implicit $mode, implicit $exec
+# CHECK: %15:vgpr_32 = V_ADD_F16_e32 1065353216, %11, implicit $mode, implicit $exec
+# CHECK: %16:vgpr_32 = V_ADD_F16_e32 1065353216, %12, implicit $mode, implicit $exec
# CHECK: %17:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit $mode, implicit $exec
name: add_f32_1.0_one_f32_use_multi_f16_use
# constant, and not folded as a multi-use literal for the f16 cases
# CHECK-LABEL: name: add_f16_1.0_multi_f32_use
-# CHECK: %13:vgpr_32 = V_MOV_B32_e32 15360, implicit $exec
-# CHECK: %14:vgpr_32 = V_ADD_F32_e32 %11, %13, implicit $mode, implicit $exec
-# CHECK: %15:vgpr_32 = V_ADD_F32_e32 %12, %13, implicit $mode, implicit $exec
+# CHECK: %14:vgpr_32 = V_ADD_F32_e32 15360, %11, implicit $mode, implicit $exec
+# CHECK: %15:vgpr_32 = V_ADD_F32_e32 15360, %12, implicit $mode, implicit $exec
name: add_f16_1.0_multi_f32_use
alignment: 1
---
# The low 16-bits are an inline immediate, but the high bits are junk
-# FIXME: Should be able to fold this
# CHECK-LABEL: name: add_f16_1.0_other_high_bits_multi_f16_use
-# CHECK: %13:vgpr_32 = V_MOV_B32_e32 80886784, implicit $exec
-# CHECK: %14:vgpr_32 = V_ADD_F16_e32 %11, %13, implicit $mode, implicit $exec
-# CHECK: %15:vgpr_32 = V_ADD_F16_e32 %12, %13, implicit $mode, implicit $exec
+# CHECK: %14:vgpr_32 = V_ADD_F16_e32 80886784, %11, implicit $mode, implicit $exec
+# CHECK: %15:vgpr_32 = V_ADD_F16_e32 80886784, %12, implicit $mode, implicit $exec
name: add_f16_1.0_other_high_bits_multi_f16_use
alignment: 1
...
---
-# FIXME: Should fold inline immediate into f16 and literal use into
-# f32 instruction.
-
# CHECK-LABEL: name: add_f16_1.0_other_high_bits_use_f16_f32
-# CHECK: %13:vgpr_32 = V_MOV_B32_e32 305413120, implicit $exec
-# CHECK: %14:vgpr_32 = V_ADD_F32_e32 %11, %13, implicit $mode, implicit $exec
-# CHECK: %15:vgpr_32 = V_ADD_F16_e32 %12, %13, implicit $mode, implicit $exec
+# CHECK: %14:vgpr_32 = V_ADD_F32_e32 305413120, %11, implicit $mode, implicit $exec
+# CHECK: %15:vgpr_32 = V_ADD_F16_e32 305413120, %12, implicit $mode, implicit $exec
name: add_f16_1.0_other_high_bits_use_f16_f32
alignment: 1
exposesReturnsTwice: false
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s2, 0x2f800000
-; SI-NEXT: s_mov_b32 s3, 0xcf800000
+; SI-NEXT: s_mov_b32 s2, 0xcf800000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_trunc_f32_e32 v0, s1
; SI-NEXT: v_trunc_f32_e32 v2, s0
-; SI-NEXT: v_mul_f32_e32 v1, s2, v0
-; SI-NEXT: v_mul_f32_e32 v3, s2, v2
+; SI-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; SI-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
; SI-NEXT: v_floor_f32_e32 v4, v1
; SI-NEXT: v_floor_f32_e32 v5, v3
; SI-NEXT: v_cvt_u32_f32_e32 v3, v4
; SI-NEXT: v_cvt_u32_f32_e32 v1, v5
-; SI-NEXT: v_fma_f32 v0, v4, s3, v0
-; SI-NEXT: v_fma_f32 v4, v5, s3, v2
+; SI-NEXT: v_fma_f32 v0, v4, s2, v0
+; SI-NEXT: v_fma_f32 v4, v5, s2, v2
; SI-NEXT: v_cvt_u32_f32_e32 v2, v0
; SI-NEXT: v_cvt_u32_f32_e32 v0, v4
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s4, 0x2f800000
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_trunc_f32_e32 v0, s3
; VI-NEXT: v_trunc_f32_e32 v4, s2
-; VI-NEXT: v_mul_f32_e32 v1, s4, v0
-; VI-NEXT: v_mul_f32_e32 v2, s4, v4
+; VI-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; VI-NEXT: v_mul_f32_e32 v2, 0x2f800000, v4
; VI-NEXT: v_floor_f32_e32 v5, v1
; VI-NEXT: s_mov_b32 s2, 0xcf800000
; VI-NEXT: v_floor_f32_e32 v6, v2
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s8, 0x2f800000
-; SI-NEXT: s_mov_b32 s9, 0xcf800000
+; SI-NEXT: s_mov_b32 s8, 0xcf800000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_trunc_f32_e32 v0, s1
; SI-NEXT: v_trunc_f32_e32 v2, s0
; SI-NEXT: v_trunc_f32_e32 v4, s3
; SI-NEXT: v_trunc_f32_e32 v6, s2
-; SI-NEXT: v_mul_f32_e32 v1, s8, v0
-; SI-NEXT: v_mul_f32_e32 v3, s8, v2
-; SI-NEXT: v_mul_f32_e32 v5, s8, v4
-; SI-NEXT: v_mul_f32_e32 v7, s8, v6
+; SI-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; SI-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; SI-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
+; SI-NEXT: v_mul_f32_e32 v7, 0x2f800000, v6
; SI-NEXT: v_floor_f32_e32 v8, v1
; SI-NEXT: v_floor_f32_e32 v9, v3
; SI-NEXT: v_floor_f32_e32 v10, v5
; SI-NEXT: v_floor_f32_e32 v11, v7
; SI-NEXT: v_cvt_u32_f32_e32 v3, v8
; SI-NEXT: v_cvt_u32_f32_e32 v1, v9
-; SI-NEXT: v_fma_f32 v0, v8, s9, v0
-; SI-NEXT: v_fma_f32 v8, v9, s9, v2
+; SI-NEXT: v_fma_f32 v0, v8, s8, v0
+; SI-NEXT: v_fma_f32 v8, v9, s8, v2
; SI-NEXT: v_cvt_u32_f32_e32 v7, v10
; SI-NEXT: v_cvt_u32_f32_e32 v5, v11
-; SI-NEXT: v_fma_f32 v4, v10, s9, v4
-; SI-NEXT: v_fma_f32 v9, v11, s9, v6
+; SI-NEXT: v_fma_f32 v4, v10, s8, v4
+; SI-NEXT: v_fma_f32 v9, v11, s8, v6
; SI-NEXT: v_cvt_u32_f32_e32 v2, v0
; SI-NEXT: v_cvt_u32_f32_e32 v0, v8
; SI-NEXT: v_cvt_u32_f32_e32 v6, v4
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s2, 0x2f800000
-; VI-NEXT: s_mov_b32 s3, 0xcf800000
+; VI-NEXT: s_mov_b32 s2, 0xcf800000
+; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_trunc_f32_e32 v0, s5
; VI-NEXT: v_trunc_f32_e32 v4, s4
-; VI-NEXT: v_mul_f32_e32 v1, s2, v0
-; VI-NEXT: v_mul_f32_e32 v2, s2, v4
+; VI-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; VI-NEXT: v_mul_f32_e32 v2, 0x2f800000, v4
; VI-NEXT: v_floor_f32_e32 v5, v1
; VI-NEXT: v_floor_f32_e32 v6, v2
-; VI-NEXT: v_fma_f32 v0, v5, s3, v0
+; VI-NEXT: v_fma_f32 v0, v5, s2, v0
; VI-NEXT: v_cvt_u32_f32_e32 v2, v0
-; VI-NEXT: v_fma_f32 v0, v6, s3, v4
+; VI-NEXT: v_fma_f32 v0, v6, s2, v4
; VI-NEXT: v_trunc_f32_e32 v4, s7
; VI-NEXT: v_cvt_u32_f32_e32 v3, v5
-; VI-NEXT: v_mul_f32_e32 v5, s2, v4
+; VI-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
; VI-NEXT: v_trunc_f32_e32 v8, s6
; VI-NEXT: v_cvt_u32_f32_e32 v1, v6
; VI-NEXT: v_floor_f32_e32 v6, v5
-; VI-NEXT: v_mul_f32_e32 v5, s2, v8
+; VI-NEXT: v_mul_f32_e32 v5, 0x2f800000, v8
; VI-NEXT: v_floor_f32_e32 v9, v5
-; VI-NEXT: v_fma_f32 v4, v6, s3, v4
+; VI-NEXT: v_fma_f32 v4, v6, s2, v4
; VI-NEXT: v_cvt_u32_f32_e32 v7, v6
; VI-NEXT: v_cvt_u32_f32_e32 v6, v4
-; VI-NEXT: v_fma_f32 v4, v9, s3, v8
+; VI-NEXT: v_fma_f32 v4, v9, s2, v8
; VI-NEXT: v_cvt_u32_f32_e32 v5, v9
; VI-NEXT: v_cvt_u32_f32_e32 v4, v4
; VI-NEXT: v_cvt_u32_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: s_mov_b32 s4, 0x80008000
-; GFX6-NEXT: v_xor_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX6-NEXT: v_xor_b32_e32 v2, s4, v2
+; GFX6-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT: v_log_f32_e32 v0, v0
; SI-NEXT: v_and_b32_e32 v10, v8, v10
; SI-NEXT: v_not_b32_e32 v11, v11
; SI-NEXT: v_and_b32_e32 v11, v9, v11
-; SI-NEXT: s_brev_b32 s8, 1
-; SI-NEXT: v_and_b32_e32 v13, s8, v9
+; SI-NEXT: v_and_b32_e32 v13, 0x80000000, v9
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v12
; SI-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc
; SI-NEXT: v_cmp_lt_i32_e64 s[0:1], 51, v12
; SI-NEXT: v_and_b32_e32 v8, v6, v8
; SI-NEXT: v_not_b32_e32 v9, v9
; SI-NEXT: v_and_b32_e32 v9, v7, v9
-; SI-NEXT: v_and_b32_e32 v11, s8, v7
+; SI-NEXT: v_and_b32_e32 v11, 0x80000000, v7
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v10
; SI-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; SI-NEXT: v_cmp_lt_i32_e64 s[0:1], 51, v10
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_xor_b32_e32 v3, -1, v2
-; GFX9-NEXT: s_mov_b32 s4, 0xf000f
; GFX9-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
-; GFX9-NEXT: v_and_b32_e32 v3, s4, v3
-; GFX9-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX9-NEXT: v_and_b32_e32 v3, 0xf000f, v3
+; GFX9-NEXT: v_and_b32_e32 v2, 0xf000f, v2
; GFX9-NEXT: v_pk_lshlrev_b16 v0, v3, v0
; GFX9-NEXT: v_pk_lshrrev_b16 v1, v2, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_or_b32_e32 v4, 16, v6
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v0, v0, v3, v4
-; SI-NEXT: s_mov_b32 s4, 0xffff
; SI-NEXT: v_or_b32_e32 v3, 16, v8
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v5
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v0, s4, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_alignbit_b32 v3, v2, v4, v3
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v2, s4, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v3
; SI-NEXT: v_alignbit_b32 v1, v3, v1, 16
; SI-NEXT: s_setpc_b64 s[30:31]
;
; SI-NEXT: v_alignbit_b32 v3, v3, v5, v4
; SI-NEXT: v_or_b32_e32 v4, 16, v10
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; SI-NEXT: s_mov_b32 s4, 0xffff
; SI-NEXT: v_alignbit_b32 v2, v2, v5, v4
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v2, s4, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v0, s4, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
; GFX9-NEXT: v_lshlrev_b16_e32 v0, v3, v0
; GFX9-NEXT: v_lshrrev_b16_e32 v2, v4, v2
; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
-; GFX9-NEXT: v_and_b32_e32 v0, v2, v0
-; GFX9-NEXT: v_and_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-NEXT: v_lshl_or_b32 v0, v7, 16, v0
; GFX9-NEXT: v_lshl_or_b32 v1, v6, 16, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
; SI-LABEL: v_fshr_v2i24:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0xffffff
-; SI-NEXT: v_and_b32_e32 v6, s4, v4
-; SI-NEXT: s_mov_b32 s5, 0xaaaaaaab
-; SI-NEXT: v_mul_hi_u32 v6, v6, s5
-; SI-NEXT: v_and_b32_e32 v7, s4, v5
+; SI-NEXT: v_and_b32_e32 v6, 0xffffff, v4
+; SI-NEXT: s_mov_b32 s4, 0xaaaaaaab
+; SI-NEXT: v_mul_hi_u32 v6, v6, s4
+; SI-NEXT: v_and_b32_e32 v7, 0xffffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_lshrrev_b32_e32 v6, 4, v6
; SI-NEXT: v_mul_u32_u24_e32 v6, 24, v6
; SI-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
-; SI-NEXT: v_mul_hi_u32 v6, v7, s5
+; SI-NEXT: v_mul_hi_u32 v6, v7, s4
; SI-NEXT: v_add_i32_e32 v4, vcc, 8, v4
; SI-NEXT: v_alignbit_b32 v0, v0, v2, v4
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v3
; VI-LABEL: v_fshr_v2i24:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0xffffff
-; VI-NEXT: v_and_b32_e32 v6, s4, v4
-; VI-NEXT: s_mov_b32 s5, 0xaaaaaaab
-; VI-NEXT: v_mul_hi_u32 v6, v6, s5
-; VI-NEXT: v_and_b32_e32 v7, s4, v5
+; VI-NEXT: v_and_b32_e32 v6, 0xffffff, v4
+; VI-NEXT: s_mov_b32 s4, 0xaaaaaaab
+; VI-NEXT: v_mul_hi_u32 v6, v6, s4
+; VI-NEXT: v_and_b32_e32 v7, 0xffffff, v5
; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: v_lshrrev_b32_e32 v6, 4, v6
; VI-NEXT: v_mul_u32_u24_e32 v6, 24, v6
; VI-NEXT: v_sub_u32_e32 v4, vcc, v4, v6
-; VI-NEXT: v_mul_hi_u32 v6, v7, s5
+; VI-NEXT: v_mul_hi_u32 v6, v7, s4
; VI-NEXT: v_add_u32_e32 v4, vcc, 8, v4
; VI-NEXT: v_alignbit_b32 v0, v0, v2, v4
; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v3
; GFX9-LABEL: v_fshr_v2i24:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s4, 0xffffff
-; GFX9-NEXT: v_and_b32_e32 v6, s4, v4
-; GFX9-NEXT: s_mov_b32 s5, 0xaaaaaaab
-; GFX9-NEXT: v_mul_hi_u32 v6, v6, s5
-; GFX9-NEXT: v_and_b32_e32 v7, s4, v5
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffffff, v4
+; GFX9-NEXT: s_mov_b32 s4, 0xaaaaaaab
+; GFX9-NEXT: v_mul_hi_u32 v6, v6, s4
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffffff, v5
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 4, v6
; GFX9-NEXT: v_mul_u32_u24_e32 v6, 24, v6
; GFX9-NEXT: v_sub_u32_e32 v4, v4, v6
-; GFX9-NEXT: v_mul_hi_u32 v6, v7, s5
+; GFX9-NEXT: v_mul_hi_u32 v6, v7, s4
; GFX9-NEXT: v_add_u32_e32 v4, 8, v4
; GFX9-NEXT: v_alignbit_b32 v0, v0, v2, v4
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v3
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s5, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
+; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v1, v3, v1, s5
+; GFX7-NEXT: v_mad_u32_u24 v1, v3, v1, s4
; GFX7-NEXT: v_mad_u32_u24 v0, v0, v2, v1
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_mov_b32 s2, 0xffff
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s3, s[0:1], 0x0
+; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v1, s2, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v2, s2, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v0, v0, v3, s3
+; GFX8-NEXT: v_mad_u32_u24 v0, v0, v3, s2
; GFX8-NEXT: v_mad_u32_u24 v2, v2, v1, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s5, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
+; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_mul_u32_u24_e32 v0, v0, v2
; GFX7-NEXT: v_mad_u32_u24 v0, v3, v1, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_add_i32_e32 v0, vcc, s5, v0
+; GFX7-NEXT: v_add_i32_e32 v0, vcc, s4, v0
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm
;
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s5, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
+; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v1, v3, v1, s5
+; GFX7-NEXT: v_mad_u32_u24 v1, v3, v1, s4
; GFX7-NEXT: v_mad_u32_u24 v0, v0, v2, v1
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_mov_b32 s2, 0xffff
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s3, s[0:1], 0x0
+; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v1, s2, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v2, s2, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v0, v0, v3, s3
+; GFX8-NEXT: v_mad_u32_u24 v0, v0, v3, s2
; GFX8-NEXT: v_mad_u32_u24 v2, v2, v1, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: s_load_dword s1, s[2:3], 0x0
+; GFX9-NODL-NEXT: s_load_dword s0, s[2:3], 0x0
; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_and_b32_e32 v3, s0, v1
+; GFX9-NODL-NEXT: v_and_b32_e32 v3, 0xffff, v1
; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_and_b32_e32 v4, s0, v2
+; GFX9-NODL-NEXT: v_and_b32_e32 v4, 0xffff, v2
; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_mad_u32_u24 v1, v2, v1, s1
+; GFX9-NODL-NEXT: v_mad_u32_u24 v1, v2, v1, s0
; GFX9-NODL-NEXT: v_mad_u32_u24 v1, v4, v3, v1
; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3]
; GFX9-NODL-NEXT: s_endpgm
; GFX7-NEXT: s_mov_b64 s[6:7], s[10:11]
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_load_dword s5, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
+; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v3, 0xffff, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v0, v0, v2, s5
+; GFX7-NEXT: v_mad_u32_u24 v0, v0, v2, s4
; GFX7-NEXT: v_mad_u32_u24 v0, v3, v1, v0
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0
-; GFX8-NEXT: s_mov_b32 s2, 0xffff
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GFX8-NEXT: flat_load_dword v1, v[2:3]
-; GFX8-NEXT: s_load_dword s3, s[0:1], 0x0
+; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v2, s2, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff, v0
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v3, s2, v1
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v0, v1, v0, s3
+; GFX8-NEXT: v_mad_u32_u24 v0, v1, v0, s2
; GFX8-NEXT: v_mad_u32_u24 v2, v3, v2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 offset:4
; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 offset:4
-; GFX7-NEXT: s_load_dword s5, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
+; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v2
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v3, 0xffff, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v0, v0, v2, s5
+; GFX7-NEXT: v_mad_u32_u24 v0, v0, v2, s4
; GFX7-NEXT: v_mad_u32_u24 v0, v3, v1, v0
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 3, v0
-; GFX8-NEXT: s_mov_b32 s2, 0xffff
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_add_u32_e32 v2, vcc, s4, v0
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v4
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s3, s[0:1], 0x0
+; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v1, s2, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v3, s2, v0
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v0, v0, v2, s3
+; GFX8-NEXT: v_mad_u32_u24 v0, v0, v2, s2
; GFX8-NEXT: v_mad_u32_u24 v2, v3, v1, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_mov_b64 s[6:7], s[10:11]
; GFX7-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_load_dword s5, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
+; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v3
+; GFX7-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v2
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v1, v1, v3, s5
+; GFX7-NEXT: v_mad_u32_u24 v1, v1, v3, s4
; GFX7-NEXT: v_mad_u32_u24 v0, v0, v2, v1
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0
-; GFX8-NEXT: s_mov_b32 s2, 0xffff
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
-; GFX8-NEXT: s_load_dword s3, s[0:1], 0x0
+; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v1, s2, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v3, s2, v3
-; GFX8-NEXT: v_and_b32_e32 v0, s2, v0
-; GFX8-NEXT: v_and_b32_e32 v2, s2, v2
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v1, v3, v1, s3
+; GFX8-NEXT: v_mad_u32_u24 v1, v3, v1, s2
; GFX8-NEXT: v_mad_u32_u24 v2, v2, v0, v1
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_mov_b64 s[6:7], s[10:11]
; GFX7-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_load_dword s5, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
+; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v3
+; GFX7-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v1, v1, v3, s5
+; GFX7-NEXT: v_mad_u32_u24 v1, v1, v3, s4
; GFX7-NEXT: v_mad_u32_u24 v0, v0, v2, v1
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0
-; GFX8-NEXT: s_mov_b32 s2, 0xffff
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
-; GFX8-NEXT: s_load_dword s3, s[0:1], 0x0
+; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v1, s2, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v3, s2, v3
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v1, v3, v1, s3
+; GFX8-NEXT: v_mad_u32_u24 v1, v3, v1, s2
; GFX8-NEXT: v_mad_u32_u24 v2, v2, v0, v1
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s5, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
+; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v0, v0, v1, s5
+; GFX7-NEXT: v_mad_u32_u24 v0, v0, v1, s4
; GFX7-NEXT: v_mad_u32_u24 v0, v3, v2, v0
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_mov_b32 s2, 0xffff
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s3, s[0:1], 0x0
+; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v1, s2, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v0, s2, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v0, v0, v3, s3
+; GFX8-NEXT: v_mad_u32_u24 v0, v0, v3, s2
; GFX8-NEXT: v_mad_u32_u24 v2, v2, v1, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s5, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
+; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v1, v3, v1, s5
+; GFX7-NEXT: v_mad_u32_u24 v1, v3, v1, s4
; GFX7-NEXT: v_mad_u32_u24 v0, v0, v2, v1
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_mov_b32 s2, 0xffff
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s3, s[0:1], 0x0
+; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v1, s2, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v2, s2, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v0, v0, v3, s3
+; GFX8-NEXT: v_mad_u32_u24 v0, v0, v3, s2
; GFX8-NEXT: v_mad_u32_u24 v1, v2, v1, v0
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v1, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s5, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
+; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v4, v0, v2, s5
+; GFX7-NEXT: v_mad_u32_u24 v4, v0, v2, s4
; GFX7-NEXT: v_mad_u32_u24 v1, v3, v1, v4
; GFX7-NEXT: v_mad_u32_u24 v0, v0, v2, v1
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_mov_b32 s2, 0xffff
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s3, s[0:1], 0x0
+; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v1, s2, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v2, s2, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v4, v2, v1, s3
+; GFX8-NEXT: v_mad_u32_u24 v4, v2, v1, s2
; GFX8-NEXT: v_mad_u32_u24 v0, v0, v3, v4
; GFX8-NEXT: v_mad_u32_u24 v2, v2, v1, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: s_load_dword s1, s[2:3], 0x0
+; GFX9-NODL-NEXT: s_load_dword s0, s[2:3], 0x0
; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_and_b32_e32 v3, s0, v1
+; GFX9-NODL-NEXT: v_and_b32_e32 v3, 0xffff, v1
; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_and_b32_e32 v4, s0, v2
+; GFX9-NODL-NEXT: v_and_b32_e32 v4, 0xffff, v2
; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NODL-NEXT: v_mul_u32_u24_e32 v2, v4, v3
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_mad_u32_u24 v3, v4, v3, s1
+; GFX9-NODL-NEXT: v_mad_u32_u24 v3, v4, v3, s0
; GFX9-NODL-NEXT: v_add3_u32 v1, v1, v3, v2
; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3]
; GFX9-NODL-NEXT: s_endpgm
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_mov_b32 s0, 0xffff
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-DL-NEXT: s_load_dword s1, s[2:3], 0x0
+; GFX9-DL-NEXT: s_load_dword s0, s[2:3], 0x0
; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_and_b32_e32 v3, s0, v1
+; GFX9-DL-NEXT: v_and_b32_e32 v3, 0xffff, v1
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_and_b32_e32 v4, s0, v2
+; GFX9-DL-NEXT: v_and_b32_e32 v4, 0xffff, v2
; GFX9-DL-NEXT: v_mul_u32_u24_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-DL-NEXT: v_mul_u32_u24_e32 v2, v4, v3
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_mad_u32_u24 v3, v4, v3, s1
+; GFX9-DL-NEXT: v_mad_u32_u24 v3, v4, v3, s0
; GFX9-DL-NEXT: v_add3_u32 v1, v1, v3, v2
; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s5, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
+; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v4, v3, v1, s5
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_mad_u32_u24 v4, v3, v1, s4
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_mad_u32_u24 v1, v3, v1, v4
; GFX7-NEXT: v_mad_u32_u24 v0, v0, v2, v1
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_mov_b32 s2, 0xffff
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s3, s[0:1], 0x0
+; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v1, s2, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v2, s2, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v4, v0, v3, s3
+; GFX8-NEXT: v_mad_u32_u24 v4, v0, v3, s2
; GFX8-NEXT: v_mad_u32_u24 v0, v0, v3, v4
; GFX8-NEXT: v_mad_u32_u24 v2, v2, v1, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ushort v1, off, s[0:3], 0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
; GFX7-NEXT: s_waitcnt vmcnt(2)
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v2
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v1, v3, v4, v1
; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ushort v1, off, s[0:3], 0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
; GFX7-NEXT: s_waitcnt vmcnt(2)
; GFX7-NEXT: v_bfe_i32 v3, v2, 0, 8
; GFX7-NEXT: v_bfe_i32 v4, v2, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_bfe_i32 v6, v0, 0, 8
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v3
+; GFX7-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX7-NEXT: v_bfe_i32 v7, v0, 8, 8
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v6
+; GFX7-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX7-NEXT: v_bfe_i32 v5, v2, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v4, s4, v4
+; GFX7-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX7-NEXT: v_bfe_i32 v8, v0, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v7, s4, v7
+; GFX7-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v1, v3, v6, v1
; GFX7-NEXT: v_ashrrev_i32_e32 v2, 24, v2
-; GFX7-NEXT: v_and_b32_e32 v5, s4, v5
+; GFX7-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX7-NEXT: v_ashrrev_i32_e32 v0, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v8, s4, v8
+; GFX7-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX7-NEXT: v_mad_u32_u24 v1, v4, v7, v1
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v2
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_mad_u32_u24 v1, v5, v8, v1
; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ubyte v1, off, s[0:3], 0
-; GFX7-NEXT: s_movk_i32 s4, 0xff
; GFX7-NEXT: s_waitcnt vmcnt(2)
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v2
; GFX7-NEXT: v_bfe_u32 v4, v2, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v7, v0, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v1, v3, v6, v1
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ushort v1, off, s[0:3], 0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
; GFX7-NEXT: s_waitcnt vmcnt(2)
; GFX7-NEXT: v_bfe_i32 v3, v2, 8, 8
; GFX7-NEXT: v_bfe_i32 v4, v2, 0, 8
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX7-NEXT: v_and_b32_e32 v4, s4, v4
+; GFX7-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_bfe_i32 v6, v0, 8, 8
; GFX7-NEXT: v_bfe_i32 v7, v0, 0, 8
; GFX7-NEXT: v_or_b32_e32 v3, v4, v3
; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v7
+; GFX7-NEXT: v_and_b32_e32 v6, 0xffff, v7
; GFX7-NEXT: v_bfe_i32 v8, v0, 16, 8
; GFX7-NEXT: v_or_b32_e32 v4, v6, v4
-; GFX7-NEXT: v_and_b32_e32 v7, s4, v8
+; GFX7-NEXT: v_and_b32_e32 v7, 0xffff, v8
; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v3
+; GFX7-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v4
-; GFX7-NEXT: v_and_b32_e32 v4, s4, v4
+; GFX7-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX7-NEXT: v_bfe_i32 v5, v2, 16, 8
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v1, v3, v4, v1
; GFX7-NEXT: v_ashrrev_i32_e32 v2, 24, v2
-; GFX7-NEXT: v_and_b32_e32 v5, s4, v5
+; GFX7-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX7-NEXT: v_ashrrev_i32_e32 v0, 24, v0
; GFX7-NEXT: v_mad_u32_u24 v1, v6, v8, v1
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v2
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_mad_u32_u24 v1, v5, v7, v1
; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s5, s[0:1], 0x0
-; GFX7-NEXT: s_movk_i32 s4, 0xff
+; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX7-NEXT: v_bfe_u32 v3, v2, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_and_b32_e32 v5, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v5, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v6, v0, 8, 8
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v1, v1, v5, s5
+; GFX7-NEXT: v_mad_u32_u24 v1, v1, v5, s4
; GFX7-NEXT: v_bfe_u32 v4, v2, 16, 8
; GFX7-NEXT: v_bfe_u32 v7, v0, 16, 8
; GFX7-NEXT: v_mad_u32_u24 v1, v3, v6, v1
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_movk_i32 s2, 0xff
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s3, s[0:1], 0x0
+; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v1, s2, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v3
; GFX8-NEXT: v_bfe_u32 v4, v3, 8, 8
; GFX8-NEXT: v_bfe_u32 v6, v3, 16, 8
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v2, s2, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v0
; GFX8-NEXT: v_bfe_u32 v5, v0, 8, 8
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v1, v1, v2, s3
+; GFX8-NEXT: v_mad_u32_u24 v1, v1, v2, s2
; GFX8-NEXT: v_bfe_u32 v7, v0, 16, 8
; GFX8-NEXT: v_mad_u32_u24 v1, v4, v5, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 24, v0
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ushort v1, off, s[0:3], 0
-; GFX7-NEXT: s_movk_i32 s4, 0xff
; GFX7-NEXT: s_waitcnt vmcnt(2)
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v2
; GFX7-NEXT: v_bfe_u32 v4, v2, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v7, v0, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v1, v3, v6, v1
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_ushort v4, v[0:1]
-; GFX8-NEXT: s_movk_i32 s0, 0xff
; GFX8-NEXT: s_waitcnt vmcnt(2)
-; GFX8-NEXT: v_and_b32_e32 v6, s0, v3
+; GFX8-NEXT: v_and_b32_e32 v6, 0xff, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 8, v3
-; GFX8-NEXT: v_and_b32_e32 v8, s0, v8
+; GFX8-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX8-NEXT: v_and_b32_sdwa v10, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v7, s0, v2
+; GFX8-NEXT: v_and_b32_e32 v7, 0xff, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v9, 8, v2
-; GFX8-NEXT: v_and_b32_e32 v9, s0, v9
+; GFX8-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mad_u16 v4, v6, v7, v4
; GFX8-NEXT: v_and_b32_sdwa v5, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NODL-NEXT: global_load_ushort v3, v0, s[2:3]
; GFX9-NODL-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NODL-NEXT: v_and_b32_e32 v4, s0, v1
+; GFX9-NODL-NEXT: v_and_b32_e32 v4, 0xff, v1
; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_and_b32_e32 v5, s0, v2
+; GFX9-NODL-NEXT: v_and_b32_e32 v5, 0xff, v2
; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v6, 8, v1
; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v7, 8, v2
-; GFX9-NODL-NEXT: v_and_b32_e32 v6, s0, v6
-; GFX9-NODL-NEXT: v_and_b32_e32 v7, s0, v7
+; GFX9-NODL-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX9-NODL-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
; GFX9-NODL-NEXT: v_mad_legacy_u16 v3, v4, v5, v3
; GFX9-NODL-NEXT: v_and_b32_sdwa v8, v1, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DL-NEXT: global_load_ushort v3, v0, s[2:3]
; GFX9-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX9-DL-NEXT: v_and_b32_e32 v4, s0, v1
+; GFX9-DL-NEXT: v_and_b32_e32 v4, 0xff, v1
; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_and_b32_e32 v5, s0, v2
+; GFX9-DL-NEXT: v_and_b32_e32 v5, 0xff, v2
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v1
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 8, v2
-; GFX9-DL-NEXT: v_and_b32_e32 v6, s0, v6
-; GFX9-DL-NEXT: v_and_b32_e32 v7, s0, v7
+; GFX9-DL-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX9-DL-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v4, v5, v3
; GFX9-DL-NEXT: v_and_b32_sdwa v8, v1, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ubyte v1, off, s[0:3], 0
-; GFX7-NEXT: s_movk_i32 s4, 0xff
; GFX7-NEXT: s_waitcnt vmcnt(2)
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v2
; GFX7-NEXT: v_bfe_u32 v4, v2, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v7, v0, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v1, v3, v6, v1
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ubyte v1, off, s[0:3], 0
-; GFX7-NEXT: s_movk_i32 s4, 0xff
; GFX7-NEXT: s_waitcnt vmcnt(2)
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v2
; GFX7-NEXT: v_bfe_u32 v2, v2, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v4, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v0, v0, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v1, v3, v4, v1
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ubyte v1, off, s[0:3], 0
-; GFX7-NEXT: s_movk_i32 s4, 0xff
; GFX7-NEXT: s_waitcnt vmcnt(2)
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v2
; GFX7-NEXT: v_bfe_u32 v4, v2, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v7, v0, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v1, v6, v3, v1
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ubyte v1, off, s[0:3], 0
-; GFX7-NEXT: s_movk_i32 s4, 0xff
; GFX7-NEXT: s_waitcnt vmcnt(2)
; GFX7-NEXT: v_bfe_u32 v4, v2, 8, 8
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v2
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_bfe_u32 v7, v0, 8, 8
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v0
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v1, v7, v4, v1
; GFX7-NEXT: v_bfe_u32 v5, v2, 16, 8
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s5, s[0:1], 0x0
-; GFX7-NEXT: s_movk_i32 s4, 0xff
+; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX7-NEXT: v_bfe_u32 v3, v2, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_and_b32_e32 v5, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v5, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v6, v0, 8, 8
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v8, v1, v5, s5
+; GFX7-NEXT: v_mad_u32_u24 v8, v1, v5, s4
; GFX7-NEXT: v_mad_u32_u24 v3, v3, v6, v8
; GFX7-NEXT: v_bfe_u32 v4, v2, 16, 8
; GFX7-NEXT: v_bfe_u32 v7, v0, 16, 8
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_movk_i32 s2, 0xff
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s3, s[0:1], 0x0
+; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v1, s2, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v3
; GFX8-NEXT: v_bfe_u32 v4, v3, 8, 8
; GFX8-NEXT: v_bfe_u32 v6, v3, 16, 8
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v2, s2, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v0
; GFX8-NEXT: v_bfe_u32 v5, v0, 8, 8
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v8, v1, v2, s3
+; GFX8-NEXT: v_mad_u32_u24 v8, v1, v2, s2
; GFX8-NEXT: v_mad_u32_u24 v4, v4, v5, v8
; GFX8-NEXT: v_bfe_u32 v7, v0, 16, 8
; GFX8-NEXT: v_mad_u32_u24 v1, v1, v2, v4
; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_movk_i32 s0, 0xff
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: s_load_dword s1, s[2:3], 0x0
+; GFX9-NODL-NEXT: s_load_dword s0, s[2:3], 0x0
; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_and_b32_e32 v3, s0, v1
+; GFX9-NODL-NEXT: v_and_b32_e32 v3, 0xff, v1
; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_and_b32_e32 v4, s0, v2
+; GFX9-NODL-NEXT: v_and_b32_e32 v4, 0xff, v2
; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v6, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
; GFX9-NODL-NEXT: v_mul_u32_u24_e32 v2, v3, v4
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_mad_u32_u24 v3, v3, v4, s1
+; GFX9-NODL-NEXT: v_mad_u32_u24 v3, v3, v4, s0
; GFX9-NODL-NEXT: v_add3_u32 v2, v5, v3, v2
; GFX9-NODL-NEXT: v_add3_u32 v1, v2, v6, v1
; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3]
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_movk_i32 s0, 0xff
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-DL-NEXT: s_load_dword s1, s[2:3], 0x0
+; GFX9-DL-NEXT: s_load_dword s0, s[2:3], 0x0
; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_and_b32_e32 v3, s0, v1
+; GFX9-DL-NEXT: v_and_b32_e32 v3, 0xff, v1
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_and_b32_e32 v4, s0, v2
+; GFX9-DL-NEXT: v_and_b32_e32 v4, 0xff, v2
; GFX9-DL-NEXT: v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
; GFX9-DL-NEXT: v_mul_u32_u24_sdwa v6, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
; GFX9-DL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
; GFX9-DL-NEXT: v_mul_u32_u24_e32 v2, v3, v4
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_mad_u32_u24 v3, v3, v4, s1
+; GFX9-DL-NEXT: v_mad_u32_u24 v3, v3, v4, s0
; GFX9-DL-NEXT: v_add3_u32 v2, v5, v3, v2
; GFX9-DL-NEXT: v_add3_u32 v1, v2, v6, v1
; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s5, s[0:1], 0x0
-; GFX7-NEXT: s_movk_i32 s4, 0xff
+; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_bfe_u32 v3, v2, 8, 8
-; GFX7-NEXT: v_and_b32_e32 v1, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_bfe_u32 v6, v0, 8, 8
-; GFX7-NEXT: v_and_b32_e32 v5, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v5, 0xff, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v3, v3, v6, s5
+; GFX7-NEXT: v_mad_u32_u24 v3, v3, v6, s4
; GFX7-NEXT: v_bfe_u32 v4, v2, 16, 8
; GFX7-NEXT: v_bfe_u32 v7, v0, 16, 8
; GFX7-NEXT: v_mad_u32_u24 v1, v1, v5, v3
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v2
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v0
; GFX7-NEXT: v_mad_u32_u24 v1, v4, v7, v1
-; GFX7-NEXT: v_add_i32_e32 v6, vcc, s5, v3
+; GFX7-NEXT: v_add_i32_e32 v6, vcc, s4, v3
; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v6
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_movk_i32 s2, 0xff
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s3, s[0:1], 0x0
+; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX8-NEXT: s_waitcnt vmcnt(1)
; GFX8-NEXT: v_bfe_u32 v4, v3, 8, 8
-; GFX8-NEXT: v_and_b32_e32 v1, s2, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v3
; GFX8-NEXT: v_bfe_u32 v6, v3, 16, 8
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_bfe_u32 v5, v0, 8, 8
-; GFX8-NEXT: v_and_b32_e32 v2, s2, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v4, v4, v5, s3
+; GFX8-NEXT: v_mad_u32_u24 v4, v4, v5, s2
; GFX8-NEXT: v_bfe_u32 v7, v0, 16, 8
; GFX8-NEXT: v_mad_u32_u24 v1, v1, v2, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 24, v0
; GFX8-NEXT: v_mad_u32_u24 v1, v6, v7, v1
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s3, v4
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, s2, v4
; GFX8-NEXT: v_mad_u32_u24 v0, v3, v0, v1
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v0, v5
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ushort v1, off, s[0:3], 0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
; GFX7-NEXT: s_waitcnt vmcnt(2)
; GFX7-NEXT: v_bfe_i32 v3, v2, 0, 8
; GFX7-NEXT: v_bfe_u32 v4, v2, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_bfe_i32 v6, v0, 0, 8
; GFX7-NEXT: v_bfe_u32 v7, v0, 8, 8
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v3
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v6
+; GFX7-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX7-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v1, v4, v7, v1
; GFX7-NEXT: v_bfe_u32 v5, v2, 16, 8
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_ushort v4, v[0:1]
-; GFX8-NEXT: s_movk_i32 s0, 0xff
; GFX8-NEXT: s_waitcnt vmcnt(2)
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 8, v3
-; GFX8-NEXT: v_and_b32_e32 v8, s0, v8
+; GFX8-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX8-NEXT: v_bfe_i32 v6, v3, 0, 8
; GFX8-NEXT: v_and_b32_sdwa v10, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX8-NEXT: s_waitcnt vmcnt(1)
; GFX8-NEXT: v_lshrrev_b32_e32 v9, 8, v2
-; GFX8-NEXT: v_and_b32_e32 v9, s0, v9
+; GFX8-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX8-NEXT: v_bfe_i32 v7, v2, 0, 8
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mad_u16 v4, v8, v9, v4
; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v6, 8, v1
; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v7, 8, v2
-; GFX9-NODL-NEXT: v_and_b32_e32 v6, s0, v6
-; GFX9-NODL-NEXT: v_and_b32_e32 v7, s0, v7
+; GFX9-NODL-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX9-NODL-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX9-NODL-NEXT: v_bfe_i32 v4, v1, 0, 8
; GFX9-NODL-NEXT: v_bfe_i32 v5, v2, 0, 8
; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v1
; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 8, v2
-; GFX9-DL-NEXT: v_and_b32_e32 v6, s0, v6
-; GFX9-DL-NEXT: v_and_b32_e32 v7, s0, v7
+; GFX9-DL-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX9-DL-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX9-DL-NEXT: v_bfe_i32 v4, v1, 0, 8
; GFX9-DL-NEXT: v_bfe_i32 v5, v2, 0, 8
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s5, s[0:1], 0x0
-; GFX7-NEXT: s_movk_i32 s4, 0xff
+; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v2
; GFX7-NEXT: v_bfe_u32 v3, v2, 8, 8
; GFX7-NEXT: v_bfe_u32 v4, v2, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v0
; GFX7-NEXT: v_bfe_u32 v6, v0, 8, 8
; GFX7-NEXT: v_bfe_u32 v7, v0, 16, 8
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, s5
+; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, s4
; GFX7-NEXT: v_mad_u32_u24 v0, v3, v6, v0
; GFX7-NEXT: v_mad_u32_u24 v0, v4, v7, v0
; GFX7-NEXT: v_mad_u32_u24 v0, v1, v5, v0
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_movk_i32 s2, 0xff
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s3, s[0:1], 0x0
+; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX8-NEXT: s_waitcnt vmcnt(1)
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 24, v3
; GFX8-NEXT: v_bfe_u32 v4, v3, 16, 8
; GFX8-NEXT: v_lshrrev_b16_e32 v5, 8, v3
-; GFX8-NEXT: v_and_b32_e32 v3, s2, v3
+; GFX8-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 24, v0
; GFX8-NEXT: v_bfe_u32 v6, v0, 16, 8
; GFX8-NEXT: v_lshrrev_b16_e32 v7, 8, v0
-; GFX8-NEXT: v_and_b32_e32 v0, s2, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v0, v3, v0, s3
+; GFX8-NEXT: v_mad_u32_u24 v0, v3, v0, s2
; GFX8-NEXT: v_mad_u32_u24 v0, v5, v7, v0
; GFX8-NEXT: v_mad_u32_u24 v0, v4, v6, v0
; GFX8-NEXT: v_mad_u32_u24 v2, v1, v2, v0
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ushort v1, off, s[0:3], 0
-; GFX7-NEXT: s_mov_b32 s4, 0xff00
-; GFX7-NEXT: s_movk_i32 s5, 0xff
; GFX7-NEXT: s_waitcnt vmcnt(2)
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v2
-; GFX7-NEXT: v_and_b32_e32 v4, s5, v2
+; GFX7-NEXT: v_and_b32_e32 v3, 0xff00, v2
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v2
; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v6, 0xff00, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX7-NEXT: v_and_b32_e32 v7, s5, v0
+; GFX7-NEXT: v_and_b32_e32 v7, 0xff, v0
; GFX7-NEXT: v_or_b32_e32 v3, v4, v3
; GFX7-NEXT: v_lshlrev_b32_e32 v4, 8, v6
; GFX7-NEXT: v_or_b32_e32 v4, v7, v4
; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX7-NEXT: v_and_b32_e32 v3, s5, v3
+; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v4
-; GFX7-NEXT: v_and_b32_e32 v4, s5, v4
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v1, v3, v4, v1
; GFX7-NEXT: v_bfe_u32 v5, v2, 16, 8
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_ushort v4, v[0:1]
-; GFX8-NEXT: s_movk_i32 s0, 0xff
; GFX8-NEXT: s_waitcnt vmcnt(2)
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 24, v3
; GFX8-NEXT: v_lshrrev_b16_e32 v7, 8, v3
; GFX8-NEXT: v_and_b32_sdwa v10, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v3, s0, v3
+; GFX8-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX8-NEXT: s_waitcnt vmcnt(1)
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 24, v2
; GFX8-NEXT: v_lshrrev_b16_e32 v9, 8, v2
; GFX8-NEXT: v_and_b32_sdwa v5, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v2, s0, v2
+; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mad_u16 v2, v3, v2, v4
; GFX8-NEXT: v_mad_u16 v2, v7, v9, v2
; GFX9-NODL-NEXT: v_and_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NODL-NEXT: v_lshl_or_b32 v2, v7, 16, v2
; GFX9-NODL-NEXT: v_lshl_or_b32 v1, v5, 16, v1
-; GFX9-NODL-NEXT: v_and_b32_e32 v10, v4, v10
-; GFX9-NODL-NEXT: v_and_b32_e32 v4, v4, v9
+; GFX9-NODL-NEXT: v_and_b32_e32 v4, 0xffff, v10
+; GFX9-NODL-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NODL-NEXT: v_pk_mul_lo_u16 v1, v1, v2
-; GFX9-NODL-NEXT: v_lshl_or_b32 v5, v8, 16, v10
-; GFX9-NODL-NEXT: v_lshl_or_b32 v4, v6, 16, v4
+; GFX9-NODL-NEXT: v_lshl_or_b32 v4, v8, 16, v4
+; GFX9-NODL-NEXT: v_lshl_or_b32 v5, v6, 16, v9
; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
; GFX9-NODL-NEXT: v_add_u16_e32 v3, v1, v3
-; GFX9-NODL-NEXT: v_pk_mul_lo_u16 v2, v4, v5
+; GFX9-NODL-NEXT: v_pk_mul_lo_u16 v2, v5, v4
; GFX9-NODL-NEXT: v_add_u16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-NODL-NEXT: v_add_u16_e32 v1, v1, v2
; GFX9-NODL-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-DL-NEXT: v_and_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-DL-NEXT: v_lshl_or_b32 v2, v7, 16, v2
; GFX9-DL-NEXT: v_lshl_or_b32 v1, v5, 16, v1
-; GFX9-DL-NEXT: v_and_b32_e32 v10, v4, v10
-; GFX9-DL-NEXT: v_and_b32_e32 v4, v4, v9
+; GFX9-DL-NEXT: v_and_b32_e32 v4, 0xffff, v10
+; GFX9-DL-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-DL-NEXT: v_pk_mul_lo_u16 v1, v1, v2
-; GFX9-DL-NEXT: v_lshl_or_b32 v5, v8, 16, v10
-; GFX9-DL-NEXT: v_lshl_or_b32 v4, v6, 16, v4
+; GFX9-DL-NEXT: v_lshl_or_b32 v4, v8, 16, v4
+; GFX9-DL-NEXT: v_lshl_or_b32 v5, v6, 16, v9
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_add_u16_e32 v3, v1, v3
-; GFX9-DL-NEXT: v_pk_mul_lo_u16 v2, v4, v5
+; GFX9-DL-NEXT: v_pk_mul_lo_u16 v2, v5, v4
; GFX9-DL-NEXT: v_add_u16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-DL-NEXT: v_add_u16_e32 v1, v1, v2
; GFX9-DL-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ubyte v1, off, s[0:3], 0
-; GFX7-NEXT: s_movk_i32 s4, 0xff
; GFX7-NEXT: s_waitcnt vmcnt(2)
-; GFX7-NEXT: v_and_b32_e32 v4, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v2
; GFX7-NEXT: v_bfe_u32 v5, v2, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v7, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v7, 0xff, v0
; GFX7-NEXT: v_bfe_u32 v8, v0, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v1, v4, v7, v1
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ushort v1, off, s[0:3], 0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
; GFX7-NEXT: s_addc_u32 s13, s13, 0
; GFX7-NEXT: s_waitcnt vmcnt(2)
; GFX7-NEXT: v_bfe_i32 v3, v2, 0, 4
; GFX7-NEXT: v_bfe_i32 v4, v2, 4, 4
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_bfe_i32 v10, v0, 0, 4
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v3
+; GFX7-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX7-NEXT: v_bfe_i32 v11, v0, 4, 4
-; GFX7-NEXT: v_and_b32_e32 v10, s4, v10
+; GFX7-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX7-NEXT: v_bfe_i32 v5, v2, 8, 4
-; GFX7-NEXT: v_and_b32_e32 v4, s4, v4
+; GFX7-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX7-NEXT: v_bfe_i32 v12, v0, 8, 4
-; GFX7-NEXT: v_and_b32_e32 v11, s4, v11
+; GFX7-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v1, v3, v10, v1
; GFX7-NEXT: v_bfe_i32 v6, v2, 12, 4
-; GFX7-NEXT: v_and_b32_e32 v5, s4, v5
+; GFX7-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX7-NEXT: v_bfe_i32 v13, v0, 12, 4
-; GFX7-NEXT: v_and_b32_e32 v12, s4, v12
+; GFX7-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX7-NEXT: v_mad_u32_u24 v1, v4, v11, v1
; GFX7-NEXT: v_bfe_i32 v7, v2, 16, 4
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v6
+; GFX7-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX7-NEXT: v_bfe_i32 v14, v0, 16, 4
-; GFX7-NEXT: v_and_b32_e32 v13, s4, v13
+; GFX7-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX7-NEXT: v_mad_u32_u24 v1, v5, v12, v1
; GFX7-NEXT: v_bfe_i32 v8, v2, 20, 4
-; GFX7-NEXT: v_and_b32_e32 v7, s4, v7
+; GFX7-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX7-NEXT: v_bfe_i32 v15, v0, 20, 4
-; GFX7-NEXT: v_and_b32_e32 v14, s4, v14
+; GFX7-NEXT: v_and_b32_e32 v14, 0xffff, v14
; GFX7-NEXT: v_mad_u32_u24 v1, v6, v13, v1
; GFX7-NEXT: v_bfe_i32 v9, v2, 24, 4
-; GFX7-NEXT: v_and_b32_e32 v8, s4, v8
+; GFX7-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX7-NEXT: v_bfe_i32 v16, v0, 24, 4
-; GFX7-NEXT: v_and_b32_e32 v15, s4, v15
+; GFX7-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX7-NEXT: v_mad_u32_u24 v1, v7, v14, v1
; GFX7-NEXT: v_ashrrev_i32_e32 v2, 28, v2
-; GFX7-NEXT: v_and_b32_e32 v9, s4, v9
+; GFX7-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX7-NEXT: v_ashrrev_i32_e32 v0, 28, v0
-; GFX7-NEXT: v_and_b32_e32 v16, s4, v16
+; GFX7-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX7-NEXT: v_mad_u32_u24 v1, v8, v15, v1
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v2
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_mad_u32_u24 v1, v9, v16, v1
; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ubyte v1, off, s[0:3], 0
-; GFX7-NEXT: s_movk_i32 s4, 0xff
; GFX7-NEXT: s_addc_u32 s13, s13, 0
; GFX7-NEXT: s_waitcnt vmcnt(2)
; GFX7-NEXT: v_bfe_i32 v3, v2, 0, 4
; GFX7-NEXT: v_bfe_i32 v4, v2, 4, 4
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_bfe_i32 v10, v0, 0, 4
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v3
+; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX7-NEXT: v_bfe_i32 v11, v0, 4, 4
-; GFX7-NEXT: v_and_b32_e32 v10, s4, v10
+; GFX7-NEXT: v_and_b32_e32 v10, 0xff, v10
; GFX7-NEXT: v_bfe_i32 v5, v2, 8, 4
-; GFX7-NEXT: v_and_b32_e32 v4, s4, v4
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX7-NEXT: v_bfe_i32 v12, v0, 8, 4
-; GFX7-NEXT: v_and_b32_e32 v11, s4, v11
+; GFX7-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mad_u32_u24 v1, v3, v10, v1
; GFX7-NEXT: v_bfe_i32 v6, v2, 12, 4
-; GFX7-NEXT: v_and_b32_e32 v5, s4, v5
+; GFX7-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX7-NEXT: v_bfe_i32 v13, v0, 12, 4
-; GFX7-NEXT: v_and_b32_e32 v12, s4, v12
+; GFX7-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX7-NEXT: v_mad_u32_u24 v1, v4, v11, v1
; GFX7-NEXT: v_bfe_i32 v7, v2, 16, 4
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v6
+; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX7-NEXT: v_bfe_i32 v14, v0, 16, 4
-; GFX7-NEXT: v_and_b32_e32 v13, s4, v13
+; GFX7-NEXT: v_and_b32_e32 v13, 0xff, v13
; GFX7-NEXT: v_mad_u32_u24 v1, v5, v12, v1
; GFX7-NEXT: v_bfe_i32 v8, v2, 20, 4
-; GFX7-NEXT: v_and_b32_e32 v7, s4, v7
+; GFX7-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX7-NEXT: v_bfe_i32 v15, v0, 20, 4
-; GFX7-NEXT: v_and_b32_e32 v14, s4, v14
+; GFX7-NEXT: v_and_b32_e32 v14, 0xff, v14
; GFX7-NEXT: v_mad_u32_u24 v1, v6, v13, v1
; GFX7-NEXT: v_bfe_i32 v9, v2, 24, 4
-; GFX7-NEXT: v_and_b32_e32 v8, s4, v8
+; GFX7-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX7-NEXT: v_bfe_i32 v16, v0, 24, 4
-; GFX7-NEXT: v_and_b32_e32 v15, s4, v15
+; GFX7-NEXT: v_and_b32_e32 v15, 0xff, v15
; GFX7-NEXT: v_mad_u32_u24 v1, v7, v14, v1
; GFX7-NEXT: v_ashrrev_i32_e32 v2, 28, v2
-; GFX7-NEXT: v_and_b32_e32 v9, s4, v9
+; GFX7-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX7-NEXT: v_ashrrev_i32_e32 v0, 28, v0
-; GFX7-NEXT: v_and_b32_e32 v16, s4, v16
+; GFX7-NEXT: v_and_b32_e32 v16, 0xff, v16
; GFX7-NEXT: v_mad_u32_u24 v1, v8, v15, v1
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v2
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-NEXT: v_mad_u32_u24 v1, v9, v16, v1
; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1
; GFX7-NEXT: buffer_store_byte v0, off, s[0:3], 0
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ushort v1, off, s[0:3], 0
-; GFX7-NEXT: s_mov_b32 s4, 0xffff
; GFX7-NEXT: s_addc_u32 s13, s13, 0
; GFX7-NEXT: s_waitcnt vmcnt(2)
; GFX7-NEXT: v_bfe_i32 v3, v2, 20, 4
; GFX7-NEXT: v_bfe_i32 v5, v2, 4, 4
; GFX7-NEXT: v_bfe_i32 v6, v2, 0, 4
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX7-NEXT: v_and_b32_e32 v4, s4, v4
+; GFX7-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v6
+; GFX7-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_bfe_i32 v10, v0, 20, 4
; GFX7-NEXT: v_bfe_i32 v11, v0, 16, 4
; GFX7-NEXT: v_or_b32_e32 v3, v4, v3
; GFX7-NEXT: v_or_b32_e32 v4, v6, v5
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v10
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v11
+; GFX7-NEXT: v_and_b32_e32 v6, 0xffff, v11
; GFX7-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX7-NEXT: v_and_b32_e32 v11, s4, v13
+; GFX7-NEXT: v_and_b32_e32 v11, 0xffff, v13
; GFX7-NEXT: v_bfe_i32 v14, v0, 24, 4
; GFX7-NEXT: v_ashrrev_i32_e32 v16, 28, v0
; GFX7-NEXT: v_or_b32_e32 v5, v6, v5
; GFX7-NEXT: v_or_b32_e32 v6, v11, v10
-; GFX7-NEXT: v_and_b32_e32 v12, s4, v14
-; GFX7-NEXT: v_and_b32_e32 v14, s4, v16
+; GFX7-NEXT: v_and_b32_e32 v12, 0xffff, v14
+; GFX7-NEXT: v_and_b32_e32 v14, 0xffff, v16
; GFX7-NEXT: v_lshrrev_b32_e32 v16, 16, v4
-; GFX7-NEXT: v_and_b32_e32 v4, s4, v4
+; GFX7-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX7-NEXT: v_lshrrev_b32_e32 v11, 16, v6
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v6
+; GFX7-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX7-NEXT: v_bfe_i32 v8, v2, 8, 4
; GFX7-NEXT: v_bfe_i32 v15, v0, 8, 4
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_bfe_i32 v7, v2, 24, 4
; GFX7-NEXT: v_ashrrev_i32_e32 v9, 28, v2
; GFX7-NEXT: v_bfe_i32 v2, v2, 12, 4
-; GFX7-NEXT: v_and_b32_e32 v8, s4, v8
+; GFX7-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX7-NEXT: v_bfe_i32 v0, v0, 12, 4
-; GFX7-NEXT: v_and_b32_e32 v13, s4, v15
+; GFX7-NEXT: v_and_b32_e32 v13, 0xffff, v15
; GFX7-NEXT: v_mad_u32_u24 v1, v16, v11, v1
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v2
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_mad_u32_u24 v1, v8, v13, v1
; GFX7-NEXT: v_lshrrev_b32_e32 v15, 16, v3
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v3
+; GFX7-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX7-NEXT: v_lshrrev_b32_e32 v10, 16, v5
-; GFX7-NEXT: v_and_b32_e32 v5, s4, v5
+; GFX7-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1
; GFX7-NEXT: v_mad_u32_u24 v0, v3, v5, v0
-; GFX7-NEXT: v_and_b32_e32 v7, s4, v7
+; GFX7-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX7-NEXT: v_mad_u32_u24 v0, v15, v10, v0
-; GFX7-NEXT: v_and_b32_e32 v9, s4, v9
+; GFX7-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX7-NEXT: v_mad_u32_u24 v0, v7, v12, v0
; GFX7-NEXT: v_mad_u32_u24 v0, v9, v14, v0
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ubyte v1, off, s[0:3], 0
-; GFX7-NEXT: s_movk_i32 s4, 0xff
-; GFX7-NEXT: s_mov_b32 s5, 0xffff
; GFX7-NEXT: s_addc_u32 s13, s13, 0
; GFX7-NEXT: s_waitcnt vmcnt(2)
; GFX7-NEXT: v_ashrrev_i32_e32 v3, 28, v2
; GFX7-NEXT: v_bfe_i32 v9, v2, 4, 4
; GFX7-NEXT: v_bfe_i32 v2, v2, 0, 4
; GFX7-NEXT: v_lshlrev_b32_e32 v10, 8, v3
-; GFX7-NEXT: v_and_b32_e32 v4, s4, v4
+; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v6
+; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v7
-; GFX7-NEXT: v_and_b32_e32 v8, s4, v8
+; GFX7-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; GFX7-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_ashrrev_i32_e32 v11, 28, v0
; GFX7-NEXT: v_bfe_i32 v12, v0, 24, 4
; GFX7-NEXT: v_or_b32_e32 v6, v8, v7
; GFX7-NEXT: v_or_b32_e32 v2, v2, v9
; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v11
-; GFX7-NEXT: v_and_b32_e32 v8, s4, v12
+; GFX7-NEXT: v_and_b32_e32 v8, 0xff, v12
; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v13
-; GFX7-NEXT: v_and_b32_e32 v10, s4, v14
+; GFX7-NEXT: v_and_b32_e32 v10, 0xff, v14
; GFX7-NEXT: v_lshlrev_b32_e32 v12, 8, v15
-; GFX7-NEXT: v_and_b32_e32 v13, s4, v16
+; GFX7-NEXT: v_and_b32_e32 v13, 0xff, v16
; GFX7-NEXT: v_lshlrev_b32_e32 v14, 8, v17
-; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX7-NEXT: v_and_b32_e32 v5, s5, v5
+; GFX7-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX7-NEXT: v_or_b32_e32 v7, v8, v7
; GFX7-NEXT: v_or_b32_e32 v8, v10, v9
; GFX7-NEXT: v_or_b32_e32 v9, v13, v12
; GFX7-NEXT: v_or_b32_e32 v0, v0, v14
; GFX7-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX7-NEXT: v_and_b32_e32 v2, s5, v2
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-NEXT: v_or_b32_e32 v4, v5, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v7
; GFX7-NEXT: v_lshlrev_b32_e32 v7, 16, v9
-; GFX7-NEXT: v_and_b32_e32 v0, s5, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_or_b32_e32 v2, v2, v6
; GFX7-NEXT: v_or_b32_e32 v0, v0, v7
-; GFX7-NEXT: v_and_b32_e32 v7, s4, v2
-; GFX7-NEXT: v_and_b32_e32 v13, s4, v0
-; GFX7-NEXT: v_and_b32_e32 v6, s5, v8
+; GFX7-NEXT: v_and_b32_e32 v7, 0xff, v2
+; GFX7-NEXT: v_and_b32_e32 v13, 0xff, v0
+; GFX7-NEXT: v_and_b32_e32 v6, 0xffff, v8
; GFX7-NEXT: v_bfe_u32 v8, v2, 8, 8
; GFX7-NEXT: v_bfe_u32 v14, v0, 8, 8
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
; GFX7-NEXT: v_mad_u32_u24 v1, v8, v14, v1
; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1
-; GFX7-NEXT: v_and_b32_e32 v9, s4, v4
-; GFX7-NEXT: v_and_b32_e32 v15, s4, v5
+; GFX7-NEXT: v_and_b32_e32 v9, 0xff, v4
+; GFX7-NEXT: v_and_b32_e32 v15, 0xff, v5
; GFX7-NEXT: v_mad_u32_u24 v0, v6, v12, v0
; GFX7-NEXT: v_bfe_u32 v10, v4, 8, 8
; GFX7-NEXT: v_bfe_u32 v16, v5, 8, 8
; GFX7-NEXT: v_bfe_u32 v4, v4, 16, 8
; GFX7-NEXT: v_bfe_u32 v5, v5, 16, 8
; GFX7-NEXT: v_mad_u32_u24 v0, v10, v16, v0
-; GFX7-NEXT: v_and_b32_e32 v3, s4, v3
-; GFX7-NEXT: v_and_b32_e32 v11, s4, v11
+; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX7-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX7-NEXT: v_mad_u32_u24 v0, v4, v5, v0
; GFX7-NEXT: v_mad_u32_u24 v0, v3, v11, v0
; GFX7-NEXT: buffer_store_byte v0, off, s[0:3], 0
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ushort v1, off, s[0:3], 0
-; GFX7-NEXT: s_mov_b32 s4, 0xf0000
; GFX7-NEXT: s_addc_u32 s13, s13, 0
; GFX7-NEXT: s_waitcnt vmcnt(2)
; GFX7-NEXT: v_bfe_u32 v8, v2, 20, 4
; GFX7-NEXT: v_bfe_u32 v6, v2, 8, 4
; GFX7-NEXT: v_and_b32_e32 v7, 15, v2
; GFX7-NEXT: v_alignbit_b32 v2, v8, v2, 16
-; GFX7-NEXT: v_and_b32_e32 v8, s4, v9
+; GFX7-NEXT: v_and_b32_e32 v8, 0xf0000, v9
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_lshlrev_b32_e32 v9, 12, v0
; GFX7-NEXT: v_and_b32_e32 v14, 15, v0
; GFX7-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX7-NEXT: v_and_b32_e32 v8, s4, v9
+; GFX7-NEXT: v_and_b32_e32 v8, 0xf0000, v9
; GFX7-NEXT: v_or_b32_e32 v8, v14, v8
; GFX7-NEXT: v_lshrrev_b32_e32 v9, 16, v7
; GFX7-NEXT: v_and_b32_e32 v7, 15, v7
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
+; GFX9-NEXT: s_addc_u32 s9, s9, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[4:5]
; GFX9-NEXT: global_load_dword v2, v0, s[6:7]
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: global_load_ushort v3, v0, s[2:3]
-; GFX9-NEXT: s_addc_u32 s9, s9, 0
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_bfe_u32 v5, v1, 4, 4
-; GFX9-NEXT: v_and_b32_e32 v6, 15, v1
-; GFX9-NEXT: v_bfe_u32 v7, v1, 12, 4
-; GFX9-NEXT: v_bfe_u32 v8, v1, 8, 4
-; GFX9-NEXT: v_bfe_u32 v9, v1, 20, 4
-; GFX9-NEXT: v_bfe_u32 v10, v1, 16, 4
-; GFX9-NEXT: v_lshrrev_b32_e32 v11, 28, v1
-; GFX9-NEXT: v_bfe_u32 v1, v1, 24, 4
+; GFX9-NEXT: v_and_b32_e32 v5, 15, v1
+; GFX9-NEXT: v_bfe_u32 v7, v1, 8, 4
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_bfe_u32 v12, v2, 4, 4
-; GFX9-NEXT: v_and_b32_e32 v13, 15, v2
-; GFX9-NEXT: v_bfe_u32 v14, v2, 12, 4
-; GFX9-NEXT: v_bfe_u32 v15, v2, 8, 4
-; GFX9-NEXT: v_bfe_u32 v16, v2, 20, 4
-; GFX9-NEXT: v_bfe_u32 v17, v2, 16, 4
-; GFX9-NEXT: v_lshrrev_b32_e32 v18, 28, v2
+; GFX9-NEXT: v_and_b32_e32 v12, 15, v2
+; GFX9-NEXT: v_bfe_u32 v4, v1, 4, 4
+; GFX9-NEXT: v_bfe_u32 v6, v1, 12, 4
+; GFX9-NEXT: v_bfe_u32 v11, v2, 4, 4
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX9-NEXT: v_bfe_u32 v9, v1, 16, 4
+; GFX9-NEXT: v_bfe_u32 v14, v2, 8, 4
+; GFX9-NEXT: v_lshl_or_b32 v6, v6, 16, v7
+; GFX9-NEXT: v_lshl_or_b32 v7, v11, 16, v12
+; GFX9-NEXT: v_lshl_or_b32 v4, v4, 16, v5
+; GFX9-NEXT: v_bfe_u32 v8, v1, 20, 4
+; GFX9-NEXT: v_bfe_u32 v13, v2, 12, 4
+; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX9-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX9-NEXT: v_pk_mul_lo_u16 v4, v4, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 28, v1
+; GFX9-NEXT: v_bfe_u32 v1, v1, 24, 4
+; GFX9-NEXT: v_bfe_u32 v15, v2, 20, 4
+; GFX9-NEXT: v_bfe_u32 v16, v2, 16, 4
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 28, v2
; GFX9-NEXT: v_bfe_u32 v2, v2, 24, 4
-; GFX9-NEXT: v_and_b32_e32 v2, v4, v2
-; GFX9-NEXT: v_and_b32_e32 v1, v4, v1
-; GFX9-NEXT: v_and_b32_e32 v17, v4, v17
-; GFX9-NEXT: v_and_b32_e32 v10, v4, v10
-; GFX9-NEXT: v_and_b32_e32 v15, v4, v15
-; GFX9-NEXT: v_and_b32_e32 v8, v4, v8
-; GFX9-NEXT: v_and_b32_e32 v13, v4, v13
-; GFX9-NEXT: v_and_b32_e32 v4, v4, v6
-; GFX9-NEXT: v_lshl_or_b32 v7, v7, 16, v8
-; GFX9-NEXT: v_lshl_or_b32 v8, v12, 16, v13
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_pk_mul_lo_u16 v4, v4, v8
-; GFX9-NEXT: v_lshl_or_b32 v9, v9, 16, v10
-; GFX9-NEXT: v_lshl_or_b32 v10, v14, 16, v15
+; GFX9-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX9-NEXT: v_lshl_or_b32 v9, v13, 16, v14
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v3, v4, v3
-; GFX9-NEXT: v_pk_mul_lo_u16 v5, v7, v10
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; GFX9-NEXT: v_pk_mul_lo_u16 v5, v6, v9
; GFX9-NEXT: v_add_u16_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: v_lshl_or_b32 v2, v18, 16, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v11, 16, v1
-; GFX9-NEXT: v_lshl_or_b32 v6, v16, 16, v17
+; GFX9-NEXT: v_lshl_or_b32 v2, v17, 16, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v10, 16, v1
+; GFX9-NEXT: v_lshl_or_b32 v10, v15, 16, v16
; GFX9-NEXT: v_add_u16_e32 v3, v3, v5
; GFX9-NEXT: v_pk_mul_lo_u16 v1, v1, v2
-; GFX9-NEXT: v_pk_mul_lo_u16 v2, v9, v6
+; GFX9-NEXT: v_pk_mul_lo_u16 v2, v8, v10
; GFX9-NEXT: v_add_u16_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-NEXT: v_add_u16_e32 v3, v3, v2
; GFX9-NEXT: v_add_u16_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: v_mov_b32_e32 v4, 0xffff
+; GFX9-DL-NEXT: s_addc_u32 s9, s9, 0
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DL-NEXT: global_load_ushort v3, v0, s[2:3]
-; GFX9-DL-NEXT: s_addc_u32 s9, s9, 0
; GFX9-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX9-DL-NEXT: v_bfe_u32 v5, v1, 4, 4
-; GFX9-DL-NEXT: v_and_b32_e32 v6, 15, v1
-; GFX9-DL-NEXT: v_bfe_u32 v7, v1, 12, 4
-; GFX9-DL-NEXT: v_bfe_u32 v8, v1, 8, 4
-; GFX9-DL-NEXT: v_bfe_u32 v9, v1, 20, 4
-; GFX9-DL-NEXT: v_bfe_u32 v10, v1, 16, 4
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v11, 28, v1
-; GFX9-DL-NEXT: v_bfe_u32 v1, v1, 24, 4
+; GFX9-DL-NEXT: v_and_b32_e32 v5, 15, v1
+; GFX9-DL-NEXT: v_bfe_u32 v7, v1, 8, 4
; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_bfe_u32 v12, v2, 4, 4
-; GFX9-DL-NEXT: v_and_b32_e32 v13, 15, v2
-; GFX9-DL-NEXT: v_bfe_u32 v14, v2, 12, 4
-; GFX9-DL-NEXT: v_bfe_u32 v15, v2, 8, 4
-; GFX9-DL-NEXT: v_bfe_u32 v16, v2, 20, 4
-; GFX9-DL-NEXT: v_bfe_u32 v17, v2, 16, 4
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v18, 28, v2
+; GFX9-DL-NEXT: v_and_b32_e32 v12, 15, v2
+; GFX9-DL-NEXT: v_bfe_u32 v4, v1, 4, 4
+; GFX9-DL-NEXT: v_bfe_u32 v6, v1, 12, 4
+; GFX9-DL-NEXT: v_bfe_u32 v11, v2, 4, 4
+; GFX9-DL-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-DL-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX9-DL-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX9-DL-NEXT: v_bfe_u32 v9, v1, 16, 4
+; GFX9-DL-NEXT: v_bfe_u32 v14, v2, 8, 4
+; GFX9-DL-NEXT: v_lshl_or_b32 v6, v6, 16, v7
+; GFX9-DL-NEXT: v_lshl_or_b32 v7, v11, 16, v12
+; GFX9-DL-NEXT: v_lshl_or_b32 v4, v4, 16, v5
+; GFX9-DL-NEXT: v_bfe_u32 v8, v1, 20, 4
+; GFX9-DL-NEXT: v_bfe_u32 v13, v2, 12, 4
+; GFX9-DL-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX9-DL-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX9-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v7
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v10, 28, v1
+; GFX9-DL-NEXT: v_bfe_u32 v1, v1, 24, 4
+; GFX9-DL-NEXT: v_bfe_u32 v15, v2, 20, 4
+; GFX9-DL-NEXT: v_bfe_u32 v16, v2, 16, 4
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v17, 28, v2
; GFX9-DL-NEXT: v_bfe_u32 v2, v2, 24, 4
-; GFX9-DL-NEXT: v_and_b32_e32 v2, v4, v2
-; GFX9-DL-NEXT: v_and_b32_e32 v1, v4, v1
-; GFX9-DL-NEXT: v_and_b32_e32 v17, v4, v17
-; GFX9-DL-NEXT: v_and_b32_e32 v10, v4, v10
-; GFX9-DL-NEXT: v_and_b32_e32 v15, v4, v15
-; GFX9-DL-NEXT: v_and_b32_e32 v8, v4, v8
-; GFX9-DL-NEXT: v_and_b32_e32 v13, v4, v13
-; GFX9-DL-NEXT: v_and_b32_e32 v4, v4, v6
-; GFX9-DL-NEXT: v_lshl_or_b32 v7, v7, 16, v8
-; GFX9-DL-NEXT: v_lshl_or_b32 v8, v12, 16, v13
-; GFX9-DL-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v8
-; GFX9-DL-NEXT: v_lshl_or_b32 v9, v9, 16, v10
-; GFX9-DL-NEXT: v_lshl_or_b32 v10, v14, 16, v15
+; GFX9-DL-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX9-DL-NEXT: v_lshl_or_b32 v9, v13, 16, v14
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_add_u16_e32 v3, v4, v3
-; GFX9-DL-NEXT: v_pk_mul_lo_u16 v5, v7, v10
+; GFX9-DL-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-DL-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-DL-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; GFX9-DL-NEXT: v_pk_mul_lo_u16 v5, v6, v9
; GFX9-DL-NEXT: v_add_u16_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-DL-NEXT: v_lshl_or_b32 v2, v18, 16, v2
-; GFX9-DL-NEXT: v_lshl_or_b32 v1, v11, 16, v1
-; GFX9-DL-NEXT: v_lshl_or_b32 v6, v16, 16, v17
+; GFX9-DL-NEXT: v_lshl_or_b32 v2, v17, 16, v2
+; GFX9-DL-NEXT: v_lshl_or_b32 v1, v10, 16, v1
+; GFX9-DL-NEXT: v_lshl_or_b32 v10, v15, 16, v16
; GFX9-DL-NEXT: v_add_u16_e32 v3, v3, v5
; GFX9-DL-NEXT: v_pk_mul_lo_u16 v1, v1, v2
-; GFX9-DL-NEXT: v_pk_mul_lo_u16 v2, v9, v6
+; GFX9-DL-NEXT: v_pk_mul_lo_u16 v2, v8, v10
; GFX9-DL-NEXT: v_add_u16_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-DL-NEXT: v_add_u16_e32 v3, v3, v2
; GFX9-DL-NEXT: v_add_u16_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: buffer_load_ubyte v1, off, s[0:3], 0
-; GFX7-NEXT: s_movk_i32 s4, 0xf00
-; GFX7-NEXT: s_movk_i32 s5, 0xf0f
; GFX7-NEXT: s_addc_u32 s13, s13, 0
; GFX7-NEXT: s_waitcnt vmcnt(2)
; GFX7-NEXT: v_lshrrev_b32_e32 v4, 4, v2
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_lshrrev_b32_e32 v11, 4, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v13, 28, v0
-; GFX7-NEXT: v_and_b32_e32 v8, s4, v8
-; GFX7-NEXT: v_and_b32_e32 v4, s4, v4
+; GFX7-NEXT: v_and_b32_e32 v8, 0xf00, v8
+; GFX7-NEXT: v_and_b32_e32 v4, 0xf00, v4
; GFX7-NEXT: v_and_b32_e32 v5, 15, v2
; GFX7-NEXT: v_bfe_u32 v10, v0, 8, 4
; GFX7-NEXT: v_and_b32_e32 v12, 15, v0
; GFX7-NEXT: v_bfe_u32 v14, v0, 16, 4
; GFX7-NEXT: v_lshrrev_b32_e32 v15, 12, v0
; GFX7-NEXT: v_alignbit_b32 v2, v6, v2, 24
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v9
+; GFX7-NEXT: v_and_b32_e32 v6, 0xf00, v9
; GFX7-NEXT: v_lshlrev_b32_e32 v9, 4, v0
; GFX7-NEXT: v_or_b32_e32 v7, v7, v8
; GFX7-NEXT: v_or_b32_e32 v3, v3, v4
; GFX7-NEXT: v_alignbit_b32 v0, v13, v0, 24
-; GFX7-NEXT: v_and_b32_e32 v8, s4, v11
+; GFX7-NEXT: v_and_b32_e32 v8, 0xf00, v11
; GFX7-NEXT: v_or_b32_e32 v5, v5, v6
-; GFX7-NEXT: v_and_b32_e32 v4, s4, v15
-; GFX7-NEXT: v_and_b32_e32 v6, s4, v9
+; GFX7-NEXT: v_and_b32_e32 v4, 0xf00, v15
+; GFX7-NEXT: v_and_b32_e32 v6, 0xf00, v9
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX7-NEXT: v_and_b32_e32 v0, s5, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xf0f, v0
; GFX7-NEXT: v_or_b32_e32 v8, v10, v8
-; GFX7-NEXT: v_and_b32_e32 v2, s5, v2
+; GFX7-NEXT: v_and_b32_e32 v2, 0xf0f, v2
; GFX7-NEXT: v_or_b32_e32 v4, v14, v4
; GFX7-NEXT: v_or_b32_e32 v6, v12, v6
; GFX7-NEXT: v_or_b32_e32 v3, v5, v3
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
+; GFX9-NEXT: s_addc_u32 s9, s9, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[4:5]
; GFX9-NEXT: global_load_dword v2, v0, s[6:7]
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: global_load_ubyte v3, v0, s[2:3]
-; GFX9-NEXT: s_addc_u32 s9, s9, 0
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_bfe_u32 v5, v1, 4, 4
-; GFX9-NEXT: v_and_b32_e32 v6, 15, v1
-; GFX9-NEXT: v_bfe_u32 v7, v1, 12, 4
-; GFX9-NEXT: v_bfe_u32 v8, v1, 8, 4
-; GFX9-NEXT: v_bfe_u32 v9, v1, 20, 4
-; GFX9-NEXT: v_bfe_u32 v10, v1, 16, 4
-; GFX9-NEXT: v_lshrrev_b32_e32 v11, 28, v1
-; GFX9-NEXT: v_bfe_u32 v1, v1, 24, 4
+; GFX9-NEXT: v_and_b32_e32 v5, 15, v1
+; GFX9-NEXT: v_bfe_u32 v7, v1, 8, 4
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_bfe_u32 v12, v2, 4, 4
-; GFX9-NEXT: v_and_b32_e32 v13, 15, v2
-; GFX9-NEXT: v_bfe_u32 v14, v2, 12, 4
-; GFX9-NEXT: v_bfe_u32 v15, v2, 8, 4
-; GFX9-NEXT: v_bfe_u32 v16, v2, 20, 4
-; GFX9-NEXT: v_bfe_u32 v17, v2, 16, 4
-; GFX9-NEXT: v_lshrrev_b32_e32 v18, 28, v2
+; GFX9-NEXT: v_and_b32_e32 v12, 15, v2
+; GFX9-NEXT: v_bfe_u32 v4, v1, 4, 4
+; GFX9-NEXT: v_bfe_u32 v6, v1, 12, 4
+; GFX9-NEXT: v_bfe_u32 v11, v2, 4, 4
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX9-NEXT: v_bfe_u32 v9, v1, 16, 4
+; GFX9-NEXT: v_bfe_u32 v14, v2, 8, 4
+; GFX9-NEXT: v_lshl_or_b32 v6, v6, 16, v7
+; GFX9-NEXT: v_lshl_or_b32 v7, v11, 16, v12
+; GFX9-NEXT: v_lshl_or_b32 v4, v4, 16, v5
+; GFX9-NEXT: v_bfe_u32 v8, v1, 20, 4
+; GFX9-NEXT: v_bfe_u32 v13, v2, 12, 4
+; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX9-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX9-NEXT: v_pk_mul_lo_u16 v4, v4, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 28, v1
+; GFX9-NEXT: v_bfe_u32 v1, v1, 24, 4
+; GFX9-NEXT: v_bfe_u32 v15, v2, 20, 4
+; GFX9-NEXT: v_bfe_u32 v16, v2, 16, 4
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 28, v2
; GFX9-NEXT: v_bfe_u32 v2, v2, 24, 4
-; GFX9-NEXT: v_and_b32_e32 v2, v4, v2
-; GFX9-NEXT: v_and_b32_e32 v1, v4, v1
-; GFX9-NEXT: v_and_b32_e32 v17, v4, v17
-; GFX9-NEXT: v_and_b32_e32 v10, v4, v10
-; GFX9-NEXT: v_and_b32_e32 v15, v4, v15
-; GFX9-NEXT: v_and_b32_e32 v8, v4, v8
-; GFX9-NEXT: v_and_b32_e32 v13, v4, v13
-; GFX9-NEXT: v_and_b32_e32 v4, v4, v6
-; GFX9-NEXT: v_lshl_or_b32 v7, v7, 16, v8
-; GFX9-NEXT: v_lshl_or_b32 v8, v12, 16, v13
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_pk_mul_lo_u16 v4, v4, v8
-; GFX9-NEXT: v_lshl_or_b32 v9, v9, 16, v10
-; GFX9-NEXT: v_lshl_or_b32 v10, v14, 16, v15
+; GFX9-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX9-NEXT: v_lshl_or_b32 v9, v13, 16, v14
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v3, v4, v3
-; GFX9-NEXT: v_pk_mul_lo_u16 v5, v7, v10
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; GFX9-NEXT: v_pk_mul_lo_u16 v5, v6, v9
; GFX9-NEXT: v_add_u16_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: v_lshl_or_b32 v2, v18, 16, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v11, 16, v1
-; GFX9-NEXT: v_lshl_or_b32 v6, v16, 16, v17
+; GFX9-NEXT: v_lshl_or_b32 v2, v17, 16, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v10, 16, v1
+; GFX9-NEXT: v_lshl_or_b32 v10, v15, 16, v16
; GFX9-NEXT: v_add_u16_e32 v3, v3, v5
; GFX9-NEXT: v_pk_mul_lo_u16 v1, v1, v2
-; GFX9-NEXT: v_pk_mul_lo_u16 v2, v9, v6
+; GFX9-NEXT: v_pk_mul_lo_u16 v2, v8, v10
; GFX9-NEXT: v_add_u16_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-NEXT: v_add_u16_e32 v3, v3, v2
; GFX9-NEXT: v_add_u16_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: v_mov_b32_e32 v4, 0xffff
+; GFX9-DL-NEXT: s_addc_u32 s9, s9, 0
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DL-NEXT: global_load_ubyte v3, v0, s[2:3]
-; GFX9-DL-NEXT: s_addc_u32 s9, s9, 0
; GFX9-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX9-DL-NEXT: v_bfe_u32 v5, v1, 4, 4
-; GFX9-DL-NEXT: v_and_b32_e32 v6, 15, v1
-; GFX9-DL-NEXT: v_bfe_u32 v7, v1, 12, 4
-; GFX9-DL-NEXT: v_bfe_u32 v8, v1, 8, 4
-; GFX9-DL-NEXT: v_bfe_u32 v9, v1, 20, 4
-; GFX9-DL-NEXT: v_bfe_u32 v10, v1, 16, 4
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v11, 28, v1
-; GFX9-DL-NEXT: v_bfe_u32 v1, v1, 24, 4
+; GFX9-DL-NEXT: v_and_b32_e32 v5, 15, v1
+; GFX9-DL-NEXT: v_bfe_u32 v7, v1, 8, 4
; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_bfe_u32 v12, v2, 4, 4
-; GFX9-DL-NEXT: v_and_b32_e32 v13, 15, v2
-; GFX9-DL-NEXT: v_bfe_u32 v14, v2, 12, 4
-; GFX9-DL-NEXT: v_bfe_u32 v15, v2, 8, 4
-; GFX9-DL-NEXT: v_bfe_u32 v16, v2, 20, 4
-; GFX9-DL-NEXT: v_bfe_u32 v17, v2, 16, 4
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v18, 28, v2
+; GFX9-DL-NEXT: v_and_b32_e32 v12, 15, v2
+; GFX9-DL-NEXT: v_bfe_u32 v4, v1, 4, 4
+; GFX9-DL-NEXT: v_bfe_u32 v6, v1, 12, 4
+; GFX9-DL-NEXT: v_bfe_u32 v11, v2, 4, 4
+; GFX9-DL-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-DL-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX9-DL-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX9-DL-NEXT: v_bfe_u32 v9, v1, 16, 4
+; GFX9-DL-NEXT: v_bfe_u32 v14, v2, 8, 4
+; GFX9-DL-NEXT: v_lshl_or_b32 v6, v6, 16, v7
+; GFX9-DL-NEXT: v_lshl_or_b32 v7, v11, 16, v12
+; GFX9-DL-NEXT: v_lshl_or_b32 v4, v4, 16, v5
+; GFX9-DL-NEXT: v_bfe_u32 v8, v1, 20, 4
+; GFX9-DL-NEXT: v_bfe_u32 v13, v2, 12, 4
+; GFX9-DL-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX9-DL-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX9-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v7
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v10, 28, v1
+; GFX9-DL-NEXT: v_bfe_u32 v1, v1, 24, 4
+; GFX9-DL-NEXT: v_bfe_u32 v15, v2, 20, 4
+; GFX9-DL-NEXT: v_bfe_u32 v16, v2, 16, 4
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v17, 28, v2
; GFX9-DL-NEXT: v_bfe_u32 v2, v2, 24, 4
-; GFX9-DL-NEXT: v_and_b32_e32 v2, v4, v2
-; GFX9-DL-NEXT: v_and_b32_e32 v1, v4, v1
-; GFX9-DL-NEXT: v_and_b32_e32 v17, v4, v17
-; GFX9-DL-NEXT: v_and_b32_e32 v10, v4, v10
-; GFX9-DL-NEXT: v_and_b32_e32 v15, v4, v15
-; GFX9-DL-NEXT: v_and_b32_e32 v8, v4, v8
-; GFX9-DL-NEXT: v_and_b32_e32 v13, v4, v13
-; GFX9-DL-NEXT: v_and_b32_e32 v4, v4, v6
-; GFX9-DL-NEXT: v_lshl_or_b32 v7, v7, 16, v8
-; GFX9-DL-NEXT: v_lshl_or_b32 v8, v12, 16, v13
-; GFX9-DL-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v8
-; GFX9-DL-NEXT: v_lshl_or_b32 v9, v9, 16, v10
-; GFX9-DL-NEXT: v_lshl_or_b32 v10, v14, 16, v15
+; GFX9-DL-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX9-DL-NEXT: v_lshl_or_b32 v9, v13, 16, v14
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_add_u16_e32 v3, v4, v3
-; GFX9-DL-NEXT: v_pk_mul_lo_u16 v5, v7, v10
+; GFX9-DL-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-DL-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-DL-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; GFX9-DL-NEXT: v_pk_mul_lo_u16 v5, v6, v9
; GFX9-DL-NEXT: v_add_u16_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-DL-NEXT: v_lshl_or_b32 v2, v18, 16, v2
-; GFX9-DL-NEXT: v_lshl_or_b32 v1, v11, 16, v1
-; GFX9-DL-NEXT: v_lshl_or_b32 v6, v16, 16, v17
+; GFX9-DL-NEXT: v_lshl_or_b32 v2, v17, 16, v2
+; GFX9-DL-NEXT: v_lshl_or_b32 v1, v10, 16, v1
+; GFX9-DL-NEXT: v_lshl_or_b32 v10, v15, 16, v16
; GFX9-DL-NEXT: v_add_u16_e32 v3, v3, v5
; GFX9-DL-NEXT: v_pk_mul_lo_u16 v1, v1, v2
-; GFX9-DL-NEXT: v_pk_mul_lo_u16 v2, v9, v6
+; GFX9-DL-NEXT: v_pk_mul_lo_u16 v2, v8, v10
; GFX9-DL-NEXT: v_add_u16_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-DL-NEXT: v_add_u16_e32 v3, v3, v2
; GFX9-DL-NEXT: v_add_u16_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; SI-NEXT: v_mov_b32_e32 v1, s4
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
-; SI-NEXT: s_movk_i32 s4, 0xff
-; SI-NEXT: s_lshr_b32 s5, s11, 8
+; SI-NEXT: s_lshr_b32 s4, s11, 8
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; SI-NEXT: v_and_b32_e32 v1, s4, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: s_cmp_lg_u32 s6, 13
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_mov_b32_e32 v1, s5
+; SI-NEXT: v_mov_b32_e32 v1, s4
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_cmp_lg_u32 s6, 12
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; SI-NEXT: v_and_b32_e32 v2, s4, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: s_mov_b32 s5, 0xffff
-; SI-NEXT: s_lshr_b32 s7, s10, 24
+; SI-NEXT: s_lshr_b32 s4, s10, 24
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_and_b32_e32 v1, s5, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_cmp_lg_u32 s6, 11
; SI-NEXT: v_or_b32_e32 v3, v1, v0
-; SI-NEXT: v_mov_b32_e32 v0, s7
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: s_cselect_b64 vcc, -1, 0
-; SI-NEXT: s_lshr_b32 s7, s10, 16
+; SI-NEXT: s_lshr_b32 s4, s10, 16
; SI-NEXT: s_cmp_lg_u32 s6, 10
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
-; SI-NEXT: v_mov_b32_e32 v1, s7
+; SI-NEXT: v_mov_b32_e32 v1, s4
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
-; SI-NEXT: s_lshr_b32 s7, s10, 8
+; SI-NEXT: s_lshr_b32 s4, s10, 8
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; SI-NEXT: v_and_b32_e32 v1, s4, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: s_cmp_lg_u32 s6, 9
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_mov_b32_e32 v1, s7
+; SI-NEXT: v_mov_b32_e32 v1, s4
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_cmp_lg_u32 s6, 8
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; SI-NEXT: v_and_b32_e32 v2, s4, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: s_lshr_b32 s7, s9, 24
+; SI-NEXT: s_lshr_b32 s4, s9, 24
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_and_b32_e32 v1, s5, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_cmp_lg_u32 s6, 7
; SI-NEXT: v_or_b32_e32 v2, v1, v0
-; SI-NEXT: v_mov_b32_e32 v0, s7
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: s_cselect_b64 vcc, -1, 0
-; SI-NEXT: s_lshr_b32 s7, s9, 16
+; SI-NEXT: s_lshr_b32 s4, s9, 16
; SI-NEXT: s_cmp_lg_u32 s6, 6
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
-; SI-NEXT: v_mov_b32_e32 v1, s7
+; SI-NEXT: v_mov_b32_e32 v1, s4
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
-; SI-NEXT: s_lshr_b32 s7, s9, 8
+; SI-NEXT: s_lshr_b32 s4, s9, 8
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; SI-NEXT: v_and_b32_e32 v1, s4, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: s_cmp_lg_u32 s6, 5
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_mov_b32_e32 v1, s7
+; SI-NEXT: v_mov_b32_e32 v1, s4
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_cmp_lg_u32 s6, 4
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; SI-NEXT: v_and_b32_e32 v4, s4, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_or_b32_e32 v1, v4, v1
-; SI-NEXT: s_lshr_b32 s7, s8, 24
+; SI-NEXT: s_lshr_b32 s4, s8, 24
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_and_b32_e32 v1, s5, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_cmp_lg_u32 s6, 3
; SI-NEXT: v_or_b32_e32 v1, v1, v0
-; SI-NEXT: v_mov_b32_e32 v0, s7
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: s_cselect_b64 vcc, -1, 0
-; SI-NEXT: s_lshr_b32 s7, s8, 16
+; SI-NEXT: s_lshr_b32 s4, s8, 16
; SI-NEXT: s_cmp_lg_u32 s6, 2
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
-; SI-NEXT: v_mov_b32_e32 v4, s7
+; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
-; SI-NEXT: s_lshr_b32 s7, s8, 8
+; SI-NEXT: s_lshr_b32 s4, s8, 8
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; SI-NEXT: v_and_b32_e32 v4, s4, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: s_cmp_lg_u32 s6, 1
; SI-NEXT: v_or_b32_e32 v0, v4, v0
-; SI-NEXT: v_mov_b32_e32 v4, s7
+; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_cmp_lg_u32 s6, 0
; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v5, 5, v5, vcc
; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; SI-NEXT: v_and_b32_e32 v5, s4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_and_b32_e32 v4, s5, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v0, v4, v0
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 4, v0
-; GFX9-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx4 v[0:3], v4, s[2:3]
; GFX9-NEXT: s_cmp_eq_u32 s7, 7
-; GFX9-NEXT: v_mov_b32_e32 v6, s6
+; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
; GFX9-NEXT: s_cmp_eq_u32 s7, 6
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v5, vcc
; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
; GFX9-NEXT: s_cmp_eq_u32 s7, 5
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
; GFX9-NEXT: s_cmp_eq_u32 s7, 4
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v5, vcc
; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
; GFX9-NEXT: s_cmp_eq_u32 s7, 3
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v3, v5, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
; GFX9-NEXT: s_cmp_eq_u32 s7, 2
-; GFX9-NEXT: v_lshl_or_b32 v3, v7, 16, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v6, vcc
+; GFX9-NEXT: v_lshl_or_b32 v3, v6, 16, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v8, v5, vcc
; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
; GFX9-NEXT: s_cmp_eq_u32 s7, 1
-; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX9-NEXT: v_and_b32_e32 v2, v5, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
; GFX9-NEXT: s_cmp_eq_u32 s7, 0
-; GFX9-NEXT: v_lshl_or_b32 v2, v8, 16, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v10, v6, vcc
+; GFX9-NEXT: v_lshl_or_b32 v2, v7, 16, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v5, vcc
; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
-; GFX9-NEXT: v_and_b32_e32 v1, v5, v1
-; GFX9-NEXT: v_and_b32_e32 v0, v5, v0
-; GFX9-NEXT: v_lshl_or_b32 v1, v7, 16, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v8, 16, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v6, 16, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v7, 16, v0
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm
;
define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {
; GFX9-LABEL: sample_d_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: v_mov_b32_e32 v6, 0xffff
-; GFX9-NEXT: v_and_b32_e32 v4, v6, v4
-; GFX9-NEXT: v_and_b32_e32 v2, v6, v2
-; GFX9-NEXT: v_and_b32_e32 v0, v6, v0
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v2
; GFX9-NEXT: v_lshl_or_b32 v2, v1, 16, v0
; GFX9: ; %bb.0: ; %main_body
; GFX9-NEXT: v_mov_b32_e32 v12, v8
; GFX9-NEXT: v_mov_b32_e32 v8, v2
-; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v6
+; GFX9-NEXT: v_lshl_or_b32 v11, v7, 16, v2
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v3
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: v_mov_b32_e32 v10, v5
-; GFX9-NEXT: v_and_b32_e32 v5, v2, v6
-; GFX9-NEXT: v_and_b32_e32 v3, v2, v3
-; GFX9-NEXT: v_and_b32_e32 v0, v2, v0
-; GFX9-NEXT: v_lshl_or_b32 v11, v7, 16, v5
-; GFX9-NEXT: v_lshl_or_b32 v9, v4, 16, v3
+; GFX9-NEXT: v_lshl_or_b32 v9, v4, 16, v2
; GFX9-NEXT: v_lshl_or_b32 v7, v1, 16, v0
; GFX9-NEXT: image_sample_d v[0:3], v[7:12], s[0:7], s[8:11] dmask:0xf a16
; GFX9-NEXT: s_waitcnt vmcnt(0)
define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {
; GFX9-LABEL: sample_c_d_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: v_mov_b32_e32 v9, 0xffff
; GFX9-NEXT: v_mov_b32_e32 v7, v3
; GFX9-NEXT: v_mov_b32_e32 v8, v2
-; GFX9-NEXT: v_and_b32_e32 v2, v9, v5
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v5
; GFX9-NEXT: v_lshl_or_b32 v3, v6, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v2, v9, v7
-; GFX9-NEXT: v_and_b32_e32 v1, v9, v1
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v7
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX9-NEXT: v_lshl_or_b32 v1, v8, 16, v1
; GFX9-NEXT: image_sample_c_d v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16
define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {
; GFX9-LABEL: sample_d_cl_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: v_mov_b32_e32 v7, 0xffff
-; GFX9-NEXT: v_and_b32_e32 v4, v7, v4
-; GFX9-NEXT: v_and_b32_e32 v2, v7, v2
-; GFX9-NEXT: v_and_b32_e32 v0, v7, v0
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: v_lshl_or_b32 v5, v5, 16, v4
; GFX9-NEXT: v_lshl_or_b32 v4, v3, 16, v2
; GFX9-NEXT: v_lshl_or_b32 v3, v1, 16, v0
; GFX9: ; %bb.0: ; %main_body
; GFX9-NEXT: v_mov_b32_e32 v11, v7
; GFX9-NEXT: v_mov_b32_e32 v7, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, 0xffff
-; GFX9-NEXT: v_and_b32_e32 v5, v0, v5
-; GFX9-NEXT: v_and_b32_e32 v3, v0, v3
-; GFX9-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_lshl_or_b32 v10, v6, 16, v5
-; GFX9-NEXT: v_lshl_or_b32 v9, v4, 16, v3
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v5
+; GFX9-NEXT: v_lshl_or_b32 v10, v6, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v3
+; GFX9-NEXT: v_lshl_or_b32 v9, v4, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v1
; GFX9-NEXT: v_lshl_or_b32 v8, v2, 16, v0
; GFX9-NEXT: image_sample_c_d_cl v[0:3], v[7:11], s[0:7], s[8:11] dmask:0xf a16
; GFX9-NEXT: s_waitcnt vmcnt(0)
define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {
; GFX9-LABEL: sample_cd_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: v_mov_b32_e32 v6, 0xffff
-; GFX9-NEXT: v_and_b32_e32 v4, v6, v4
-; GFX9-NEXT: v_and_b32_e32 v2, v6, v2
-; GFX9-NEXT: v_and_b32_e32 v0, v6, v0
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v2
; GFX9-NEXT: v_lshl_or_b32 v2, v1, 16, v0
define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {
; GFX9-LABEL: sample_c_cd_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: v_mov_b32_e32 v9, 0xffff
; GFX9-NEXT: v_mov_b32_e32 v7, v3
; GFX9-NEXT: v_mov_b32_e32 v8, v2
-; GFX9-NEXT: v_and_b32_e32 v2, v9, v5
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v5
; GFX9-NEXT: v_lshl_or_b32 v3, v6, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v2, v9, v7
-; GFX9-NEXT: v_and_b32_e32 v1, v9, v1
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v7
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX9-NEXT: v_lshl_or_b32 v1, v8, 16, v1
; GFX9-NEXT: image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16
define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {
; GFX9-LABEL: sample_cd_cl_2d:
; GFX9: ; %bb.0: ; %main_body
-; GFX9-NEXT: v_mov_b32_e32 v7, 0xffff
-; GFX9-NEXT: v_and_b32_e32 v4, v7, v4
-; GFX9-NEXT: v_and_b32_e32 v2, v7, v2
-; GFX9-NEXT: v_and_b32_e32 v0, v7, v0
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: v_lshl_or_b32 v5, v5, 16, v4
; GFX9-NEXT: v_lshl_or_b32 v4, v3, 16, v2
; GFX9-NEXT: v_lshl_or_b32 v3, v1, 16, v0
; GFX9: ; %bb.0: ; %main_body
; GFX9-NEXT: v_mov_b32_e32 v11, v7
; GFX9-NEXT: v_mov_b32_e32 v7, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, 0xffff
-; GFX9-NEXT: v_and_b32_e32 v5, v0, v5
-; GFX9-NEXT: v_and_b32_e32 v3, v0, v3
-; GFX9-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_lshl_or_b32 v10, v6, 16, v5
-; GFX9-NEXT: v_lshl_or_b32 v9, v4, 16, v3
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v5
+; GFX9-NEXT: v_lshl_or_b32 v10, v6, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v3
+; GFX9-NEXT: v_lshl_or_b32 v9, v4, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v1
; GFX9-NEXT: v_lshl_or_b32 v8, v2, 16, v0
; GFX9-NEXT: image_sample_c_cd_cl v[0:3], v[7:11], s[0:7], s[8:11] dmask:0xf a16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9: ; %bb.0: ; %main_body
; GFX9-NEXT: v_mov_b32_e32 v13, v8
; GFX9-NEXT: v_mov_b32_e32 v8, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, 0xffff
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v6
+; GFX9-NEXT: v_lshl_or_b32 v12, v7, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v4
+; GFX9-NEXT: v_lshl_or_b32 v11, v5, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v2
; GFX9-NEXT: v_mov_b32_e32 v9, v1
-; GFX9-NEXT: v_and_b32_e32 v1, v0, v6
-; GFX9-NEXT: v_lshl_or_b32 v12, v7, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v1, v0, v4
-; GFX9-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX9-NEXT: v_lshl_or_b32 v11, v5, 16, v1
; GFX9-NEXT: v_lshl_or_b32 v10, v3, 16, v0
; GFX9-NEXT: image_sample_c_d_o v0, v[8:13], s[0:7], s[8:11] dmask:0x4 a16 da
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9: ; %bb.0: ; %main_body
; GFX9-NEXT: v_mov_b32_e32 v13, v8
; GFX9-NEXT: v_mov_b32_e32 v8, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, 0xffff
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v6
+; GFX9-NEXT: v_lshl_or_b32 v12, v7, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v4
+; GFX9-NEXT: v_lshl_or_b32 v11, v5, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v2
; GFX9-NEXT: v_mov_b32_e32 v9, v1
-; GFX9-NEXT: v_and_b32_e32 v1, v0, v6
-; GFX9-NEXT: v_lshl_or_b32 v12, v7, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v1, v0, v4
-; GFX9-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX9-NEXT: v_lshl_or_b32 v11, v5, 16, v1
; GFX9-NEXT: v_lshl_or_b32 v10, v3, 16, v0
; GFX9-NEXT: image_sample_c_d_o v[0:1], v[8:13], s[0:7], s[8:11] dmask:0x6 a16 da
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_mov_b32 s8, s2
; GFX6-NEXT: s_mov_b32 s9, s3
; GFX6-NEXT: buffer_load_dword v0, off, s[8:11], 0
-; GFX6-NEXT: s_mov_b32 s2, 0x3e22f983
; GFX6-NEXT: s_mov_b32 s4, s0
; GFX6-NEXT: s_mov_b32 s5, s1
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, s2, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x3e22f983, v1
; GFX6-NEXT: v_fract_f32_e32 v1, v1
-; GFX6-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x3e22f983, v0
; GFX6-NEXT: v_fract_f32_e32 v0, v0
; GFX6-NEXT: v_cos_f32_e32 v0, v0
; GFX6-NEXT: v_cos_f32_e32 v1, v1
; SI: buffer_load_dword v[[A_F16_0:[0-9]+]]
; VI: flat_load_dword v[[A_F16_0:[0-9]+]]
; GFX9: global_load_dword v[[A_F16_0:[0-9]+]]
-; SI: s_mov_b32 [[A_F32_2:s[0-9]+]], 0x3f317218
-; GFX9: s_movk_i32 [[A_F32_2:s[0-9]+]], 0x398c
; VI: v_mov_b32_e32 [[A_F32_2_V:v[0-9]+]], 0x398c
; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_F16_0]]
; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_1]]
; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_0]]
; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
; SI: v_log_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]]
-; SI: v_mul_f32_e32 v[[R_F32_5:[0-9]+]], [[A_F32_2]], v[[R_F32_0]]
+; SI: v_mul_f32_e32 v[[R_F32_5:[0-9]+]], 0x3f317218, v[[R_F32_0]]
; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_5]]
-; SI: v_mul_f32_e32 v[[R_F32_6:[0-9]+]], [[A_F32_2]], v[[R_F32_1]]
+; SI: v_mul_f32_e32 v[[R_F32_6:[0-9]+]], 0x3f317218, v[[R_F32_1]]
; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_6]]
; GFX9: v_log_f16_e32 v[[R_F16_2:[0-9]+]], v[[A_F16_0]]
; VIGFX9: v_log_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; VI: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
; VI: v_mul_f16_sdwa v[[R_F16_2:[0-9]+]], v[[R_F16_1]], [[A_F32_2_V]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9: v_mul_f16_e32 v[[R_F32_3:[0-9]+]], [[A_F32_2]], v[[R_F16_2]]
-; VI: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], 0x398c, v[[R_F16_0]]
-; GFX9: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], [[A_F32_2]], v[[R_F16_0]]
+; GFX9: v_mul_f16_e32 v[[R_F32_3:[0-9]+]], 0x398c, v[[R_F16_2]]
+; VIGFX9: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], 0x398c, v[[R_F16_0]]
; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_0]]
; SI-NOT: v_and_b32_e32
; SI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_1]], v[[R_F16_0]]
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
-; GCN-DAG: s_mov_b32 [[R_F32_LOG_CONST:s[0-9]+]], 0x3f317218
; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3f317218, v{{[0-9]+}}
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3f317218, v{{[0-9]+}}
define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
entry:
%res = call <2 x float> @llvm.log.v2f32(<2 x float> %in)
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
-; GCN-DAG: s_mov_b32 [[R_F32_LOG_CONST:s[0-9]+]], 0x3f317218
; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3f317218, v{{[0-9]+}}
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3f317218, v{{[0-9]+}}
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3f317218, v{{[0-9]+}}
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3f317218, v{{[0-9]+}}
define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
entry:
%res = call <4 x float> @llvm.log.v4f32(<4 x float> %in)
; SI: buffer_load_dword v[[A_F16_0:[0-9]+]]
; VI: flat_load_dword v[[A_F16_0:[0-9]+]]
; GFX9: global_load_dword v[[A_F16_0:[0-9]+]]
-; SI: s_mov_b32 [[A_F32_2:s[0-9]+]], 0x3e9a209a
-; GFX9: s_movk_i32 [[A_F32_2:s[0-9]+]], 0x34d1
; VI: v_mov_b32_e32 [[A_F32_2_V:v[0-9]+]], 0x34d1
; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_F16_0]]
; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_1]]
; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_0]]
; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
; SI: v_log_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]]
-; SI: v_mul_f32_e32 v[[R_F32_5:[0-9]+]], [[A_F32_2]], v[[R_F32_0]]
+; SI: v_mul_f32_e32 v[[R_F32_5:[0-9]+]], 0x3e9a209a, v[[R_F32_0]]
; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_5]]
-; SI: v_mul_f32_e32 v[[R_F32_6:[0-9]+]], [[A_F32_2]], v[[R_F32_1]]
+; SI: v_mul_f32_e32 v[[R_F32_6:[0-9]+]], 0x3e9a209a, v[[R_F32_1]]
; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_6]]
; GFX9: v_log_f16_e32 v[[R_F16_2:[0-9]+]], v[[A_F16_0]]
; VIGFX9: v_log_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; VI: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
; VI: v_mul_f16_sdwa v[[R_F16_2:[0-9]+]], v[[R_F16_1]], [[A_F32_2_V]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI: v_mul_f16_e32 v[[R_F32_3:[0-9]+]], 0x34d1, v[[R_F16_0]]
-; GFX9: v_mul_f16_e32 v[[R_F32_3:[0-9]+]], [[A_F32_2]], v[[R_F16_2]]
-; GFX9: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], [[A_F32_2]], v[[R_F16_0]]
+; GFX9: v_mul_f16_e32 v[[R_F32_3:[0-9]+]], 0x34d1, v[[R_F16_2]]
+; GFX9: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], 0x34d1, v[[R_F16_0]]
; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_0]]
; SI-NOT: v_and_b32_e32
; SI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_1]], v[[R_F16_0]]
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
-; GCN-DAG: s_mov_b32 [[R_F32_LOG_CONST:s[0-9]+]], 0x3e9a209a
; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3e9a209a, v{{[0-9]+}}
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3e9a209a, v{{[0-9]+}}
define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
entry:
%res = call <2 x float> @llvm.log10.v2f32(<2 x float> %in)
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
-; GCN-DAG: s_mov_b32 [[R_F32_LOG_CONST:s[0-9]+]], 0x3e9a209a
; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3e9a209a, v{{[0-9]+}}
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3e9a209a, v{{[0-9]+}}
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3e9a209a, v{{[0-9]+}}
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3e9a209a, v{{[0-9]+}}
define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
entry:
%res = call <4 x float> @llvm.log10.v4f32(<4 x float> %in)
; GFX6-NEXT: s_mov_b32 s8, s2
; GFX6-NEXT: s_mov_b32 s9, s3
; GFX6-NEXT: buffer_load_dword v0, off, s[8:11], 0
-; GFX6-NEXT: s_mov_b32 s2, 0x3e22f983
; GFX6-NEXT: s_mov_b32 s4, s0
; GFX6-NEXT: s_mov_b32 s5, s1
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, s2, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x3e22f983, v1
; GFX6-NEXT: v_fract_f32_e32 v1, v1
-; GFX6-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x3e22f983, v0
; GFX6-NEXT: v_fract_f32_e32 v0, v0
; GFX6-NEXT: v_sin_f32_e32 v0, v0
; GFX6-NEXT: v_sin_f32_e32 v1, v1
; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s2
; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s3
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s2, 0xffff
; GCN-NOHSA-SI-NEXT: s_mov_b32 s4, s0
; GCN-NOHSA-SI-NEXT: s_mov_b32 s5, s1
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v2, s2, v0
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, s2, v1
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v2, 0xffff, v0
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, 0xffff, v1
; GCN-NOHSA-SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 offset:8
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx2 v[2:3], off, s[4:7], 0
; GCN-NOHSA-SI-NEXT: s_endpgm
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: flat_load_dwordx2 v[3:4], v[0:1]
-; GCN-HSA-NEXT: s_mov_b32 s2, 0xffff
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s1
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GCN-HSA-NEXT: v_and_b32_e32 v2, s2, v4
-; GCN-HSA-NEXT: v_and_b32_e32 v0, s2, v3
+; GCN-HSA-NEXT: v_and_b32_e32 v2, 0xffff, v4
+; GCN-HSA-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GCN-HSA-NEXT: flat_store_dwordx3 v[5:6], v[0:2]
; GCN-HSA-NEXT: s_endpgm
;
; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s2
; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s3
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, 0xffff
; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v2, s2, v1
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v2, 0xffff, v1
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, s2, v0
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[4:7], 0
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s2
; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s3
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx2 v[4:5], off, s[8:11], 0
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s2, 0xffff
; GCN-NOHSA-SI-NEXT: s_mov_b32 s4, s0
; GCN-NOHSA-SI-NEXT: s_mov_b32 s5, s1
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v3, 16, v5
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v2, s2, v5
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, s2, v4
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v2, 0xffff, v5
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NOHSA-SI-NEXT: s_endpgm
;
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: flat_load_dwordx2 v[4:5], v[0:1]
-; GCN-HSA-NEXT: s_mov_b32 s2, 0xffff
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s1
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v5
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; GCN-HSA-NEXT: v_and_b32_e32 v2, s2, v5
-; GCN-HSA-NEXT: v_and_b32_e32 v0, s2, v4
+; GCN-HSA-NEXT: v_and_b32_e32 v2, 0xffff, v5
+; GCN-HSA-NEXT: v_and_b32_e32 v0, 0xffff, v4
; GCN-HSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GCN-HSA-NEXT: s_endpgm
;
; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s2
; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s3
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, 0xffff
; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v2, s2, v1
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v2, 0xffff, v1
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, s2, v0
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s2
; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s3
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s2, 0xffff
; GCN-NOHSA-SI-NEXT: s_mov_b32 s4, s0
; GCN-NOHSA-SI-NEXT: s_mov_b32 s5, s1
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v11, 16, v3
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v6, s2, v1
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, s2, v0
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v10, s2, v3
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, s2, v2
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v6, 0xffff, v1
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, 0xffff, v0
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v10, 0xffff, v3
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, 0xffff, v2
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:16
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0
; GCN-NOHSA-SI-NEXT: s_endpgm
; GCN-HSA-LABEL: global_zextload_v8i16_to_v8i32:
; GCN-HSA: ; %bb.0:
; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GCN-HSA-NEXT: s_mov_b32 s4, 0xffff
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v11, 16, v3
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GCN-HSA-NEXT: v_and_b32_e32 v10, s4, v3
-; GCN-HSA-NEXT: v_and_b32_e32 v8, s4, v2
+; GCN-HSA-NEXT: v_and_b32_e32 v10, 0xffff, v3
+; GCN-HSA-NEXT: v_and_b32_e32 v8, 0xffff, v2
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GCN-HSA-NEXT: v_and_b32_e32 v6, s4, v1
-; GCN-HSA-NEXT: v_and_b32_e32 v4, s4, v0
+; GCN-HSA-NEXT: v_and_b32_e32 v6, 0xffff, v1
+; GCN-HSA-NEXT: v_and_b32_e32 v4, 0xffff, v0
; GCN-HSA-NEXT: flat_store_dwordx4 v[14:15], v[8:11]
; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[4:7]
; GCN-HSA-NEXT: s_endpgm
; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s2
; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s3
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, 0xffff
; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v10, s2, v3
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v10, 0xffff, v3
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v8, s2, v2
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v8, 0xffff, v2
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v6, s2, v1
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v6, 0xffff, v1
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v4, s2, v0
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v4, 0xffff, v0
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:16
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0
; GCN-NOHSA-VI-NEXT: s_endpgm
; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s6
; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s7
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s6, 0xffff
; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v19, 16, v5
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v17, 16, v4
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v10, s6, v1
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, s6, v0
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v14, s6, v3
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v12, s6, v2
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v10, 0xffff, v1
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, 0xffff, v0
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v14, 0xffff, v3
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v12, 0xffff, v2
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v3, 16, v7
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v1, 16, v6
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v18, s6, v5
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v16, s6, v4
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v2, s6, v7
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, s6, v6
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v18, 0xffff, v5
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v16, 0xffff, v4
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v2, 0xffff, v7
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:32
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:16
; GCN-HSA-LABEL: global_zextload_v16i16_to_v16i32:
; GCN-HSA: ; %bb.0:
; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GCN-HSA-NEXT: s_mov_b32 s4, 0xffff
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_waitcnt vmcnt(1)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v11, 16, v3
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GCN-HSA-NEXT: v_and_b32_e32 v10, s4, v3
-; GCN-HSA-NEXT: v_and_b32_e32 v8, s4, v2
+; GCN-HSA-NEXT: v_and_b32_e32 v10, 0xffff, v3
+; GCN-HSA-NEXT: v_and_b32_e32 v8, 0xffff, v2
; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
; GCN-HSA-NEXT: s_waitcnt vmcnt(1)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v13, 16, v6
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v11, 16, v5
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v9, 16, v4
-; GCN-HSA-NEXT: v_and_b32_e32 v10, s4, v5
-; GCN-HSA-NEXT: v_and_b32_e32 v8, s4, v4
-; GCN-HSA-NEXT: v_and_b32_e32 v12, s4, v6
+; GCN-HSA-NEXT: v_and_b32_e32 v10, 0xffff, v5
+; GCN-HSA-NEXT: v_and_b32_e32 v8, 0xffff, v4
+; GCN-HSA-NEXT: v_and_b32_e32 v12, 0xffff, v6
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GCN-HSA-NEXT: v_and_b32_e32 v3, s4, v1
-; GCN-HSA-NEXT: v_and_b32_e32 v1, s4, v0
+; GCN-HSA-NEXT: v_and_b32_e32 v3, 0xffff, v1
+; GCN-HSA-NEXT: v_and_b32_e32 v1, 0xffff, v0
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s1
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; GCN-HSA-NEXT: v_and_b32_e32 v14, s4, v7
+; GCN-HSA-NEXT: v_and_b32_e32 v14, 0xffff, v7
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s0
; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[1:4]
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[12:15]
; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s7
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, 0xffff
; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(1)
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v11, 16, v1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v19, 16, v7
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v18, s6, v7
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v18, 0xffff, v7
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v17, 16, v6
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v16, s6, v6
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v10, s6, v1
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v16, 0xffff, v6
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v10, 0xffff, v1
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v8, s6, v0
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v8, 0xffff, v0
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v15, 16, v3
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v14, s6, v3
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v14, 0xffff, v3
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v13, 16, v2
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v12, s6, v2
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v12, 0xffff, v2
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v3, 16, v5
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v2, s6, v5
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v2, 0xffff, v5
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, s6, v4
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, 0xffff, v4
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:48
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:16
; GCN-NOHSA-SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NOHSA-SI-NEXT: s_mov_b32 s3, 0xf000
; GCN-NOHSA-SI-NEXT: s_mov_b32 s2, -1
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, 0xffff
; GCN-NOHSA-SI-NEXT: s_mov_b32 s10, s2
; GCN-NOHSA-SI-NEXT: s_mov_b32 s11, s3
; GCN-NOHSA-SI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(2)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v27, 16, v7
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v25, 16, v6
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v18, s0, v3
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v16, s0, v2
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v22, s0, v1
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v20, s0, v0
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v18, 0xffff, v3
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v16, 0xffff, v2
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v22, 0xffff, v1
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v20, 0xffff, v0
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v3, 16, v5
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v26, s0, v7
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v24, s0, v6
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v2, s0, v5
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, s0, v4
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v26, 0xffff, v7
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v24, 0xffff, v6
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v2, 0xffff, v5
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(1)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v7, 16, v11
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v5, 16, v10
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v31, 16, v9
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v29, 16, v8
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v6, s0, v11
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, s0, v10
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v30, s0, v9
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v28, s0, v8
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v6, 0xffff, v11
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, 0xffff, v10
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v30, 0xffff, v9
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v28, 0xffff, v8
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v11, 16, v15
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v9, 16, v14
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v35, 16, v13
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v33, 16, v12
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v10, s0, v15
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, s0, v14
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v34, s0, v13
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v32, s0, v12
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v10, 0xffff, v15
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, 0xffff, v14
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v34, 0xffff, v13
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v32, 0xffff, v12
; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[32:35], off, s[0:3], 0 offset:96
; GCN-HSA-LABEL: global_zextload_v32i16_to_v32i32:
; GCN-HSA: ; %bb.0:
; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GCN-HSA-NEXT: s_mov_b32 s14, 0xffff
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_add_u32 s4, s2, 16
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCN-HSA-NEXT: s_waitcnt vmcnt(3)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v19, 16, v1
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v17, 16, v0
-; GCN-HSA-NEXT: v_and_b32_e32 v18, s14, v1
-; GCN-HSA-NEXT: v_and_b32_e32 v16, s14, v0
+; GCN-HSA-NEXT: v_and_b32_e32 v18, 0xffff, v1
+; GCN-HSA-NEXT: v_and_b32_e32 v16, 0xffff, v0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s12
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s13
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
; GCN-HSA-NEXT: s_waitcnt vmcnt(3)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v19, 16, v5
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v17, 16, v4
-; GCN-HSA-NEXT: v_and_b32_e32 v18, s14, v5
-; GCN-HSA-NEXT: v_and_b32_e32 v16, s14, v4
+; GCN-HSA-NEXT: v_and_b32_e32 v18, 0xffff, v5
+; GCN-HSA-NEXT: v_and_b32_e32 v16, 0xffff, v4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s10
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v19, 16, v7
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v17, 16, v6
-; GCN-HSA-NEXT: v_and_b32_e32 v18, s14, v7
-; GCN-HSA-NEXT: v_and_b32_e32 v16, s14, v6
+; GCN-HSA-NEXT: v_and_b32_e32 v18, 0xffff, v7
+; GCN-HSA-NEXT: v_and_b32_e32 v16, 0xffff, v6
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s11
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[16:19]
; GCN-HSA-NEXT: s_waitcnt vmcnt(4)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v9
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 16, v8
-; GCN-HSA-NEXT: v_and_b32_e32 v6, s14, v9
-; GCN-HSA-NEXT: v_and_b32_e32 v4, s14, v8
+; GCN-HSA-NEXT: v_and_b32_e32 v6, 0xffff, v9
+; GCN-HSA-NEXT: v_and_b32_e32 v4, 0xffff, v8
; GCN-HSA-NEXT: s_add_u32 s0, s0, 48
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v19, 16, v11
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v17, 16, v10
-; GCN-HSA-NEXT: v_and_b32_e32 v18, s14, v11
-; GCN-HSA-NEXT: v_and_b32_e32 v16, s14, v10
+; GCN-HSA-NEXT: v_and_b32_e32 v18, 0xffff, v11
+; GCN-HSA-NEXT: v_and_b32_e32 v16, 0xffff, v10
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[16:19]
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v10, 16, v15
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v18, 16, v13
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v16, 16, v12
-; GCN-HSA-NEXT: v_and_b32_e32 v9, s14, v15
-; GCN-HSA-NEXT: v_and_b32_e32 v17, s14, v13
-; GCN-HSA-NEXT: v_and_b32_e32 v15, s14, v12
+; GCN-HSA-NEXT: v_and_b32_e32 v9, 0xffff, v15
+; GCN-HSA-NEXT: v_and_b32_e32 v17, 0xffff, v13
+; GCN-HSA-NEXT: v_and_b32_e32 v15, 0xffff, v12
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s1
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GCN-HSA-NEXT: v_and_b32_e32 v5, s14, v3
-; GCN-HSA-NEXT: v_and_b32_e32 v3, s14, v2
+; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xffff, v3
+; GCN-HSA-NEXT: v_and_b32_e32 v3, 0xffff, v2
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v8, 16, v14
-; GCN-HSA-NEXT: v_and_b32_e32 v7, s14, v14
+; GCN-HSA-NEXT: v_and_b32_e32 v7, 0xffff, v14
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s0
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[15:18]
; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[7:10]
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:32
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0 offset:48
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, 0xffff
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(3)
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v19, 16, v3
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v18, s0, v3
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v18, 0xffff, v3
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v17, 16, v2
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v16, s0, v2
+; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
+; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v31, 16, v15
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v30, 0xffff, v15
+; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v29, 16, v14
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v28, 0xffff, v14
+; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v15, 16, v13
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v14, 0xffff, v13
+; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v16, 0xffff, v2
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v2, s0, v1
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v2, 0xffff, v1
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, s0, v0
-; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(2)
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v23, 16, v7
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v22, s0, v7
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v22, 0xffff, v7
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v21, 16, v6
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v20, s0, v6
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v20, 0xffff, v6
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v6, s0, v5
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v6, 0xffff, v5
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v4, s0, v4
-; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(1)
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v27, 16, v11
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v26, s0, v11
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v26, 0xffff, v11
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v24, s0, v10
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v24, 0xffff, v10
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v11, 16, v9
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v10, s0, v9
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v10, 0xffff, v9
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v9, 16, v8
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v8, s0, v8
-; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v31, 16, v15
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v30, s0, v15
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v28, s0, v14
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v15, 16, v13
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v14, s0, v13
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v12, s0, v12
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:96
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[28:31], off, s[0:3], 0 offset:112
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:64
; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s6
; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s7
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, 0xffff
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[16:19], off, s[8:11], 0 offset:16
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(1)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v3, 16, v15
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v9, 16, v19
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v7, 16, v18
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v2, s0, v15
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, s0, v14
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v2, 0xffff, v15
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, 0xffff, v14
; GCN-NOHSA-SI-NEXT: buffer_store_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: buffer_store_dword v1, off, s[12:15], 0 offset:8 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: buffer_store_dword v2, off, s[12:15], 0 offset:12 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: buffer_store_dword v3, off, s[12:15], 0 offset:16 ; 4-byte Folded Spill
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v5, s0, v13
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v5, 0xffff, v13
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v3, s0, v12
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v3, 0xffff, v12
; GCN-NOHSA-SI-NEXT: buffer_store_dword v3, off, s[12:15], 0 offset:20 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: buffer_store_dword v4, off, s[12:15], 0 offset:24 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: buffer_store_dword v6, off, s[12:15], 0 offset:32 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v15, 16, v17
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v13, 16, v16
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, s0, v19
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, 0xffff, v19
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v6, s0, v18
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v6, 0xffff, v18
; GCN-NOHSA-SI-NEXT: buffer_store_dword v6, off, s[12:15], 0 offset:36 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: buffer_store_dword v7, off, s[12:15], 0 offset:40 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: buffer_store_dword v8, off, s[12:15], 0 offset:44 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: buffer_store_dword v9, off, s[12:15], 0 offset:48 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[24:27], off, s[8:11], 0 offset:32
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v14, s0, v17
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v12, s0, v16
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v12, 0xffff, v16
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[28:31], off, s[8:11], 0 offset:48
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(1)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v19, 16, v27
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v17, 16, v26
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v23, 16, v25
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v21, 16, v24
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v18, s0, v27
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v16, s0, v26
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v22, s0, v25
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v20, s0, v24
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v18, 0xffff, v27
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v16, 0xffff, v26
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v22, 0xffff, v25
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v20, 0xffff, v24
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v27, 16, v31
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v25, 16, v30
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v34, 16, v29
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v26, s0, v31
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v24, s0, v30
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v26, 0xffff, v31
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v24, 0xffff, v30
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[35:38], off, s[8:11], 0 offset:64
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v33, s0, v29
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v31, s0, v28
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v33, 0xffff, v29
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v31, 0xffff, v28
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[39:42], off, s[8:11], 0 offset:80
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(1)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v46, 16, v38
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v44, 16, v37
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v50, 16, v36
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v48, 16, v35
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v45, s0, v38
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v43, s0, v37
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v49, s0, v36
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v47, s0, v35
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v45, 0xffff, v38
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v43, 0xffff, v37
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v49, 0xffff, v36
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v47, 0xffff, v35
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v38, 16, v42
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v36, 16, v41
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v54, 16, v40
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v52, 16, v39
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v37, s0, v42
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v35, s0, v41
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v37, 0xffff, v42
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v35, 0xffff, v41
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[55:58], off, s[8:11], 0 offset:96
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v53, s0, v40
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v51, s0, v39
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v53, 0xffff, v40
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v51, 0xffff, v39
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[39:42], off, s[8:11], 0 offset:112
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(1)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v61, 16, v58
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v11, 16, v56
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v9, 16, v55
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v60, s0, v58
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v58, s0, v57
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v10, s0, v56
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, s0, v55
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v60, 0xffff, v58
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v58, 0xffff, v57
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v10, 0xffff, v56
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, 0xffff, v55
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v7, 16, v42
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v5, 16, v41
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v3, 16, v40
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v1, 16, v39
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v6, s0, v42
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, s0, v41
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v2, s0, v40
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, s0, v39
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v6, 0xffff, v42
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, 0xffff, v41
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v2, 0xffff, v40
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, 0xffff, v39
; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:224
; GCN-HSA-LABEL: global_zextload_v64i16_to_v64i32:
; GCN-HSA: ; %bb.0:
; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GCN-HSA-NEXT: s_mov_b32 s12, 0xffff
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_waitcnt vmcnt(6)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v27, 16, v1
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v25, 16, v0
-; GCN-HSA-NEXT: v_and_b32_e32 v26, s12, v1
-; GCN-HSA-NEXT: v_and_b32_e32 v24, s12, v0
+; GCN-HSA-NEXT: v_and_b32_e32 v26, 0xffff, v1
+; GCN-HSA-NEXT: v_and_b32_e32 v24, 0xffff, v0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s7
; GCN-HSA-NEXT: flat_load_dwordx4 v[32:35], v[0:1]
; GCN-HSA-NEXT: s_add_u32 s10, s0, 0xa0
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v27, 16, v3
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v25, 16, v2
-; GCN-HSA-NEXT: v_and_b32_e32 v26, s12, v3
-; GCN-HSA-NEXT: v_and_b32_e32 v24, s12, v2
+; GCN-HSA-NEXT: v_and_b32_e32 v26, 0xffff, v3
+; GCN-HSA-NEXT: v_and_b32_e32 v24, 0xffff, v2
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[24:27]
; GCN-HSA-NEXT: s_addc_u32 s11, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v25, s3
; GCN-HSA-NEXT: s_waitcnt vmcnt(8)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v5
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; GCN-HSA-NEXT: v_and_b32_e32 v2, s12, v5
-; GCN-HSA-NEXT: v_and_b32_e32 v0, s12, v4
+; GCN-HSA-NEXT: v_and_b32_e32 v2, 0xffff, v5
+; GCN-HSA-NEXT: v_and_b32_e32 v0, 0xffff, v4
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v24, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xb0
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v7
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v1, 16, v6
-; GCN-HSA-NEXT: v_and_b32_e32 v2, s12, v7
-; GCN-HSA-NEXT: v_and_b32_e32 v0, s12, v6
+; GCN-HSA-NEXT: v_and_b32_e32 v2, 0xffff, v7
+; GCN-HSA-NEXT: v_and_b32_e32 v0, 0xffff, v6
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
; GCN-HSA-NEXT: s_waitcnt vmcnt(9)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v9
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v1, 16, v8
-; GCN-HSA-NEXT: v_and_b32_e32 v2, s12, v9
-; GCN-HSA-NEXT: v_and_b32_e32 v0, s12, v8
+; GCN-HSA-NEXT: v_and_b32_e32 v2, 0xffff, v9
+; GCN-HSA-NEXT: v_and_b32_e32 v0, 0xffff, v8
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v11
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v1, 16, v10
-; GCN-HSA-NEXT: v_and_b32_e32 v2, s12, v11
-; GCN-HSA-NEXT: v_and_b32_e32 v0, s12, v10
+; GCN-HSA-NEXT: v_and_b32_e32 v2, 0xffff, v11
+; GCN-HSA-NEXT: v_and_b32_e32 v0, 0xffff, v10
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s2
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 16, v14
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v13
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v1, 16, v12
-; GCN-HSA-NEXT: v_and_b32_e32 v2, s12, v13
-; GCN-HSA-NEXT: v_and_b32_e32 v0, s12, v12
-; GCN-HSA-NEXT: v_and_b32_e32 v4, s12, v14
+; GCN-HSA-NEXT: v_and_b32_e32 v2, 0xffff, v13
+; GCN-HSA-NEXT: v_and_b32_e32 v0, 0xffff, v12
+; GCN-HSA-NEXT: v_and_b32_e32 v6, 0xffff, v15
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s4
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v15
-; GCN-HSA-NEXT: v_and_b32_e32 v6, s12, v15
+; GCN-HSA-NEXT: v_and_b32_e32 v4, 0xffff, v14
; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
; GCN-HSA-NEXT: s_waitcnt vmcnt(11)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v17
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s3
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v1, 16, v16
-; GCN-HSA-NEXT: v_and_b32_e32 v2, s12, v17
-; GCN-HSA-NEXT: v_and_b32_e32 v0, s12, v16
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GCN-HSA-NEXT: v_and_b32_e32 v2, 0xffff, v17
+; GCN-HSA-NEXT: v_and_b32_e32 v0, 0xffff, v16
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x60
+; GCN-HSA-NEXT: v_lshrrev_b32_e32 v4, 16, v19
; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v19
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v1, 16, v18
-; GCN-HSA-NEXT: v_and_b32_e32 v2, s12, v19
-; GCN-HSA-NEXT: v_and_b32_e32 v0, s12, v18
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: v_lshrrev_b32_e32 v2, 16, v18
+; GCN-HSA-NEXT: v_and_b32_e32 v3, 0xffff, v19
+; GCN-HSA-NEXT: v_and_b32_e32 v1, 0xffff, v18
+; GCN-HSA-NEXT: flat_store_dwordx4 v[5:6], v[1:4]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x70
; GCN-HSA-NEXT: s_waitcnt vmcnt(10)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v15, 16, v33
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v13, 16, v32
-; GCN-HSA-NEXT: v_and_b32_e32 v14, s12, v33
-; GCN-HSA-NEXT: v_and_b32_e32 v12, s12, v32
+; GCN-HSA-NEXT: v_and_b32_e32 v14, 0xffff, v33
+; GCN-HSA-NEXT: v_and_b32_e32 v12, 0xffff, v32
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v21
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v1, 16, v20
-; GCN-HSA-NEXT: v_and_b32_e32 v2, s12, v21
-; GCN-HSA-NEXT: v_and_b32_e32 v0, s12, v20
+; GCN-HSA-NEXT: v_and_b32_e32 v2, 0xffff, v21
+; GCN-HSA-NEXT: v_and_b32_e32 v0, 0xffff, v20
; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s3
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v23
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 16, v22
-; GCN-HSA-NEXT: v_and_b32_e32 v6, s12, v23
-; GCN-HSA-NEXT: v_and_b32_e32 v4, s12, v22
+; GCN-HSA-NEXT: v_and_b32_e32 v6, 0xffff, v23
+; GCN-HSA-NEXT: v_and_b32_e32 v4, 0xffff, v22
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v11, 16, v35
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v9, 16, v34
-; GCN-HSA-NEXT: v_and_b32_e32 v10, s12, v35
-; GCN-HSA-NEXT: v_and_b32_e32 v8, s12, v34
+; GCN-HSA-NEXT: v_and_b32_e32 v10, 0xffff, v35
+; GCN-HSA-NEXT: v_and_b32_e32 v8, 0xffff, v34
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
; GCN-HSA-NEXT: s_add_u32 s0, s0, 48
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v29
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 16, v28
-; GCN-HSA-NEXT: v_and_b32_e32 v6, s12, v29
-; GCN-HSA-NEXT: v_and_b32_e32 v4, s12, v28
+; GCN-HSA-NEXT: v_and_b32_e32 v6, 0xffff, v29
+; GCN-HSA-NEXT: v_and_b32_e32 v4, 0xffff, v28
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s2
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v31
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v1, 16, v30
-; GCN-HSA-NEXT: v_and_b32_e32 v2, s12, v31
-; GCN-HSA-NEXT: v_and_b32_e32 v0, s12, v30
+; GCN-HSA-NEXT: v_and_b32_e32 v2, 0xffff, v31
+; GCN-HSA-NEXT: v_and_b32_e32 v0, 0xffff, v30
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_endpgm
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[24:27], off, s[4:7], 0 offset:16
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[28:31], off, s[4:7], 0 offset:32
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[32:35], off, s[4:7], 0 offset:48
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, 0xffff
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(7)
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v63, 16, v11
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v62, s4, v11
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v62, 0xffff, v11
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v61, 16, v10
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v60, s4, v10
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v60, 0xffff, v10
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v11, 16, v9
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v10, s4, v9
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v10, 0xffff, v9
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v9, 16, v8
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v8, s4, v8
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(3)
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v3, 16, v7
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v2, s4, v7
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v2, 0xffff, v7
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v6
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, s4, v6
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, 0xffff, v6
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v6, s4, v5
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v6, 0xffff, v5
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v4, s4, v4
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(2)
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v39, 16, v27
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v38, s4, v27
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v38, 0xffff, v27
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v37, 16, v26
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v36, s4, v26
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v36, 0xffff, v26
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v26, s4, v25
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v26, 0xffff, v25
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v25, 16, v24
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v24, s4, v24
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(1)
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v43, 16, v31
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v42, s4, v31
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v42, 0xffff, v31
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v41, 16, v30
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v40, s4, v30
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v40, 0xffff, v30
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v30, s4, v29
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v30, 0xffff, v29
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v29, 16, v28
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v28, s4, v28
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v47, 16, v35
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v46, s4, v35
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v46, 0xffff, v35
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v45, 16, v34
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v44, s4, v34
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v44, 0xffff, v34
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v35, 16, v33
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v34, s4, v33
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v34, 0xffff, v33
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v33, 16, v32
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v32, s4, v32
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v32, 0xffff, v32
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v51, 16, v23
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v50, s4, v23
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v50, 0xffff, v23
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v49, 16, v22
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v48, s4, v22
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v48, 0xffff, v22
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v22, s4, v21
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v22, 0xffff, v21
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v21, 16, v20
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v20, s4, v20
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v55, 16, v19
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v54, s4, v19
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v54, 0xffff, v19
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v53, 16, v18
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v52, s4, v18
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v52, 0xffff, v18
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v18, s4, v17
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v18, 0xffff, v17
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v17, 16, v16
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v16, s4, v16
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v59, 16, v15
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v58, s4, v15
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v58, 0xffff, v15
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v57, 16, v14
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v56, s4, v14
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v56, 0xffff, v14
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v15, 16, v13
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v14, s4, v13
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v14, 0xffff, v13
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v12, s4, v12
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:224
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[60:63], off, s[0:3], 0 offset:240
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:192
; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s3
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx2 v[8:9], off, s[8:11], 0
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s2, 0xffff
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, v1
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v5, v1
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, v1
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v2, 16, v9
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v6, 16, v8
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, s2, v8
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, s2, v9
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, 0xffff, v8
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, 0xffff, v9
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 offset:16
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0
; GCN-NOHSA-SI-NEXT: s_endpgm
; GCN-HSA-LABEL: global_zextload_v4i16_to_v4i64:
; GCN-HSA: ; %bb.0:
; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GCN-HSA-NEXT: s_mov_b32 s4, 0xffff
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v2, 16, v9
-; GCN-HSA-NEXT: v_and_b32_e32 v0, s4, v9
+; GCN-HSA-NEXT: v_and_b32_e32 v0, 0xffff, v9
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v6, 16, v8
-; GCN-HSA-NEXT: v_and_b32_e32 v4, s4, v8
+; GCN-HSA-NEXT: v_and_b32_e32 v4, 0xffff, v8
; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
; GCN-HSA-NEXT: s_endpgm
; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s2
; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s3
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx2 v[8:9], off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, 0xffff
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, 0
; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, v5
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v4, s2, v9
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v4, 0xffff, v9
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v6, 16, v9
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, s2, v8
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, 0xffff, v8
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v2, 16, v8
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
define amdgpu_kernel void @global_zextload_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(1)* %in) #0 {
; GCN-NOHSA-SI-LABEL: global_zextload_v8i16_to_v8i64:
; GCN-NOHSA-SI: ; %bb.0:
-; GCN-NOHSA-SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s2, -1
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s12, 0xffff
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s10, s2
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s11, s3
+; GCN-NOHSA-SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s6, -1
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s10, s6
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s11, s7
; GCN-NOHSA-SI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s6
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s7
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s2
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s3
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, 0
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v9, 0
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v19, v9
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v13, v9
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v5, v9
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s4, s0
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s5, s1
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v18, 16, v1
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v10, 16, v3
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v14, 16, v2
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, s12, v0
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v12, s12, v2
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v16, s12, v1
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, s12, v3
-; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:48
-; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:16
-; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:32
-; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, 0xffff, v0
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v12, 0xffff, v2
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v16, 0xffff, v1
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, 0xffff, v3
+; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:48
+; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[16:19], off, s[4:7], 0 offset:16
+; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[4:7], 0 offset:32
+; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0
; GCN-NOHSA-SI-NEXT: s_endpgm
;
; GCN-HSA-LABEL: global_zextload_v8i16_to_v8i64:
; GCN-HSA: ; %bb.0:
; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GCN-HSA-NEXT: s_mov_b32 s4, 0xffff
; GCN-HSA-NEXT: v_mov_b32_e32 v12, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v14, v12
; GCN-HSA-NEXT: v_mov_b32_e32 v15, v12
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, v12
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s3
; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, v12
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s2
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v6, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v10, 0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v13, 16, v3
-; GCN-HSA-NEXT: v_and_b32_e32 v11, s4, v3
+; GCN-HSA-NEXT: v_and_b32_e32 v11, 0xffff, v3
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[11:14]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, v12
; GCN-HSA-NEXT: v_mov_b32_e32 v13, v12
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v14, 16, v1
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GCN-HSA-NEXT: v_and_b32_e32 v3, s4, v0
-; GCN-HSA-NEXT: v_and_b32_e32 v12, s4, v1
+; GCN-HSA-NEXT: v_and_b32_e32 v3, 0xffff, v0
+; GCN-HSA-NEXT: v_and_b32_e32 v12, 0xffff, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GCN-HSA-NEXT: v_and_b32_e32 v7, s4, v2
+; GCN-HSA-NEXT: v_and_b32_e32 v7, 0xffff, v2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[12:15]
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[7:10]
; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s6
; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s7
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, 0xffff
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v19, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v17, 0
; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v9, v17
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, v17
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v16, s6, v3
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v16, 0xffff, v3
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v4, s6, v0
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v4, 0xffff, v0
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v8, s6, v1
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v8, 0xffff, v1
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v10, 16, v1
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v12, s6, v2
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v12, 0xffff, v2
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v14, 16, v2
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:48
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:32
; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s6
; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s7
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, 0xffff
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(1)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v10, 16, v1
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v14, 16, v2
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v18, 16, v0
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v16, s0, v0
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v12, s0, v2
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, s0, v1
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v16, 0xffff, v0
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v12, 0xffff, v2
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, 0xffff, v1
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, s0, v3
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v20, 0
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v21, 16, v5
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v25, 16, v6
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v23, s0, v6
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v23, 0xffff, v6
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, s0, v4
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v26, s0, v7
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v19, s0, v5
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v26, 0xffff, v7
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v19, 0xffff, v5
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v22, v20
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v27, v20
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v29, v20
; GCN-HSA-LABEL: global_zextload_v16i16_to_v16i64:
; GCN-HSA: ; %bb.0:
; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GCN-HSA-NEXT: s_mov_b32 s6, 0xffff
; GCN-HSA-NEXT: v_mov_b32_e32 v8, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v10, v8
; GCN-HSA-NEXT: v_mov_b32_e32 v12, v8
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, 0
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s4
; GCN-HSA-NEXT: s_add_u32 s4, s0, 0x50
; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, 0
; GCN-HSA-NEXT: s_waitcnt vmcnt(1)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v11, 16, v1
-; GCN-HSA-NEXT: v_and_b32_e32 v9, s6, v1
+; GCN-HSA-NEXT: v_and_b32_e32 v9, 0xffff, v1
; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[9:12]
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s5
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s4
; GCN-HSA-NEXT: s_add_u32 s4, s0, 0x70
; GCN-HSA-NEXT: s_waitcnt vmcnt(1)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v11, 16, v5
-; GCN-HSA-NEXT: v_and_b32_e32 v9, s6, v5
+; GCN-HSA-NEXT: v_and_b32_e32 v9, 0xffff, v5
; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[9:12]
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s5
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s4
; GCN-HSA-NEXT: s_add_u32 s4, s0, 32
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v11, 16, v7
-; GCN-HSA-NEXT: v_and_b32_e32 v9, s6, v7
+; GCN-HSA-NEXT: v_and_b32_e32 v9, 0xffff, v7
; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[9:12]
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s5
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v11, 16, v2
-; GCN-HSA-NEXT: v_and_b32_e32 v9, s6, v2
+; GCN-HSA-NEXT: v_and_b32_e32 v9, 0xffff, v2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v12, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s4
; GCN-HSA-NEXT: s_add_u32 s2, s0, 64
; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[9:12]
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v14, 16, v4
-; GCN-HSA-NEXT: v_and_b32_e32 v12, s6, v4
+; GCN-HSA-NEXT: v_and_b32_e32 v12, 0xffff, v4
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: s_add_u32 s0, s0, 0x60
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v9, 16, v3
-; GCN-HSA-NEXT: v_and_b32_e32 v7, s6, v3
+; GCN-HSA-NEXT: v_and_b32_e32 v7, 0xffff, v3
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[1:2], v[7:10]
; GCN-HSA-NEXT: v_mov_b32_e32 v13, v8
; GCN-HSA-NEXT: v_mov_b32_e32 v1, v8
; GCN-HSA-NEXT: v_mov_b32_e32 v3, 0
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v10, 16, v6
-; GCN-HSA-NEXT: v_and_b32_e32 v8, s6, v6
+; GCN-HSA-NEXT: v_and_b32_e32 v8, 0xffff, v6
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s3
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GCN-HSA-NEXT: v_and_b32_e32 v0, s6, v0
+; GCN-HSA-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v11, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s2
; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s7
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, 0xffff
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v30, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v28, 0
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v25, v28
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v21, v28
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v19, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v23, 0
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(1)
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v8, s0, v0
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v12, s0, v1
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, s0, v2
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v16, s0, v3
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v16, 0xffff, v3
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v20, s0, v4
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v24, s0, v5
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v3, s0, v6
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v27, s0, v7
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v27, 0xffff, v7
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
+; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v20, 0xffff, v4
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v22, 16, v4
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v24, 0xffff, v5
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v26, 16, v5
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v3, 0xffff, v6
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v5, 16, v6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, v28
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[27:30], off, s[0:3], 0 offset:112
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v27, 0
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v8, 0xffff, v0
+; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v10, 16, v0
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v12, 0xffff, v1
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v14, 16, v1
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, 0xffff, v2
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, v28
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[3:6], off, s[0:3], 0 offset:96
; GCN-NOHSA-SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NOHSA-SI-NEXT: s_mov_b32 s3, 0xf000
; GCN-NOHSA-SI-NEXT: s_mov_b32 s2, -1
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, 0xffff
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, 0
; GCN-NOHSA-SI-NEXT: s_mov_b32 s10, s2
; GCN-NOHSA-SI-NEXT: s_mov_b32 s11, s3
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v23, 16, v3
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v21, 16, v4
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v20, 16, v2
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v18, s0, v2
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v18, 0xffff, v2
; GCN-NOHSA-SI-NEXT: buffer_store_dword v18, off, s[12:15], 0 offset:4 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: buffer_store_dword v19, off, s[12:15], 0 offset:8 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: buffer_store_dword v20, off, s[12:15], 0 offset:12 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: buffer_store_dword v21, off, s[12:15], 0 offset:16 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(2)
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v19, s0, v4
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v19, 0xffff, v4
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: buffer_store_dword v19, off, s[12:15], 0 offset:20 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: buffer_store_dword v20, off, s[12:15], 0 offset:24 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: buffer_store_dword v21, off, s[12:15], 0 offset:28 ; 4-byte Folded Spill
; GCN-NOHSA-SI-NEXT: buffer_store_dword v22, off, s[12:15], 0 offset:32 ; 4-byte Folded Spill
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, s0, v3
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v4, 0xffff, v3
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v32, 16, v5
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v30, s0, v5
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v30, 0xffff, v5
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v36, 16, v6
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v34, s0, v6
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v34, 0xffff, v6
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v26, s0, v8
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v26, 0xffff, v8
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v40, 16, v7
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v38, s0, v7
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v38, 0xffff, v7
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v44, 16, v9
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v42, s0, v9
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v42, 0xffff, v9
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v48, 16, v10
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v46, s0, v10
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v46, 0xffff, v10
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v24, 16, v12
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v22, s0, v12
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v22, 0xffff, v12
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v50, s0, v11
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v50, 0xffff, v11
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v56, 16, v13
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v54, s0, v13
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v54, 0xffff, v13
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v2, 16, v17
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v60, 16, v14
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v58, s0, v14
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v58, 0xffff, v14
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v18, s0, v16
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v18, 0xffff, v16
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v10, 16, v15
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, s0, v15
-; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, s0, v17
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v8, 0xffff, v15
+; GCN-NOHSA-SI-NEXT: v_and_b32_e32 v0, 0xffff, v17
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, v1
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v9, v1
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v11, v1
; GCN-HSA-LABEL: global_zextload_v32i16_to_v32i64:
; GCN-HSA: ; %bb.0:
; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GCN-HSA-NEXT: s_mov_b32 s18, 0xffff
; GCN-HSA-NEXT: v_mov_b32_e32 v4, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v6, v4
; GCN-HSA-NEXT: v_mov_b32_e32 v8, v4
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: s_waitcnt vmcnt(3)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GCN-HSA-NEXT: v_and_b32_e32 v5, s18, v3
+; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xffff, v3
; GCN-HSA-NEXT: flat_store_dwordx4 v[21:22], v[5:8]
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s3
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GCN-HSA-NEXT: v_and_b32_e32 v5, s18, v1
+; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xffff, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v21, s2
; GCN-HSA-NEXT: flat_store_dwordx4 v[21:22], v[5:8]
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s13
; GCN-HSA-NEXT: s_waitcnt vmcnt(4)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v12
-; GCN-HSA-NEXT: v_and_b32_e32 v5, s18, v12
+; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xffff, v12
; GCN-HSA-NEXT: v_mov_b32_e32 v21, s12
; GCN-HSA-NEXT: flat_store_dwordx4 v[21:22], v[5:8]
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s15
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v10
-; GCN-HSA-NEXT: v_and_b32_e32 v5, s18, v10
+; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xffff, v10
; GCN-HSA-NEXT: v_mov_b32_e32 v21, s14
; GCN-HSA-NEXT: flat_store_dwordx4 v[21:22], v[5:8]
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s7
; GCN-HSA-NEXT: s_waitcnt vmcnt(5)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v14
-; GCN-HSA-NEXT: v_and_b32_e32 v5, s18, v14
+; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xffff, v14
; GCN-HSA-NEXT: v_mov_b32_e32 v21, s6
; GCN-HSA-NEXT: flat_store_dwordx4 v[21:22], v[5:8]
; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
; GCN-HSA-NEXT: s_waitcnt vmcnt(5)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v20
-; GCN-HSA-NEXT: v_and_b32_e32 v5, s18, v20
+; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xffff, v20
; GCN-HSA-NEXT: v_mov_b32_e32 v21, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v20, s8
; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[5:8]
; GCN-HSA-NEXT: v_mov_b32_e32 v21, s11
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v18
-; GCN-HSA-NEXT: v_and_b32_e32 v5, s18, v18
+; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xffff, v18
; GCN-HSA-NEXT: v_mov_b32_e32 v20, s10
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[5:8]
-; GCN-HSA-NEXT: v_and_b32_e32 v3, s18, v16
+; GCN-HSA-NEXT: v_and_b32_e32 v3, 0xffff, v16
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v15
-; GCN-HSA-NEXT: v_and_b32_e32 v5, s18, v15
+; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xffff, v15
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v8, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s2
; GCN-HSA-NEXT: flat_store_dwordx4 v[14:15], v[5:8]
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xe0
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v13
-; GCN-HSA-NEXT: v_and_b32_e32 v5, s18, v13
+; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xffff, v13
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v8, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s0
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xc0
; GCN-HSA-NEXT: v_mov_b32_e32 v8, 0
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v19
-; GCN-HSA-NEXT: v_and_b32_e32 v5, s18, v19
+; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xffff, v19
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[5:8]
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xa0
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v17
-; GCN-HSA-NEXT: v_and_b32_e32 v5, s18, v17
+; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xffff, v17
; GCN-HSA-NEXT: v_mov_b32_e32 v8, 0
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[5:8]
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v19, 16, v9
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v11
-; GCN-HSA-NEXT: v_and_b32_e32 v5, s18, v11
+; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xffff, v11
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v8, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s2
; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[5:8]
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GCN-HSA-NEXT: v_and_b32_e32 v8, s18, v0
+; GCN-HSA-NEXT: v_and_b32_e32 v8, 0xffff, v0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 16, v16
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[3:6]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
-; GCN-HSA-NEXT: v_and_b32_e32 v17, s18, v9
+; GCN-HSA-NEXT: v_and_b32_e32 v17, 0xffff, v9
; GCN-HSA-NEXT: v_mov_b32_e32 v20, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v18, v4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v14, 16, v2
-; GCN-HSA-NEXT: v_and_b32_e32 v12, s18, v2
+; GCN-HSA-NEXT: v_and_b32_e32 v12, 0xffff, v2
; GCN-HSA-NEXT: v_mov_b32_e32 v15, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v13, v4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[5:8], off, s[8:11], 0 offset:16
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[31:34], off, s[8:11], 0 offset:32
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[35:38], off, s[8:11], 0 offset:48
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, 0xffff
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v57, 0
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v12, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v16, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v24, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v16, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v20, 0
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(3)
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, s0, v2
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v9, s0, v1
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, 0xffff, v2
+; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(1)
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v45, 0xffff, v33
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v48, s0, v36
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v48, 0xffff, v36
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v50, 16, v36
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v54, s0, v38
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v54, 0xffff, v38
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v56, 16, v38
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v36, s0, v37
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v36, 0xffff, v37
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v38, 16, v37
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v37, 0
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v13, s0, v4
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v17, s0, v3
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v4, s0, v6
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v21, s0, v5
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v25, s0, v8
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v28, s0, v7
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v39, s0, v32
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v41, 16, v32
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v42, s0, v31
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v32, s0, v34
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v45, s0, v33
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v51, s0, v35
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v55, v37
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v51, 0xffff, v35
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v53, 16, v35
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[54:57], off, s[0:3], 0 offset:240
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v52, v37
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[48:51], off, s[0:3], 0 offset:208
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v46, v37
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v48, 0
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v28, 0xffff, v7
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v42, 0xffff, v31
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v44, 16, v31
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[45:48], off, s[0:3], 0 offset:160
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v43, v37
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v31, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v29, v37
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v9, 0xffff, v1
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v17, 0xffff, v3
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v19, 16, v3
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v25, 0xffff, v8
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v27, 16, v8
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v39, 0xffff, v32
+; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v41, 16, v32
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v32, 0xffff, v34
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v34, 16, v34
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v35, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v33, v37
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v28, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v26, v37
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v14, v37
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v10, v37
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, v37
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v13, 0xffff, v4
+; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v15, 16, v4
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v4, 0xffff, v6
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v21, 0xffff, v5
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v23, 16, v5
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[32:35], off, s[0:3], 0 offset:176
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[39:42], off, s[0:3], 0 offset:144
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v22, v37
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, v37
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v18, v37
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v14, v37
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[25:28], off, s[0:3], 0 offset:112
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[21:24], off, s[0:3], 0 offset:64
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:80
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
; CI-NEXT: buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
-; CI-NEXT: s_mov_b32 s4, 0xffff
; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; CI-NEXT: v_and_b32_e32 v0, s4, v0
+; CI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; CI-NEXT: v_and_b32_e32 v1, s4, v1
+; CI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; CI-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; CI-NEXT: v_lshrrev_b32_e32 v9, 16, v3
; CI-NEXT: v_lshrrev_b32_e32 v1, v3, v1
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
-; CI-NEXT: s_mov_b32 s4, 0xff00ff
; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v3, 8, v3
; CI-NEXT: v_lshrrev_b32_e32 v2, 8, v2
-; CI-NEXT: v_and_b32_e32 v3, s4, v3
-; CI-NEXT: v_and_b32_e32 v2, s4, v2
+; CI-NEXT: v_and_b32_e32 v3, 0xff00ff, v3
+; CI-NEXT: v_and_b32_e32 v2, 0xff00ff, v2
; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
; CI-NEXT: s_endpgm
;
; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; GCN-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
-; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x41200000
-; GCN-DAG: v_mac_f32_e32 [[VB]], [[SK]], [[VA]]
-; GCN-DAG: v_mac_f32_e32 [[VC]], [[SK]], [[VA]]
+; GCN-DAG: v_mac_f32_e32 [[VB]], 0x41200000, [[VA]]
+; GCN-DAG: v_mac_f32_e32 [[VC]], 0x41200000, [[VA]]
; GCN: s_endpgm
define amdgpu_kernel void @madmk_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX89 %s
; GCN-LABEL: {{^}}v_mul_i16:
-; SI: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}}
-; SI: v_and_b32_e32 v{{[0-9]+}}, [[K]]
-; SI: v_and_b32_e32 v{{[0-9]+}}, [[K]]
+; SI: v_and_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
+; SI: v_and_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
; SI: v_mul_u32_u24
; GFX89: v_mul_lo_u16_e32 v0, v0, v1
; GCN-LABEL: test_umul24_anyextend_i23_src0_src1:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s4, 0x7fffff
-; GCN-NEXT: v_and_b32_e32 v0, s4, v0
-; GCN-NEXT: v_and_b32_e32 v1, s4, v1
+; GCN-NEXT: v_and_b32_e32 v0, 0x7fffff, v0
+; GCN-NEXT: v_and_b32_e32 v1, 0x7fffff, v1
; GCN-NEXT: v_mul_u32_u24_e32 v0, 0xea, v0
; GCN-NEXT: v_mul_u32_u24_e32 v1, 0x39b, v1
; GCN-NEXT: v_and_b32_e32 v0, 0x7ffffe, v0
-; GCN-NEXT: v_and_b32_e32 v1, s4, v1
+; GCN-NEXT: v_and_b32_e32 v1, 0x7fffff, v1
; GCN-NEXT: v_mul_u32_u24_e32 v0, v0, v1
; GCN-NEXT: v_and_b32_e32 v0, 0x1fffe, v0
; GCN-NEXT: v_mul_u32_u24_e32 v0, 0x63, v0
ret void
}
; CHECK-LABEL: {{^}}vector_imm:
-; CHECK: s_movk_i32 [[IMM:s[0-9]+]], 0x64
-; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
-; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
-; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
-; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
+; CHECK: v_xor_b32_e32 v{{[0-9]}}, 0x64, v{{[0-9]}}
+; CHECK: v_xor_b32_e32 v{{[0-9]}}, 0x64, v{{[0-9]}}
+; CHECK: v_xor_b32_e32 v{{[0-9]}}, 0x64, v{{[0-9]}}
+; CHECK: v_xor_b32_e32 v{{[0-9]}}, 0x64, v{{[0-9]}}
define amdgpu_kernel void @vector_imm(<4 x i32> addrspace(1)* %out) #1 {
entry:
}
; GCN-LABEL: {{^}}fadd_v2_v_imm:
-; GCN: s_mov_b32 s[[K:[0-9]+]], 0x42c80000
-; GFX900-COUNT-2: v_add_f32_e32 v{{[0-9]+}}, s[[K]], v{{[0-9]+}}
+; GFX90A: s_mov_b32 s[[K:[0-9]+]], 0x42c80000
+; GFX900-COUNT-2: v_add_f32_e32 v{{[0-9]+}}, 0x42c80000, v{{[0-9]+}}
; GFX90A: v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[[[K]]:{{[0-9:]+}}] op_sel_hi:[1,0]{{$}}
define amdgpu_kernel void @fadd_v2_v_imm(<2 x float> addrspace(1)* %a) {
%id = tail call i32 @llvm.amdgcn.workitem.id.x()
}
; GCN-LABEL: {{^}}fmul_v2_v_imm:
-; GCN: s_mov_b32 s[[K:[0-9]+]], 0x42c80000
-; GFX900-COUNT-2: v_mul_f32_e32 v{{[0-9]+}}, s[[K]], v{{[0-9]+}}
+; GFX90A: s_mov_b32 s[[K:[0-9]+]], 0x42c80000
+; GFX900-COUNT-2: v_mul_f32_e32 v{{[0-9]+}}, 0x42c80000, v{{[0-9]+}}
; GFX90A: v_pk_mul_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[[[K]]:{{[0-9:]+}}] op_sel_hi:[1,0]{{$}}
define amdgpu_kernel void @fmul_v2_v_imm(<2 x float> addrspace(1)* %a) {
%id = tail call i32 @llvm.amdgcn.workitem.id.x()
}
; GCN-LABEL: {{^}}fneg_v2f32_vec:
-; GFX900: s_brev_b32 [[SIGN:s[0-9]+]], 1
-; GFX900-COUNT-2: v_xor_b32_e32 v{{[0-9]+}}, [[SIGN]], v{{[0-9]+}}
+; GFX900-COUNT-2: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
; GFX90A: v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 0 neg_lo:[1,1] neg_hi:[1,1]{{$}}
define amdgpu_kernel void @fneg_v2f32_vec(<2 x float> addrspace(1)* %a) {
%id = tail call i32 @llvm.amdgcn.workitem.id.x()
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; SI-LABEL: {{^}}s_movk_i32_k0:
-; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xffff{{$}}
; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xffff, v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 1, v[[HI_VREG]]
; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k0(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
}
; SI-LABEL: {{^}}s_movk_i32_k1:
-; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x7fff{{$}}
; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x7fff, v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 1, v[[HI_VREG]]
; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k1(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
; SI-LABEL: {{^}}s_movk_i32_k2:
; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x7fff{{$}}
; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x7fff, v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 64, v[[HI_VREG]]
; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k2(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
}
; SI-LABEL: {{^}}s_movk_i32_k3:
-; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0x8000{{$}}
; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x8000, v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 1, v[[HI_VREG]]
; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k3(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
}
; SI-LABEL: {{^}}s_movk_i32_k4:
-; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0x20000{{$}}
; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x20000, v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 1, v[[HI_VREG]]
; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k4(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
}
; SI-LABEL: {{^}}s_movk_i32_k5:
-; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0xffef{{$}}
-; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0xff00ffff{{$}}
; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xffffffef, v[[LO_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xff00ffff, v[[HI_VREG]]
; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k5(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4
}
; SI-LABEL: {{^}}s_movk_i32_k6:
-; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x41{{$}}
; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x41, v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 63, v[[HI_VREG]]
; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k6(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
}
; SI-LABEL: {{^}}s_movk_i32_k7:
-; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x2000{{$}}
-; SI-DAG: s_movk_i32 [[HI_S_IMM:s[0-9]+]], 0x4000{{$}}
; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x2000, v[[LO_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x4000, v[[HI_VREG]]
; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k7(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4
}
; SI-LABEL: {{^}}s_movk_i32_k8:
-; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x8000{{$}}
-; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xffff8000, v[[LO_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x11111111, v[[HI_VREG]]
; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k8(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4
}
; SI-LABEL: {{^}}s_movk_i32_k9:
-; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x8001{{$}}
-; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xffff8001, v[[LO_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x11111111, v[[HI_VREG]]
; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k9(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4
}
; SI-LABEL: {{^}}s_movk_i32_k10:
-; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x8888{{$}}
-; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xffff8888, v[[LO_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x11111111, v[[HI_VREG]]
; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k10(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4
}
; SI-LABEL: {{^}}s_movk_i32_k11:
-; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x8fff{{$}}
-; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xffff8fff, v[[LO_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x11111111, v[[HI_VREG]]
; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k11(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4
}
; SI-LABEL: {{^}}s_movk_i32_k12:
-; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xffff7001{{$}}
-; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xffff7001, v[[LO_VREG]]
+; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x11111111, v[[HI_VREG]]
; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k12(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4
; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT: s_movk_i32 s4, 0x7fff
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_min_i32_e32 v1, s4, v1
-; GFX6-NEXT: s_movk_i32 s5, 0x8000
-; GFX6-NEXT: v_min_i32_e32 v0, s4, v0
-; GFX6-NEXT: v_max_i32_e32 v1, s5, v1
-; GFX6-NEXT: v_max_i32_e32 v0, s5, v0
+; GFX6-NEXT: v_min_i32_e32 v1, 0x7fff, v1
+; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0
+; GFX6-NEXT: v_max_i32_e32 v1, 0xffff8000, v1
+; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v4, v3
; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v2
; GFX8-NEXT: v_ashrrev_i16_e32 v2, 15, v4
-; GFX8-NEXT: s_movk_i32 s6, 0x8000
-; GFX8-NEXT: v_xor_b32_e32 v2, s6, v2
+; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2
; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v1
; GFX8-NEXT: v_add_u16_e32 v1, v0, v1
; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v0
; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v1
-; GFX8-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16
; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
-; GFX6-NEXT: s_movk_i32 s4, 0x7fff
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3
-; GFX6-NEXT: v_min_i32_e32 v1, s4, v1
-; GFX6-NEXT: s_movk_i32 s5, 0x8000
-; GFX6-NEXT: v_min_i32_e32 v0, s4, v0
+; GFX6-NEXT: v_min_i32_e32 v1, 0x7fff, v1
+; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
-; GFX6-NEXT: v_max_i32_e32 v1, s5, v1
-; GFX6-NEXT: v_max_i32_e32 v0, s5, v0
-; GFX6-NEXT: v_min_i32_e32 v2, s4, v2
+; GFX6-NEXT: v_max_i32_e32 v1, 0xffff8000, v1
+; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0
+; GFX6-NEXT: v_min_i32_e32 v2, 0x7fff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX6-NEXT: v_max_i32_e32 v3, s5, v2
+; GFX6-NEXT: v_max_i32_e32 v3, 0xffff8000, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_or_b32_e32 v2, 0xffff0000, v3
; GFX6-NEXT: v_alignbit_b32 v1, v3, v1, 16
; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5
; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v4
; GFX8-NEXT: v_ashrrev_i16_e32 v4, 15, v6
-; GFX8-NEXT: s_movk_i32 s6, 0x8000
-; GFX8-NEXT: v_xor_b32_e32 v4, s6, v4
+; GFX8-NEXT: v_xor_b32_e32 v4, 0xffff8000, v4
; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v3
; GFX8-NEXT: v_add_u16_e32 v3, v1, v3
; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1
; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v3
-; GFX8-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX8-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v2
; GFX8-NEXT: v_add_u16_e32 v2, v0, v2
; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0
; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v2
-; GFX8-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5
-; GFX6-NEXT: s_movk_i32 s4, 0x7fff
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4
-; GFX6-NEXT: v_min_i32_e32 v1, s4, v1
-; GFX6-NEXT: s_movk_i32 s5, 0x8000
-; GFX6-NEXT: v_min_i32_e32 v0, s4, v0
-; GFX6-NEXT: v_max_i32_e32 v1, s5, v1
-; GFX6-NEXT: v_max_i32_e32 v0, s5, v0
-; GFX6-NEXT: s_mov_b32 s6, 0xffff
+; GFX6-NEXT: v_min_i32_e32 v1, 0x7fff, v1
+; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0
+; GFX6-NEXT: v_max_i32_e32 v1, 0xffff8000, v1
+; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0
; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16
; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16
; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s6, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v7
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v6
-; GFX6-NEXT: v_min_i32_e32 v1, s4, v1
-; GFX6-NEXT: v_min_i32_e32 v2, s4, v2
-; GFX6-NEXT: v_max_i32_e32 v1, s5, v1
-; GFX6-NEXT: v_max_i32_e32 v2, s5, v2
+; GFX6-NEXT: v_min_i32_e32 v1, 0x7fff, v1
+; GFX6-NEXT: v_min_i32_e32 v2, 0x7fff, v2
+; GFX6-NEXT: v_max_i32_e32 v1, 0xffff8000, v1
+; GFX6-NEXT: v_max_i32_e32 v2, 0xffff8000, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_and_b32_e32 v2, s6, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5
; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v4
; GFX8-NEXT: v_ashrrev_i16_e32 v4, 15, v6
-; GFX8-NEXT: s_movk_i32 s6, 0x8000
-; GFX8-NEXT: v_xor_b32_e32 v4, s6, v4
+; GFX8-NEXT: v_xor_b32_e32 v4, 0xffff8000, v4
; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v2
; GFX8-NEXT: v_add_u16_e32 v2, v0, v2
; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0
; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v2
-; GFX8-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v5, v4
; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v2
; GFX8-NEXT: v_ashrrev_i16_e32 v2, 15, v5
-; GFX8-NEXT: v_xor_b32_e32 v2, s6, v2
+; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2
; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v3
; GFX8-NEXT: v_add_u16_e32 v3, v1, v3
; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1
; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v3
-; GFX8-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX8-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-NEXT: v_add_i32_e64 v2, s[4:5], v0, v2
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v2
-; GFX6-NEXT: s_brev_b32 s6, 1
-; GFX6-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-NEXT: v_add_i32_e64 v2, s[4:5], v1, v3
; GFX6-NEXT: v_cmp_gt_i32_e32 vcc, 0, v3
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v2
-; GFX6-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v0, v2
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v2
-; GFX8-NEXT: s_brev_b32 s6, 1
-; GFX8-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v1, v3
; GFX8-NEXT: v_cmp_gt_i32_e32 vcc, 0, v3
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v2
-; GFX8-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GCN-NEXT: s_mov_b32 s8, s2
; GCN-NEXT: s_mov_b32 s9, s3
; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; GCN-NEXT: s_mov_b32 s2, 0x4f7ffffe
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GCN-NEXT: v_rcp_iflag_f32_e32 v7, v7
; GCN-NEXT: v_sub_i32_e32 v11, vcc, 0, v3
-; GCN-NEXT: v_mul_f32_e32 v5, s2, v5
-; GCN-NEXT: v_mul_f32_e32 v7, s2, v7
+; GCN-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5
+; GCN-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
; GCN-NEXT: v_cvt_u32_f32_e32 v7, v7
; GCN-NEXT: v_add_i32_e32 v0, vcc, v4, v0
; TONGA-NEXT: s_mov_b32 s8, s2
; TONGA-NEXT: s_mov_b32 s9, s3
; TONGA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; TONGA-NEXT: s_mov_b32 s2, 0x4f7ffffe
; TONGA-NEXT: s_mov_b32 s4, s0
; TONGA-NEXT: s_mov_b32 s5, s1
; TONGA-NEXT: s_waitcnt vmcnt(0)
; TONGA-NEXT: v_rcp_iflag_f32_e32 v5, v5
; TONGA-NEXT: v_rcp_iflag_f32_e32 v7, v7
; TONGA-NEXT: v_sub_u32_e32 v11, vcc, 0, v3
-; TONGA-NEXT: v_mul_f32_e32 v5, s2, v5
-; TONGA-NEXT: v_mul_f32_e32 v7, s2, v7
+; TONGA-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5
+; TONGA-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
; TONGA-NEXT: v_cvt_u32_f32_e32 v5, v5
; TONGA-NEXT: v_cvt_u32_f32_e32 v7, v7
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v4, v0
; GFX9-NEXT: s_mov_b32 s8, s2
; GFX9-NEXT: s_mov_b32 s9, s3
; GFX9-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; GFX9-NEXT: s_mov_b32 s2, 0x4f7ffffe
; GFX9-NEXT: s_mov_b32 s4, s0
; GFX9-NEXT: s_mov_b32 s5, s1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v7
; GFX9-NEXT: v_ashrrev_i32_e32 v8, 31, v0
; GFX9-NEXT: v_ashrrev_i32_e32 v9, 31, v1
-; GFX9-NEXT: v_mul_f32_e32 v6, s2, v6
-; GFX9-NEXT: v_mul_f32_e32 v7, s2, v7
+; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
+; GFX9-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v7
; GFX9-NEXT: v_add_u32_e32 v0, v0, v8
; GCN-NEXT: s_mov_b32 s5, s3
; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
-; GCN-NEXT: s_mov_b32 s2, 0x4f7ffffe
; GCN-NEXT: s_mov_b32 s8, s0
; GCN-NEXT: s_mov_b32 s9, s1
; GCN-NEXT: s_waitcnt vmcnt(1)
; GCN-NEXT: v_ashrrev_i32_e32 v8, 31, v0
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_ashrrev_i32_e32 v11, 31, v5
; GCN-NEXT: v_ashrrev_i32_e32 v9, 31, v4
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v11, v5
; GCN-NEXT: v_add_i32_e32 v4, vcc, v9, v4
-; GCN-NEXT: v_xor_b32_e32 v5, v5, v11
-; GCN-NEXT: v_xor_b32_e32 v15, v8, v9
-; GCN-NEXT: v_xor_b32_e32 v4, v4, v9
-; GCN-NEXT: v_cvt_f32_u32_e32 v9, v5
; GCN-NEXT: v_add_i32_e32 v0, vcc, v8, v0
+; GCN-NEXT: v_xor_b32_e32 v4, v4, v9
+; GCN-NEXT: v_xor_b32_e32 v15, v8, v9
; GCN-NEXT: v_xor_b32_e32 v0, v0, v8
; GCN-NEXT: v_cvt_f32_u32_e32 v8, v4
-; GCN-NEXT: v_rcp_iflag_f32_e32 v9, v9
+; GCN-NEXT: v_sub_i32_e32 v9, vcc, 0, v4
+; GCN-NEXT: v_ashrrev_i32_e32 v11, 31, v5
+; GCN-NEXT: v_rcp_iflag_f32_e32 v8, v8
; GCN-NEXT: v_ashrrev_i32_e32 v13, 31, v6
-; GCN-NEXT: v_add_i32_e32 v6, vcc, v13, v6
; GCN-NEXT: v_ashrrev_i32_e32 v10, 31, v1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v8, v8
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v11, v5
+; GCN-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GCN-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GCN-NEXT: v_add_i32_e32 v6, vcc, v13, v6
+; GCN-NEXT: v_add_i32_e32 v1, vcc, v10, v1
+; GCN-NEXT: v_mul_lo_u32 v9, v9, v8
+; GCN-NEXT: v_xor_b32_e32 v5, v5, v11
; GCN-NEXT: v_xor_b32_e32 v6, v6, v13
-; GCN-NEXT: v_mul_f32_e32 v9, s2, v9
; GCN-NEXT: v_xor_b32_e32 v16, v10, v11
+; GCN-NEXT: v_mul_hi_u32 v9, v8, v9
+; GCN-NEXT: v_xor_b32_e32 v1, v1, v10
+; GCN-NEXT: v_cvt_f32_u32_e32 v10, v5
; GCN-NEXT: v_cvt_f32_u32_e32 v11, v6
-; GCN-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT: v_rcp_iflag_f32_e32 v10, v10
+; GCN-NEXT: v_rcp_iflag_f32_e32 v11, v11
+; GCN-NEXT: v_mul_hi_u32 v8, v0, v8
; GCN-NEXT: v_ashrrev_i32_e32 v12, 31, v2
+; GCN-NEXT: v_mul_f32_e32 v9, 0x4f7ffffe, v10
+; GCN-NEXT: v_mul_f32_e32 v10, 0x4f7ffffe, v11
+; GCN-NEXT: v_mul_lo_u32 v11, v8, v4
+; GCN-NEXT: v_cvt_u32_f32_e32 v9, v9
; GCN-NEXT: v_add_i32_e32 v2, vcc, v12, v2
; GCN-NEXT: v_xor_b32_e32 v17, v12, v13
; GCN-NEXT: v_xor_b32_e32 v2, v2, v12
-; GCN-NEXT: v_mul_f32_e32 v8, s2, v8
; GCN-NEXT: v_sub_i32_e32 v12, vcc, 0, v5
-; GCN-NEXT: v_cvt_u32_f32_e32 v8, v8
-; GCN-NEXT: v_rcp_iflag_f32_e32 v11, v11
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v11
+; GCN-NEXT: v_cvt_u32_f32_e32 v10, v10
; GCN-NEXT: v_mul_lo_u32 v12, v12, v9
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v10, v1
-; GCN-NEXT: v_xor_b32_e32 v1, v1, v10
-; GCN-NEXT: v_sub_i32_e32 v10, vcc, 0, v4
-; GCN-NEXT: v_mul_lo_u32 v10, v10, v8
-; GCN-NEXT: v_mul_hi_u32 v12, v9, v12
-; GCN-NEXT: v_mul_f32_e32 v11, s2, v11
-; GCN-NEXT: v_cvt_u32_f32_e32 v11, v11
-; GCN-NEXT: v_mul_hi_u32 v10, v8, v10
-; GCN-NEXT: v_add_i32_e32 v9, vcc, v12, v9
-; GCN-NEXT: v_sub_i32_e32 v12, vcc, 0, v6
-; GCN-NEXT: v_mul_lo_u32 v12, v12, v11
-; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8
-; GCN-NEXT: v_mul_hi_u32 v8, v0, v8
-; GCN-NEXT: v_mul_hi_u32 v12, v11, v12
+; GCN-NEXT: v_add_i32_e32 v11, vcc, 1, v8
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v4
+; GCN-NEXT: v_cndmask_b32_e64 v8, v8, v11, s[0:1]
+; GCN-NEXT: v_sub_i32_e32 v11, vcc, v0, v4
; GCN-NEXT: v_ashrrev_i32_e32 v14, 31, v7
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v11, s[0:1]
; GCN-NEXT: v_add_i32_e32 v7, vcc, v14, v7
-; GCN-NEXT: v_xor_b32_e32 v7, v7, v14
-; GCN-NEXT: v_cvt_f32_u32_e32 v10, v7
-; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11
-; GCN-NEXT: v_mul_lo_u32 v12, v8, v4
-; GCN-NEXT: v_rcp_iflag_f32_e32 v10, v10
-; GCN-NEXT: v_mul_hi_u32 v9, v1, v9
-; GCN-NEXT: v_mul_hi_u32 v11, v2, v11
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v12
-; GCN-NEXT: v_add_i32_e32 v12, vcc, 1, v8
; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v4
-; GCN-NEXT: v_cndmask_b32_e64 v8, v8, v12, s[0:1]
-; GCN-NEXT: v_sub_i32_e32 v12, vcc, v0, v4
-; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v12, s[0:1]
-; GCN-NEXT: v_mul_f32_e32 v10, s2, v10
-; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v4
-; GCN-NEXT: v_mul_lo_u32 v0, v9, v5
-; GCN-NEXT: v_cvt_u32_f32_e32 v4, v10
-; GCN-NEXT: v_mul_lo_u32 v10, v11, v6
-; GCN-NEXT: v_add_i32_e32 v12, vcc, 1, v8
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, v1, v0
-; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v9
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, 0, v6
+; GCN-NEXT: v_mul_lo_u32 v0, v0, v10
+; GCN-NEXT: v_xor_b32_e32 v4, v7, v14
+; GCN-NEXT: v_mul_hi_u32 v7, v9, v12
+; GCN-NEXT: v_cvt_f32_u32_e32 v12, v4
+; GCN-NEXT: v_mul_hi_u32 v0, v10, v0
+; GCN-NEXT: v_add_i32_e32 v11, vcc, 1, v8
+; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT: v_mul_hi_u32 v7, v1, v7
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v10
+; GCN-NEXT: v_mul_hi_u32 v0, v2, v0
+; GCN-NEXT: v_mul_lo_u32 v10, v7, v5
+; GCN-NEXT: v_rcp_iflag_f32_e32 v12, v12
+; GCN-NEXT: v_sub_i32_e32 v9, vcc, 0, v4
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, v1, v10
+; GCN-NEXT: v_mul_lo_u32 v10, v0, v6
+; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v5
+; GCN-NEXT: v_mul_f32_e32 v12, 0x4f7ffffe, v12
+; GCN-NEXT: v_cvt_u32_f32_e32 v12, v12
; GCN-NEXT: v_sub_i32_e32 v2, vcc, v2, v10
-; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v0, v5
-; GCN-NEXT: v_add_i32_e32 v10, vcc, 1, v11
-; GCN-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[2:3]
-; GCN-NEXT: v_sub_i32_e32 v9, vcc, v0, v5
+; GCN-NEXT: v_add_i32_e32 v10, vcc, 1, v7
+; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v10, s[2:3]
+; GCN-NEXT: v_add_i32_e32 v10, vcc, 1, v0
; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v6
-; GCN-NEXT: v_cndmask_b32_e64 v10, v11, v10, s[4:5]
-; GCN-NEXT: v_sub_i32_e32 v11, vcc, v2, v6
-; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[2:3]
-; GCN-NEXT: v_add_i32_e32 v9, vcc, 1, v1
+; GCN-NEXT: v_cndmask_b32_e64 v10, v0, v10, s[4:5]
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v1, v5
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[2:3]
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, v2, v6
+; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v1, s[4:5]
+; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v7
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5
-; GCN-NEXT: v_cndmask_b32_e64 v8, v8, v12, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v9, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v8, v8, v11, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v7, v1, vcc
; GCN-NEXT: v_xor_b32_e32 v1, v8, v15
; GCN-NEXT: v_xor_b32_e32 v5, v0, v16
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v1, v15
; GCN-NEXT: v_sub_i32_e32 v1, vcc, v5, v16
-; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v7
-; GCN-NEXT: v_mul_lo_u32 v5, v5, v4
-; GCN-NEXT: v_ashrrev_i32_e32 v9, 31, v3
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v9, v3
-; GCN-NEXT: v_mul_hi_u32 v5, v4, v5
-; GCN-NEXT: v_xor_b32_e32 v3, v3, v9
-; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v11, s[4:5]
-; GCN-NEXT: v_add_i32_e32 v8, vcc, 1, v10
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT: v_mul_hi_u32 v4, v3, v4
+; GCN-NEXT: v_mul_lo_u32 v5, v9, v12
+; GCN-NEXT: v_ashrrev_i32_e32 v8, 31, v3
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v8, v3
+; GCN-NEXT: v_mul_hi_u32 v5, v12, v5
+; GCN-NEXT: v_xor_b32_e32 v3, v3, v8
+; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v10
+; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v12
+; GCN-NEXT: v_mul_hi_u32 v5, v3, v5
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6
-; GCN-NEXT: v_cndmask_b32_e32 v2, v10, v8, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v2, v10, v7, vcc
; GCN-NEXT: v_xor_b32_e32 v2, v2, v17
-; GCN-NEXT: v_mul_lo_u32 v5, v4, v7
+; GCN-NEXT: v_mul_lo_u32 v6, v5, v4
; GCN-NEXT: v_sub_i32_e32 v2, vcc, v2, v17
-; GCN-NEXT: v_xor_b32_e32 v6, v9, v14
-; GCN-NEXT: v_sub_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v4
-; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v3, v7
-; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]
-; GCN-NEXT: v_sub_i32_e32 v5, vcc, v3, v7
-; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v4
-; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v7
-; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; GCN-NEXT: v_xor_b32_e32 v3, v3, v6
+; GCN-NEXT: v_xor_b32_e32 v7, v8, v14
; GCN-NEXT: v_sub_i32_e32 v3, vcc, v3, v6
+; GCN-NEXT: v_add_i32_e32 v6, vcc, 1, v5
+; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v3, v4
+; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[0:1]
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, v3, v4
+; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1]
+; GCN-NEXT: v_add_i32_e32 v6, vcc, 1, v5
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v4
+; GCN-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
+; GCN-NEXT: v_xor_b32_e32 v3, v3, v7
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, v3, v7
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; GCN-NEXT: s_endpgm
;
; TONGA-NEXT: s_mov_b32 s5, s3
; TONGA-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
; TONGA-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
-; TONGA-NEXT: s_mov_b32 s2, 0x4f7ffffe
; TONGA-NEXT: s_mov_b32 s8, s0
; TONGA-NEXT: s_mov_b32 s9, s1
; TONGA-NEXT: s_waitcnt vmcnt(1)
; TONGA-NEXT: v_ashrrev_i32_e32 v8, 31, v0
; TONGA-NEXT: s_waitcnt vmcnt(0)
-; TONGA-NEXT: v_ashrrev_i32_e32 v11, 31, v5
; TONGA-NEXT: v_ashrrev_i32_e32 v9, 31, v4
-; TONGA-NEXT: v_add_u32_e32 v5, vcc, v11, v5
; TONGA-NEXT: v_add_u32_e32 v4, vcc, v9, v4
-; TONGA-NEXT: v_xor_b32_e32 v5, v5, v11
-; TONGA-NEXT: v_xor_b32_e32 v15, v8, v9
-; TONGA-NEXT: v_xor_b32_e32 v4, v4, v9
-; TONGA-NEXT: v_cvt_f32_u32_e32 v9, v5
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v8, v0
+; TONGA-NEXT: v_xor_b32_e32 v4, v4, v9
+; TONGA-NEXT: v_xor_b32_e32 v15, v8, v9
; TONGA-NEXT: v_xor_b32_e32 v0, v0, v8
; TONGA-NEXT: v_cvt_f32_u32_e32 v8, v4
-; TONGA-NEXT: v_rcp_iflag_f32_e32 v9, v9
+; TONGA-NEXT: v_sub_u32_e32 v9, vcc, 0, v4
+; TONGA-NEXT: v_ashrrev_i32_e32 v11, 31, v5
+; TONGA-NEXT: v_rcp_iflag_f32_e32 v8, v8
; TONGA-NEXT: v_ashrrev_i32_e32 v13, 31, v6
-; TONGA-NEXT: v_add_u32_e32 v6, vcc, v13, v6
; TONGA-NEXT: v_ashrrev_i32_e32 v10, 31, v1
-; TONGA-NEXT: v_rcp_iflag_f32_e32 v8, v8
+; TONGA-NEXT: v_add_u32_e32 v5, vcc, v11, v5
+; TONGA-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; TONGA-NEXT: v_cvt_u32_f32_e32 v8, v8
+; TONGA-NEXT: v_add_u32_e32 v6, vcc, v13, v6
+; TONGA-NEXT: v_add_u32_e32 v1, vcc, v10, v1
+; TONGA-NEXT: v_mul_lo_u32 v9, v9, v8
+; TONGA-NEXT: v_xor_b32_e32 v5, v5, v11
; TONGA-NEXT: v_xor_b32_e32 v6, v6, v13
-; TONGA-NEXT: v_mul_f32_e32 v9, s2, v9
; TONGA-NEXT: v_xor_b32_e32 v16, v10, v11
+; TONGA-NEXT: v_mul_hi_u32 v9, v8, v9
+; TONGA-NEXT: v_xor_b32_e32 v1, v1, v10
+; TONGA-NEXT: v_cvt_f32_u32_e32 v10, v5
; TONGA-NEXT: v_cvt_f32_u32_e32 v11, v6
-; TONGA-NEXT: v_cvt_u32_f32_e32 v9, v9
+; TONGA-NEXT: v_add_u32_e32 v8, vcc, v9, v8
+; TONGA-NEXT: v_rcp_iflag_f32_e32 v10, v10
+; TONGA-NEXT: v_rcp_iflag_f32_e32 v11, v11
+; TONGA-NEXT: v_mul_hi_u32 v8, v0, v8
; TONGA-NEXT: v_ashrrev_i32_e32 v12, 31, v2
+; TONGA-NEXT: v_mul_f32_e32 v9, 0x4f7ffffe, v10
+; TONGA-NEXT: v_mul_f32_e32 v10, 0x4f7ffffe, v11
+; TONGA-NEXT: v_mul_lo_u32 v11, v8, v4
+; TONGA-NEXT: v_cvt_u32_f32_e32 v9, v9
; TONGA-NEXT: v_add_u32_e32 v2, vcc, v12, v2
; TONGA-NEXT: v_xor_b32_e32 v17, v12, v13
; TONGA-NEXT: v_xor_b32_e32 v2, v2, v12
-; TONGA-NEXT: v_mul_f32_e32 v8, s2, v8
; TONGA-NEXT: v_sub_u32_e32 v12, vcc, 0, v5
-; TONGA-NEXT: v_cvt_u32_f32_e32 v8, v8
-; TONGA-NEXT: v_rcp_iflag_f32_e32 v11, v11
+; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v0, v11
+; TONGA-NEXT: v_cvt_u32_f32_e32 v10, v10
; TONGA-NEXT: v_mul_lo_u32 v12, v12, v9
-; TONGA-NEXT: v_add_u32_e32 v1, vcc, v10, v1
-; TONGA-NEXT: v_xor_b32_e32 v1, v1, v10
-; TONGA-NEXT: v_sub_u32_e32 v10, vcc, 0, v4
-; TONGA-NEXT: v_mul_lo_u32 v10, v10, v8
-; TONGA-NEXT: v_mul_hi_u32 v12, v9, v12
-; TONGA-NEXT: v_mul_f32_e32 v11, s2, v11
-; TONGA-NEXT: v_cvt_u32_f32_e32 v11, v11
-; TONGA-NEXT: v_mul_hi_u32 v10, v8, v10
-; TONGA-NEXT: v_add_u32_e32 v9, vcc, v12, v9
-; TONGA-NEXT: v_sub_u32_e32 v12, vcc, 0, v6
-; TONGA-NEXT: v_mul_lo_u32 v12, v12, v11
-; TONGA-NEXT: v_add_u32_e32 v8, vcc, v10, v8
-; TONGA-NEXT: v_mul_hi_u32 v8, v0, v8
-; TONGA-NEXT: v_mul_hi_u32 v12, v11, v12
+; TONGA-NEXT: v_add_u32_e32 v11, vcc, 1, v8
+; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v4
+; TONGA-NEXT: v_cndmask_b32_e64 v8, v8, v11, s[0:1]
+; TONGA-NEXT: v_sub_u32_e32 v11, vcc, v0, v4
; TONGA-NEXT: v_ashrrev_i32_e32 v14, 31, v7
+; TONGA-NEXT: v_cndmask_b32_e64 v0, v0, v11, s[0:1]
; TONGA-NEXT: v_add_u32_e32 v7, vcc, v14, v7
-; TONGA-NEXT: v_xor_b32_e32 v7, v7, v14
-; TONGA-NEXT: v_cvt_f32_u32_e32 v10, v7
-; TONGA-NEXT: v_add_u32_e32 v11, vcc, v12, v11
-; TONGA-NEXT: v_mul_lo_u32 v12, v8, v4
-; TONGA-NEXT: v_rcp_iflag_f32_e32 v10, v10
-; TONGA-NEXT: v_mul_hi_u32 v9, v1, v9
-; TONGA-NEXT: v_mul_hi_u32 v11, v2, v11
-; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v0, v12
-; TONGA-NEXT: v_add_u32_e32 v12, vcc, 1, v8
-; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v4
-; TONGA-NEXT: v_cndmask_b32_e64 v8, v8, v12, s[0:1]
-; TONGA-NEXT: v_sub_u32_e32 v12, vcc, v0, v4
-; TONGA-NEXT: v_cndmask_b32_e64 v0, v0, v12, s[0:1]
-; TONGA-NEXT: v_mul_f32_e32 v10, s2, v10
; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v4
-; TONGA-NEXT: v_mul_lo_u32 v0, v9, v5
-; TONGA-NEXT: v_cvt_u32_f32_e32 v4, v10
-; TONGA-NEXT: v_mul_lo_u32 v10, v11, v6
-; TONGA-NEXT: v_add_u32_e32 v12, vcc, 1, v8
-; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v1, v0
-; TONGA-NEXT: v_add_u32_e32 v1, vcc, 1, v9
+; TONGA-NEXT: v_sub_u32_e32 v0, vcc, 0, v6
+; TONGA-NEXT: v_mul_lo_u32 v0, v0, v10
+; TONGA-NEXT: v_xor_b32_e32 v4, v7, v14
+; TONGA-NEXT: v_mul_hi_u32 v7, v9, v12
+; TONGA-NEXT: v_cvt_f32_u32_e32 v12, v4
+; TONGA-NEXT: v_mul_hi_u32 v0, v10, v0
+; TONGA-NEXT: v_add_u32_e32 v11, vcc, 1, v8
+; TONGA-NEXT: v_add_u32_e32 v7, vcc, v7, v9
+; TONGA-NEXT: v_mul_hi_u32 v7, v1, v7
+; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v10
+; TONGA-NEXT: v_mul_hi_u32 v0, v2, v0
+; TONGA-NEXT: v_mul_lo_u32 v10, v7, v5
+; TONGA-NEXT: v_rcp_iflag_f32_e32 v12, v12
+; TONGA-NEXT: v_sub_u32_e32 v9, vcc, 0, v4
+; TONGA-NEXT: v_sub_u32_e32 v1, vcc, v1, v10
+; TONGA-NEXT: v_mul_lo_u32 v10, v0, v6
+; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v5
+; TONGA-NEXT: v_mul_f32_e32 v12, 0x4f7ffffe, v12
+; TONGA-NEXT: v_cvt_u32_f32_e32 v12, v12
; TONGA-NEXT: v_sub_u32_e32 v2, vcc, v2, v10
-; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v0, v5
-; TONGA-NEXT: v_add_u32_e32 v10, vcc, 1, v11
-; TONGA-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[2:3]
-; TONGA-NEXT: v_sub_u32_e32 v9, vcc, v0, v5
+; TONGA-NEXT: v_add_u32_e32 v10, vcc, 1, v7
+; TONGA-NEXT: v_cndmask_b32_e64 v7, v7, v10, s[2:3]
+; TONGA-NEXT: v_add_u32_e32 v10, vcc, 1, v0
; TONGA-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v6
-; TONGA-NEXT: v_cndmask_b32_e64 v10, v11, v10, s[4:5]
-; TONGA-NEXT: v_sub_u32_e32 v11, vcc, v2, v6
-; TONGA-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[2:3]
-; TONGA-NEXT: v_add_u32_e32 v9, vcc, 1, v1
+; TONGA-NEXT: v_cndmask_b32_e64 v10, v0, v10, s[4:5]
+; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v1, v5
+; TONGA-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[2:3]
+; TONGA-NEXT: v_sub_u32_e32 v1, vcc, v2, v6
+; TONGA-NEXT: v_cndmask_b32_e64 v2, v2, v1, s[4:5]
+; TONGA-NEXT: v_add_u32_e32 v1, vcc, 1, v7
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5
-; TONGA-NEXT: v_cndmask_b32_e64 v8, v8, v12, s[0:1]
-; TONGA-NEXT: v_cndmask_b32_e32 v0, v1, v9, vcc
+; TONGA-NEXT: v_cndmask_b32_e64 v8, v8, v11, s[0:1]
+; TONGA-NEXT: v_cndmask_b32_e32 v0, v7, v1, vcc
; TONGA-NEXT: v_xor_b32_e32 v1, v8, v15
; TONGA-NEXT: v_xor_b32_e32 v5, v0, v16
; TONGA-NEXT: v_subrev_u32_e32 v0, vcc, v15, v1
; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, v16, v5
-; TONGA-NEXT: v_sub_u32_e32 v5, vcc, 0, v7
-; TONGA-NEXT: v_mul_lo_u32 v5, v5, v4
-; TONGA-NEXT: v_ashrrev_i32_e32 v9, 31, v3
-; TONGA-NEXT: v_add_u32_e32 v3, vcc, v9, v3
-; TONGA-NEXT: v_mul_hi_u32 v5, v4, v5
-; TONGA-NEXT: v_xor_b32_e32 v3, v3, v9
-; TONGA-NEXT: v_cndmask_b32_e64 v2, v2, v11, s[4:5]
-; TONGA-NEXT: v_add_u32_e32 v8, vcc, 1, v10
-; TONGA-NEXT: v_add_u32_e32 v4, vcc, v5, v4
-; TONGA-NEXT: v_mul_hi_u32 v4, v3, v4
+; TONGA-NEXT: v_mul_lo_u32 v5, v9, v12
+; TONGA-NEXT: v_ashrrev_i32_e32 v8, 31, v3
+; TONGA-NEXT: v_add_u32_e32 v3, vcc, v8, v3
+; TONGA-NEXT: v_mul_hi_u32 v5, v12, v5
+; TONGA-NEXT: v_xor_b32_e32 v3, v3, v8
+; TONGA-NEXT: v_add_u32_e32 v7, vcc, 1, v10
+; TONGA-NEXT: v_add_u32_e32 v5, vcc, v5, v12
+; TONGA-NEXT: v_mul_hi_u32 v5, v3, v5
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6
-; TONGA-NEXT: v_cndmask_b32_e32 v2, v10, v8, vcc
+; TONGA-NEXT: v_cndmask_b32_e32 v2, v10, v7, vcc
; TONGA-NEXT: v_xor_b32_e32 v2, v2, v17
-; TONGA-NEXT: v_mul_lo_u32 v5, v4, v7
+; TONGA-NEXT: v_mul_lo_u32 v6, v5, v4
; TONGA-NEXT: v_subrev_u32_e32 v2, vcc, v17, v2
-; TONGA-NEXT: v_xor_b32_e32 v6, v9, v14
-; TONGA-NEXT: v_sub_u32_e32 v3, vcc, v3, v5
-; TONGA-NEXT: v_add_u32_e32 v5, vcc, 1, v4
-; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v3, v7
-; TONGA-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]
-; TONGA-NEXT: v_sub_u32_e32 v5, vcc, v3, v7
-; TONGA-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; TONGA-NEXT: v_add_u32_e32 v5, vcc, 1, v4
-; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v3, v7
-; TONGA-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; TONGA-NEXT: v_xor_b32_e32 v3, v3, v6
-; TONGA-NEXT: v_subrev_u32_e32 v3, vcc, v6, v3
+; TONGA-NEXT: v_xor_b32_e32 v7, v8, v14
+; TONGA-NEXT: v_sub_u32_e32 v3, vcc, v3, v6
+; TONGA-NEXT: v_add_u32_e32 v6, vcc, 1, v5
+; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v3, v4
+; TONGA-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[0:1]
+; TONGA-NEXT: v_sub_u32_e32 v6, vcc, v3, v4
+; TONGA-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1]
+; TONGA-NEXT: v_add_u32_e32 v6, vcc, 1, v5
+; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v3, v4
+; TONGA-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
+; TONGA-NEXT: v_xor_b32_e32 v3, v3, v7
+; TONGA-NEXT: v_subrev_u32_e32 v3, vcc, v7, v3
; TONGA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; TONGA-NEXT: s_endpgm
;
; GFX9-NEXT: s_mov_b32 s5, s3
; GFX9-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
; GFX9-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
-; GFX9-NEXT: s_mov_b32 s2, 0x4f7ffffe
; GFX9-NEXT: s_mov_b32 s8, s0
; GFX9-NEXT: s_mov_b32 s9, s1
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_rcp_iflag_f32_e32 v10, v10
; GFX9-NEXT: v_rcp_iflag_f32_e32 v12, v12
; GFX9-NEXT: v_rcp_iflag_f32_e32 v14, v14
-; GFX9-NEXT: v_mul_f32_e32 v8, s2, v8
+; GFX9-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v8
-; GFX9-NEXT: v_mul_f32_e32 v10, s2, v10
-; GFX9-NEXT: v_mul_f32_e32 v12, s2, v12
+; GFX9-NEXT: v_mul_f32_e32 v10, 0x4f7ffffe, v10
+; GFX9-NEXT: v_mul_f32_e32 v12, 0x4f7ffffe, v12
; GFX9-NEXT: v_cvt_u32_f32_e32 v10, v10
; GFX9-NEXT: v_sub_u32_e32 v9, 0, v4
-; GFX9-NEXT: v_mul_f32_e32 v14, s2, v14
+; GFX9-NEXT: v_mul_f32_e32 v14, 0x4f7ffffe, v14
; GFX9-NEXT: v_cvt_u32_f32_e32 v12, v12
; GFX9-NEXT: v_cvt_u32_f32_e32 v14, v14
; GFX9-NEXT: v_mul_lo_u32 v9, v9, v8
; GCN-NEXT: s_or_b32 s0, s0, 1
; GCN-NEXT: v_mov_b32_e32 v3, s0
; GCN-NEXT: s_mov_b32 s5, s1
-; GCN-NEXT: v_mul_f32_e32 v1, s3, v1
+; GCN-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_mad_f32 v2, -v1, v0, s3
; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1
; GCN-IR-NEXT: s_or_b32 s0, s0, 1
; GCN-IR-NEXT: v_mov_b32_e32 v3, s0
; GCN-IR-NEXT: s_mov_b32 s5, s1
-; GCN-IR-NEXT: v_mul_f32_e32 v1, s3, v1
+; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s3
; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1
; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0
; GCN-NEXT: v_or_b32_e32 v0, 1, v0
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1
-; GCN-NEXT: v_mul_f32_e32 v2, s4, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x41c00000, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mad_f32 v3, -v2, v1, s4
; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v0, 30, v0
; GCN-IR-NEXT: v_or_b32_e32 v0, 1, v0
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1
-; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2
+; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x41c00000, v2
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
; GCN-IR-NEXT: v_mad_f32 v3, -v2, v1, s4
; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0
; GCN-NEXT: v_or_b32_e32 v0, 1, v0
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1
-; GCN-NEXT: v_mul_f32_e32 v2, s4, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x47000000, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mad_f32 v3, -v2, v1, s4
; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v0, 30, v0
; GCN-IR-NEXT: v_or_b32_e32 v0, 1, v0
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1
-; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2
+; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x47000000, v2
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
; GCN-IR-NEXT: v_mad_f32 v3, -v2, v1, s4
; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
; Check that "pulling out" SDWA operands works correctly.
; GCN-LABEL: {{^}}pulled_out_test:
-; NOSDWA-DAG: v_and_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
+; NOSDWA-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xff, v{{[0-9]+}}
; NOSDWA-DAG: v_lshlrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
-; NOSDWA-DAG: v_and_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
+; NOSDWA-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xff, v{{[0-9]+}}
; NOSDWA-DAG: v_lshlrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; NOSDWA-NOT: v_and_b32_sdwa
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
; SI-NEXT: buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
-; SI-NEXT: s_mov_b32 s4, 0xffff
; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; SI-NEXT: v_lshlrev_b32_e32 v0, v2, v0
; SI-NEXT: v_lshlrev_b32_e32 v2, v9, v7
; SI-NEXT: v_lshlrev_b32_e32 v3, v8, v6
-; SI-NEXT: v_and_b32_e32 v1, s4, v1
-; SI-NEXT: v_and_b32_e32 v0, s4, v0
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
; CI-NEXT: buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
-; CI-NEXT: s_mov_b32 s4, 0xffff
; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; CI-NEXT: v_lshlrev_b32_e32 v0, v2, v0
; CI-NEXT: v_lshlrev_b32_e32 v2, v9, v7
; CI-NEXT: v_lshlrev_b32_e32 v3, v8, v6
-; CI-NEXT: v_and_b32_e32 v1, s4, v1
-; CI-NEXT: v_and_b32_e32 v0, s4, v0
+; CI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; CI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; CI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; VI-NEXT: s_mov_b32 s2, 0xff000000
; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v0
; VI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; VI-NEXT: v_and_b32_e32 v4, s2, v4
-; VI-NEXT: v_and_b32_e32 v0, s2, v0
+; VI-NEXT: v_and_b32_e32 v4, 0xff000000, v4
+; VI-NEXT: v_and_b32_e32 v0, 0xff000000, v0
; VI-NEXT: v_or_b32_e32 v1, v1, v4
; VI-NEXT: v_or_b32_e32 v0, v5, v0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
-; CI-NEXT: s_mov_b32 s4, 0xff00
; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v4, 8, v3
; CI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; CI-NEXT: v_and_b32_e32 v4, s4, v4
+; CI-NEXT: v_and_b32_e32 v4, 0xff00, v4
; CI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; CI-NEXT: v_and_b32_e32 v3, s4, v3
+; CI-NEXT: v_and_b32_e32 v3, 0xff00, v3
; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; CI-NEXT: v_or_b32_e32 v3, v3, v4
; CI-NEXT: v_and_b32_e32 v2, 0xff00ff00, v2
; SI-NEXT: s_mov_b32 s8, s2
; SI-NEXT: s_mov_b32 s9, s3
; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; SI-NEXT: s_mov_b32 s2, 0xffff
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_ashr_i32_e32 v0, v0, v6
; SI-NEXT: v_ashr_i32_e32 v2, v4, v2
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v3, s2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_and_b32_e32 v2, s2, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v1, v3, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; CHECK-NEXT: v_bfe_i32 v5, v0, 0, 31
; CHECK-NEXT: s_mov_b32 s4, 0x38e38e39
; CHECK-NEXT: s_mov_b32 s5, 0xc71c71c7
-; CHECK-NEXT: s_brev_b32 s6, -2
-; CHECK-NEXT: s_mov_b32 s7, 0x7ffffffd
+; CHECK-NEXT: s_mov_b32 s6, 0x7ffffffd
; CHECK-NEXT: v_mul_hi_i32 v5, v5, s4
; CHECK-NEXT: v_mul_hi_i32 v4, v4, s4
; CHECK-NEXT: v_mul_hi_i32 v3, v3, s5
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
; CHECK-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT: v_and_b32_e32 v2, s6, v2
-; CHECK-NEXT: v_and_b32_e32 v1, s6, v1
-; CHECK-NEXT: v_and_b32_e32 v0, s6, v0
+; CHECK-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
+; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; CHECK-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 3, v0
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, s7, v1
+; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, s6, v1
; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 3, v2
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: v_mul_f32_e32 v1, s6, v1
+; GCN-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_mad_f32 v2, -v1, v0, s6
; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1
-; GCN-IR-NEXT: v_mul_f32_e32 v1, s6, v1
+; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s6
; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1
; GCN-NEXT: v_ashrrev_i32_e32 v3, 30, v0
; GCN-NEXT: v_or_b32_e32 v3, 1, v3
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1
-; GCN-NEXT: v_mul_f32_e32 v2, s4, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x41c00000, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mad_f32 v4, -v2, v1, s4
; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v3, 30, v0
; GCN-IR-NEXT: v_or_b32_e32 v3, 1, v3
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1
-; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2
+; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x41c00000, v2
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
; GCN-IR-NEXT: v_mad_f32 v4, -v2, v1, s4
; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
; GCN-NEXT: v_ashrrev_i32_e32 v3, 30, v0
; GCN-NEXT: v_or_b32_e32 v3, 1, v3
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1
-; GCN-NEXT: v_mul_f32_e32 v2, s4, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x47000000, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mad_f32 v4, -v2, v1, s4
; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v3, 30, v0
; GCN-IR-NEXT: v_or_b32_e32 v3, 1, v3
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1
-; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2
+; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x47000000, v2
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
; GCN-IR-NEXT: v_mad_f32 v4, -v2, v1, s4
; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT: s_movk_i32 s4, 0x7fff
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_min_i32_e32 v1, s4, v1
-; GFX6-NEXT: s_movk_i32 s5, 0x8000
-; GFX6-NEXT: v_min_i32_e32 v0, s4, v0
-; GFX6-NEXT: v_max_i32_e32 v1, s5, v1
-; GFX6-NEXT: v_max_i32_e32 v0, s5, v0
+; GFX6-NEXT: v_min_i32_e32 v1, 0x7fff, v1
+; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0
+; GFX6-NEXT: v_max_i32_e32 v1, 0xffff8000, v1
+; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v4, v3
; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v2
; GFX8-NEXT: v_ashrrev_i16_e32 v2, 15, v4
-; GFX8-NEXT: s_movk_i32 s6, 0x8000
-; GFX8-NEXT: v_xor_b32_e32 v2, s6, v2
+; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2
; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v1
; GFX8-NEXT: v_sub_u16_e32 v1, v0, v1
; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v0
; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v1
-; GFX8-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16
; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
-; GFX6-NEXT: s_movk_i32 s4, 0x7fff
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
-; GFX6-NEXT: v_min_i32_e32 v1, s4, v1
-; GFX6-NEXT: s_movk_i32 s5, 0x8000
-; GFX6-NEXT: v_min_i32_e32 v0, s4, v0
+; GFX6-NEXT: v_min_i32_e32 v1, 0x7fff, v1
+; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v5
-; GFX6-NEXT: v_max_i32_e32 v1, s5, v1
-; GFX6-NEXT: v_max_i32_e32 v0, s5, v0
-; GFX6-NEXT: s_mov_b32 s6, 0xffff
-; GFX6-NEXT: v_min_i32_e32 v2, s4, v2
+; GFX6-NEXT: v_max_i32_e32 v1, 0xffff8000, v1
+; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0
+; GFX6-NEXT: v_min_i32_e32 v2, 0x7fff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s6, v0
-; GFX6-NEXT: v_max_i32_e32 v3, s5, v2
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT: v_max_i32_e32 v3, 0xffff8000, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT: v_and_b32_e32 v2, s6, v3
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX6-NEXT: v_alignbit_b32 v1, v3, v1, 16
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5
; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v4
; GFX8-NEXT: v_ashrrev_i16_e32 v4, 15, v6
-; GFX8-NEXT: s_movk_i32 s6, 0x8000
-; GFX8-NEXT: v_xor_b32_e32 v4, s6, v4
+; GFX8-NEXT: v_xor_b32_e32 v4, 0xffff8000, v4
; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v3
; GFX8-NEXT: v_sub_u16_e32 v3, v1, v3
; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1
; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v3
-; GFX8-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX8-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v2
; GFX8-NEXT: v_sub_u16_e32 v2, v0, v2
; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0
; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v2
-; GFX8-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5
-; GFX6-NEXT: s_movk_i32 s4, 0x7fff
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
-; GFX6-NEXT: v_min_i32_e32 v1, s4, v1
-; GFX6-NEXT: s_movk_i32 s5, 0x8000
-; GFX6-NEXT: v_min_i32_e32 v0, s4, v0
-; GFX6-NEXT: v_max_i32_e32 v1, s5, v1
-; GFX6-NEXT: v_max_i32_e32 v0, s5, v0
-; GFX6-NEXT: s_mov_b32 s6, 0xffff
+; GFX6-NEXT: v_min_i32_e32 v1, 0x7fff, v1
+; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0
+; GFX6-NEXT: v_max_i32_e32 v1, 0xffff8000, v1
+; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0
; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16
; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16
; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s6, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v3, v7
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
-; GFX6-NEXT: v_min_i32_e32 v1, s4, v1
-; GFX6-NEXT: v_min_i32_e32 v2, s4, v2
-; GFX6-NEXT: v_max_i32_e32 v1, s5, v1
-; GFX6-NEXT: v_max_i32_e32 v2, s5, v2
+; GFX6-NEXT: v_min_i32_e32 v1, 0x7fff, v1
+; GFX6-NEXT: v_min_i32_e32 v2, 0x7fff, v2
+; GFX6-NEXT: v_max_i32_e32 v1, 0xffff8000, v1
+; GFX6-NEXT: v_max_i32_e32 v2, 0xffff8000, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_and_b32_e32 v2, s6, v2
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5
; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v4
; GFX8-NEXT: v_ashrrev_i16_e32 v4, 15, v6
-; GFX8-NEXT: s_movk_i32 s6, 0x8000
-; GFX8-NEXT: v_xor_b32_e32 v4, s6, v4
+; GFX8-NEXT: v_xor_b32_e32 v4, 0xffff8000, v4
; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v2
; GFX8-NEXT: v_sub_u16_e32 v2, v0, v2
; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0
; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v2
-; GFX8-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v5, v4
; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v2
; GFX8-NEXT: v_ashrrev_i16_e32 v2, 15, v5
-; GFX8-NEXT: v_xor_b32_e32 v2, s6, v2
+; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2
; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v3
; GFX8-NEXT: v_sub_u16_e32 v3, v1, v3
; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1
; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v3
-; GFX8-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX8-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-NEXT: v_sub_i32_e64 v2, s[4:5], v0, v2
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v2
-; GFX6-NEXT: s_brev_b32 s6, 1
-; GFX6-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v3
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v2
-; GFX6-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v0, v2
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v2
-; GFX8-NEXT: s_brev_b32 s6, 1
-; GFX8-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v1, v3
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v2
-; GFX8-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v3
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v3
-; GFX6-NEXT: s_brev_b32 s6, 1
-; GFX6-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v4
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v3
-; GFX6-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v2, v5
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v3
-; GFX6-NEXT: v_xor_b32_e32 v2, s6, v2
+; GFX6-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v0, v3
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v3
-; GFX8-NEXT: s_brev_b32 s6, 1
-; GFX8-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v1, v4
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v1
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v3
-; GFX8-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v2, v5
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v2
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v3
-; GFX8-NEXT: v_xor_b32_e32 v2, s6, v2
+; GFX8-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v0, v4
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v4
-; GFX6-NEXT: s_brev_b32 s6, 1
-; GFX6-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v1, v5
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v4
-; GFX6-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v2, v6
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v6
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v4
-; GFX6-NEXT: v_xor_b32_e32 v2, s6, v2
+; GFX6-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v3, v7
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v7
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v4
-; GFX6-NEXT: v_xor_b32_e32 v3, s6, v3
+; GFX6-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v0, v4
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v4
-; GFX8-NEXT: s_brev_b32 s6, 1
-; GFX8-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v1, v5
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v1
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v4
-; GFX8-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v2, v6
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v6
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v2
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v4
-; GFX8-NEXT: v_xor_b32_e32 v2, s6, v2
+; GFX8-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v3, v7
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v7
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v3
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v4
-; GFX8-NEXT: v_xor_b32_e32 v3, s6, v3
+; GFX8-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v0, v8
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v8
-; GFX6-NEXT: s_brev_b32 s6, 1
-; GFX6-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v1, v9
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v9
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v8
-; GFX6-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v2, v10
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v10
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v8
-; GFX6-NEXT: v_xor_b32_e32 v2, s6, v2
+; GFX6-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v3, v11
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v11
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v8
-; GFX6-NEXT: v_xor_b32_e32 v3, s6, v3
+; GFX6-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v4, v12
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v12
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v4
; GFX6-NEXT: v_ashrrev_i32_e32 v4, 31, v8
-; GFX6-NEXT: v_xor_b32_e32 v4, s6, v4
+; GFX6-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v5, v13
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v13
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v5
; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v8
-; GFX6-NEXT: v_xor_b32_e32 v5, s6, v5
+; GFX6-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc
; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v6, v14
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v14
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v6
; GFX6-NEXT: v_ashrrev_i32_e32 v6, 31, v8
-; GFX6-NEXT: v_xor_b32_e32 v6, s6, v6
+; GFX6-NEXT: v_xor_b32_e32 v6, 0x80000000, v6
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc
; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v7, v15
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v15
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v7
; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v8
-; GFX6-NEXT: v_xor_b32_e32 v7, s6, v7
+; GFX6-NEXT: v_xor_b32_e32 v7, 0x80000000, v7
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v0, v8
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v8
-; GFX8-NEXT: s_brev_b32 s6, 1
-; GFX8-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v1, v9
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v9
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v1
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v8
-; GFX8-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v2, v10
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v10
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v2
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v8
-; GFX8-NEXT: v_xor_b32_e32 v2, s6, v2
+; GFX8-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v3, v11
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v11
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v3
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v8
-; GFX8-NEXT: v_xor_b32_e32 v3, s6, v3
+; GFX8-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v4, v12
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v12
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v4
; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v8
-; GFX8-NEXT: v_xor_b32_e32 v4, s6, v4
+; GFX8-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v5, v13
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v13
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v5
; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v8
-; GFX8-NEXT: v_xor_b32_e32 v5, s6, v5
+; GFX8-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc
; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v6, v14
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v14
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v6
; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v8
-; GFX8-NEXT: v_xor_b32_e32 v6, s6, v6
+; GFX8-NEXT: v_xor_b32_e32 v6, 0x80000000, v6
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc
; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v7, v15
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v15
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v7
; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v8
-; GFX8-NEXT: v_xor_b32_e32 v7, s6, v7
+; GFX8-NEXT: v_xor_b32_e32 v7, 0x80000000, v7
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v16
; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v0, v16
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v0
-; GFX6-NEXT: s_brev_b32 s6, 1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v16
-; GFX6-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v1, v17
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v17
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v16
-; GFX6-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc
; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v2, v18
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v18
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v16
-; GFX6-NEXT: v_xor_b32_e32 v2, s6, v2
+; GFX6-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc
; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v3, v19
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v19
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v16
-; GFX6-NEXT: v_xor_b32_e32 v3, s6, v3
+; GFX6-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc
; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v4, v20
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v20
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v4
; GFX6-NEXT: v_ashrrev_i32_e32 v4, 31, v16
-; GFX6-NEXT: v_xor_b32_e32 v4, s6, v4
+; GFX6-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v4, v16, v4, vcc
; GFX6-NEXT: buffer_load_dword v16, off, s[0:3], s32
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v21
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v5
; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v17
-; GFX6-NEXT: v_xor_b32_e32 v5, s6, v5
+; GFX6-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v5, v17, v5, vcc
; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v6, v22
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v22
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v6
; GFX6-NEXT: v_ashrrev_i32_e32 v6, 31, v17
-; GFX6-NEXT: v_xor_b32_e32 v6, s6, v6
+; GFX6-NEXT: v_xor_b32_e32 v6, 0x80000000, v6
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v6, v17, v6, vcc
; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v7, v23
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v23
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v7
; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v17
-; GFX6-NEXT: v_xor_b32_e32 v7, s6, v7
+; GFX6-NEXT: v_xor_b32_e32 v7, 0x80000000, v7
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v7, v17, v7, vcc
; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v8, v24
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v24
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v8
; GFX6-NEXT: v_ashrrev_i32_e32 v8, 31, v17
-; GFX6-NEXT: v_xor_b32_e32 v8, s6, v8
+; GFX6-NEXT: v_xor_b32_e32 v8, 0x80000000, v8
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v9, v25
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v25
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v9
; GFX6-NEXT: v_ashrrev_i32_e32 v9, 31, v17
-; GFX6-NEXT: v_xor_b32_e32 v9, s6, v9
+; GFX6-NEXT: v_xor_b32_e32 v9, 0x80000000, v9
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc
; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v10, v26
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v26
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v10
; GFX6-NEXT: v_ashrrev_i32_e32 v10, 31, v17
-; GFX6-NEXT: v_xor_b32_e32 v10, s6, v10
+; GFX6-NEXT: v_xor_b32_e32 v10, 0x80000000, v10
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v10, v17, v10, vcc
; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v11, v27
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v27
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v11
; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v17
-; GFX6-NEXT: v_xor_b32_e32 v11, s6, v11
+; GFX6-NEXT: v_xor_b32_e32 v11, 0x80000000, v11
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc
; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v12, v28
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v28
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v12
; GFX6-NEXT: v_ashrrev_i32_e32 v12, 31, v17
-; GFX6-NEXT: v_xor_b32_e32 v12, s6, v12
+; GFX6-NEXT: v_xor_b32_e32 v12, 0x80000000, v12
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc
; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v13, v29
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v29
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v13
; GFX6-NEXT: v_ashrrev_i32_e32 v13, 31, v17
-; GFX6-NEXT: v_xor_b32_e32 v13, s6, v13
+; GFX6-NEXT: v_xor_b32_e32 v13, 0x80000000, v13
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc
; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v14, v30
; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v30
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v14
; GFX6-NEXT: v_ashrrev_i32_e32 v14, 31, v17
-; GFX6-NEXT: v_xor_b32_e32 v14, s6, v14
+; GFX6-NEXT: v_xor_b32_e32 v14, 0x80000000, v14
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v14, v17, v14, vcc
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v15, v16
; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v15
; GFX6-NEXT: v_ashrrev_i32_e32 v15, 31, v16
-; GFX6-NEXT: v_xor_b32_e32 v15, s6, v15
+; GFX6-NEXT: v_xor_b32_e32 v15, 0x80000000, v15
; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v16
; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v0, v16
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v0
-; GFX8-NEXT: s_brev_b32 s6, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v16
-; GFX8-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v1, v17
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v17
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v1
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v16
-; GFX8-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc
; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v2, v18
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v18
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v2
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v16
-; GFX8-NEXT: v_xor_b32_e32 v2, s6, v2
+; GFX8-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc
; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v3, v19
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v19
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v3
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v16
-; GFX8-NEXT: v_xor_b32_e32 v3, s6, v3
+; GFX8-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc
; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v4, v20
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v20
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v4
; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v16
-; GFX8-NEXT: v_xor_b32_e32 v4, s6, v4
+; GFX8-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v4, v16, v4, vcc
; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v21
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v5
; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v17
-; GFX8-NEXT: v_xor_b32_e32 v5, s6, v5
+; GFX8-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v5, v17, v5, vcc
; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v6, v22
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v22
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v6
; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v17
-; GFX8-NEXT: v_xor_b32_e32 v6, s6, v6
+; GFX8-NEXT: v_xor_b32_e32 v6, 0x80000000, v6
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v6, v17, v6, vcc
; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v7, v23
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v23
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v7
; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v17
-; GFX8-NEXT: v_xor_b32_e32 v7, s6, v7
+; GFX8-NEXT: v_xor_b32_e32 v7, 0x80000000, v7
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v17, v7, vcc
; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v8, v24
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v24
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v8
; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v17
-; GFX8-NEXT: v_xor_b32_e32 v8, s6, v8
+; GFX8-NEXT: v_xor_b32_e32 v8, 0x80000000, v8
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v9, v25
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v25
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v9
; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v17
-; GFX8-NEXT: v_xor_b32_e32 v9, s6, v9
+; GFX8-NEXT: v_xor_b32_e32 v9, 0x80000000, v9
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc
; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v10, v26
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v26
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v10
; GFX8-NEXT: v_ashrrev_i32_e32 v10, 31, v17
-; GFX8-NEXT: v_xor_b32_e32 v10, s6, v10
+; GFX8-NEXT: v_xor_b32_e32 v10, 0x80000000, v10
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v10, v17, v10, vcc
; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v11, v27
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v27
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v11
; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v17
-; GFX8-NEXT: v_xor_b32_e32 v11, s6, v11
+; GFX8-NEXT: v_xor_b32_e32 v11, 0x80000000, v11
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc
; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v12, v28
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v28
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v12
; GFX8-NEXT: v_ashrrev_i32_e32 v12, 31, v17
-; GFX8-NEXT: v_xor_b32_e32 v12, s6, v12
+; GFX8-NEXT: v_xor_b32_e32 v12, 0x80000000, v12
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc
; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v13, v29
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v29
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v13
; GFX8-NEXT: v_ashrrev_i32_e32 v13, 31, v17
-; GFX8-NEXT: v_xor_b32_e32 v13, s6, v13
+; GFX8-NEXT: v_xor_b32_e32 v13, 0x80000000, v13
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc
; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v14, v30
; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v30
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v14
; GFX8-NEXT: v_ashrrev_i32_e32 v14, 31, v17
-; GFX8-NEXT: v_xor_b32_e32 v14, s6, v14
+; GFX8-NEXT: v_xor_b32_e32 v14, 0x80000000, v14
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v14, v17, v14, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v15, v16
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v15
; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v16
-; GFX8-NEXT: v_xor_b32_e32 v15, s6, v15
+; GFX8-NEXT: v_xor_b32_e32 v15, 0x80000000, v15
; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v0
; GFX9-NEXT: v_fma_f16 v1, v1, v3, v5
; GFX9-NEXT: v_fma_f16 v0, v0, v2, v4
-; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX9-NEXT: v_fma_f16 v7, v9, v8, v7
-; GFX9-NEXT: v_and_b32_e32 v0, v2, v0
-; GFX9-NEXT: v_and_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-NEXT: v_lshl_or_b32 v0, v7, 16, v0
; GFX9-NEXT: v_lshl_or_b32 v1, v6, 16, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: v_pk_sub_i16 v2, v2, v3
-; GFX9-NEXT: v_and_b32_e32 v0, v4, v2
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v2
; GFX9-NEXT: v_and_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-NEXT: v_mov_b32_e32 v3, v1
; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX6-LABEL: v_uaddsat_i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_movk_i32 s4, 0xff
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
+; GFX6-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_uaddsat_i8:
; GFX6-LABEL: v_uaddsat_i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
+; GFX6-NEXT: v_min_u32_e32 v0, 0xffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_uaddsat_i16:
; GFX6-LABEL: v_uaddsat_v2i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_min_u32_e32 v1, s4, v1
-; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
+; GFX6-NEXT: v_min_u32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_min_u32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-LABEL: v_uaddsat_v3i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_and_b32_e32 v5, s4, v5
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
-; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3
-; GFX6-NEXT: v_min_u32_e32 v1, s4, v1
+; GFX6-NEXT: v_min_u32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
-; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
+; GFX6-NEXT: v_min_u32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_min_u32_e32 v3, s4, v2
+; GFX6-NEXT: v_min_u32_e32 v3, 0xffff, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_or_b32_e32 v2, 0xffff0000, v3
; GFX6-NEXT: v_alignbit_b32 v1, v3, v1, 16
; GFX6-LABEL: v_uaddsat_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v5, s4, v5
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4
-; GFX6-NEXT: v_min_u32_e32 v1, s4, v1
-; GFX6-NEXT: v_and_b32_e32 v7, s4, v7
-; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
-; GFX6-NEXT: v_and_b32_e32 v6, s4, v6
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
-; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
+; GFX6-NEXT: v_min_u32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX6-NEXT: v_min_u32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v6
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v7
-; GFX6-NEXT: v_min_u32_e32 v2, s4, v2
-; GFX6-NEXT: v_min_u32_e32 v1, s4, v1
+; GFX6-NEXT: v_min_u32_e32 v2, 0xffff, v2
+; GFX6-NEXT: v_min_u32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: s_mov_b32 s8, s2
; SI-NEXT: s_mov_b32 s9, s3
; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; SI-NEXT: s_mov_b32 s2, 0x4f7ffffe
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_rcp_iflag_f32_e32 v4, v4
; SI-NEXT: v_rcp_iflag_f32_e32 v5, v5
; SI-NEXT: v_sub_i32_e32 v7, vcc, 0, v3
-; SI-NEXT: v_mul_f32_e32 v4, s2, v4
-; SI-NEXT: v_mul_f32_e32 v5, s2, v5
+; SI-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
+; SI-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5
; SI-NEXT: v_cvt_u32_f32_e32 v4, v4
; SI-NEXT: v_cvt_u32_f32_e32 v5, v5
; SI-NEXT: v_mul_lo_u32 v6, v6, v4
; VI-NEXT: s_mov_b32 s8, s2
; VI-NEXT: s_mov_b32 s9, s3
; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; VI-NEXT: s_mov_b32 s2, 0x4f7ffffe
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_rcp_iflag_f32_e32 v4, v4
; VI-NEXT: v_rcp_iflag_f32_e32 v5, v5
; VI-NEXT: v_sub_u32_e32 v7, vcc, 0, v3
-; VI-NEXT: v_mul_f32_e32 v4, s2, v4
-; VI-NEXT: v_mul_f32_e32 v5, s2, v5
+; VI-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
+; VI-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5
; VI-NEXT: v_cvt_u32_f32_e32 v4, v4
; VI-NEXT: v_cvt_u32_f32_e32 v5, v5
; VI-NEXT: v_mul_lo_u32 v6, v6, v4
; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: v_mov_b32_e32 v1, s3
; GCN-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
-; GCN-NEXT: s_mov_b32 s2, 0x4f7ffffe
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2
; GCN-NEXT: v_cvt_f32_u32_e32 v5, v3
; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v5
-; GCN-NEXT: v_mul_f32_e32 v4, s2, v4
+; GCN-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
; GCN-NEXT: v_cvt_u32_f32_e32 v6, v4
-; GCN-NEXT: v_mul_f32_e32 v5, s2, v5
+; GCN-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5
; GCN-NEXT: v_cvt_u32_f32_e32 v7, v5
; GCN-NEXT: v_sub_u32_e32 v4, vcc, 0, v2
; GCN-NEXT: v_mul_lo_u32 v5, v4, v6
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0 offset:16
; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0
-; SI-NEXT: s_mov_b32 s2, 0x4f7ffffe
; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_rcp_iflag_f32_e32 v10, v10
; SI-NEXT: v_rcp_iflag_f32_e32 v12, v12
; SI-NEXT: v_rcp_iflag_f32_e32 v14, v14
-; SI-NEXT: v_mul_f32_e32 v8, s2, v8
-; SI-NEXT: v_mul_f32_e32 v10, s2, v10
-; SI-NEXT: v_mul_f32_e32 v12, s2, v12
-; SI-NEXT: v_mul_f32_e32 v14, s2, v14
+; SI-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; SI-NEXT: v_mul_f32_e32 v10, 0x4f7ffffe, v10
+; SI-NEXT: v_mul_f32_e32 v12, 0x4f7ffffe, v12
+; SI-NEXT: v_mul_f32_e32 v14, 0x4f7ffffe, v14
; SI-NEXT: v_cvt_u32_f32_e32 v8, v8
; SI-NEXT: v_cvt_u32_f32_e32 v10, v10
; SI-NEXT: v_cvt_u32_f32_e32 v12, v12
; VI-NEXT: s_mov_b32 s5, s3
; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0 offset:16
; VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0
-; VI-NEXT: s_mov_b32 s2, 0x4f7ffffe
; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_rcp_iflag_f32_e32 v10, v10
; VI-NEXT: v_rcp_iflag_f32_e32 v12, v12
; VI-NEXT: v_rcp_iflag_f32_e32 v14, v14
-; VI-NEXT: v_mul_f32_e32 v8, s2, v8
-; VI-NEXT: v_mul_f32_e32 v10, s2, v10
-; VI-NEXT: v_mul_f32_e32 v12, s2, v12
-; VI-NEXT: v_mul_f32_e32 v14, s2, v14
+; VI-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; VI-NEXT: v_mul_f32_e32 v10, 0x4f7ffffe, v10
+; VI-NEXT: v_mul_f32_e32 v12, 0x4f7ffffe, v12
+; VI-NEXT: v_mul_f32_e32 v14, 0x4f7ffffe, v14
; VI-NEXT: v_cvt_u32_f32_e32 v8, v8
; VI-NEXT: v_cvt_u32_f32_e32 v10, v10
; VI-NEXT: v_cvt_u32_f32_e32 v12, v12
; GCN-NEXT: v_mov_b32_e32 v5, s3
; GCN-NEXT: v_mov_b32_e32 v4, s2
; GCN-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
-; GCN-NEXT: s_mov_b32 s2, 0x4f7ffffe
; GCN-NEXT: v_mov_b32_e32 v8, s0
; GCN-NEXT: v_mov_b32_e32 v9, s1
; GCN-NEXT: s_waitcnt vmcnt(1)
; GCN-NEXT: v_rcp_iflag_f32_e32 v12, v12
; GCN-NEXT: v_rcp_iflag_f32_e32 v14, v14
; GCN-NEXT: v_rcp_iflag_f32_e32 v16, v16
-; GCN-NEXT: v_mul_f32_e32 v10, s2, v10
-; GCN-NEXT: v_mul_f32_e32 v12, s2, v12
-; GCN-NEXT: v_mul_f32_e32 v14, s2, v14
-; GCN-NEXT: v_mul_f32_e32 v16, s2, v16
+; GCN-NEXT: v_mul_f32_e32 v10, 0x4f7ffffe, v10
+; GCN-NEXT: v_mul_f32_e32 v12, 0x4f7ffffe, v12
+; GCN-NEXT: v_mul_f32_e32 v14, 0x4f7ffffe, v14
+; GCN-NEXT: v_mul_f32_e32 v16, 0x4f7ffffe, v16
; GCN-NEXT: v_cvt_u32_f32_e32 v10, v10
; GCN-NEXT: v_cvt_u32_f32_e32 v12, v12
; GCN-NEXT: v_cvt_u32_f32_e32 v14, v14
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
-; GCN-NEXT: v_mul_f32_e32 v1, s4, v1
+; GCN-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
; GCN-NEXT: v_mad_f32 v1, -v1, v0, s4
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
-; GCN-IR-NEXT: v_mul_f32_e32 v1, s4, v1
+; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s4
; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0
; GCN-NEXT: s_mov_b32 s4, 0x41c00000
; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
-; GCN-NEXT: v_mul_f32_e32 v1, s4, v1
+; GCN-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
; GCN-NEXT: v_mad_f32 v1, -v1, v0, s4
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0
; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
-; GCN-IR-NEXT: v_mul_f32_e32 v1, s4, v1
+; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s4
; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0
; GCN-NEXT: s_mov_b32 s4, 0x47000000
; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
-; GCN-NEXT: v_mul_f32_e32 v1, s4, v1
+; GCN-NEXT: v_mul_f32_e32 v1, 0x47000000, v1
; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
; GCN-NEXT: v_mad_f32 v1, -v1, v0, s4
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0
; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
-; GCN-IR-NEXT: v_mul_f32_e32 v1, s4, v1
+; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x47000000, v1
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s4
; GFX6-LABEL: test_udivrem_v2:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
-; GFX6-NEXT: s_mov_b32 s2, 0x4f7ffffe
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s7
+; GFX6-NEXT: s_sub_i32 s2, 0, s6
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX6-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, s2, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: s_sub_i32 s2, 0, s6
; GFX6-NEXT: v_mul_lo_u32 v2, s2, v0
; GFX6-NEXT: s_sub_i32 s2, 0, s7
; GFX6-NEXT: v_mul_lo_u32 v3, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
-; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1
+; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s7
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s6, v0
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s6, v0
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s7, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s6, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s7, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s7, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX8-LABEL: test_udivrem_v2:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
-; GFX8-NEXT: s_mov_b32 s2, 0x4f7ffffe
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s7
+; GFX8-NEXT: s_sub_i32 s2, 0, s6
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX8-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_f32_e32 v1, s2, v1
+; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX8-NEXT: s_sub_i32 s2, 0, s6
; GFX8-NEXT: v_mul_lo_u32 v2, s2, v0
; GFX8-NEXT: s_sub_i32 s2, 0, s7
; GFX8-NEXT: v_mul_lo_u32 v3, s2, v1
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s7, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s6, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s7, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-LABEL: test_udivrem_v4:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
-; GFX6-NEXT: s_mov_b32 s13, 0x4f7ffffe
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
-; GFX6-NEXT: s_sub_i32 s2, 0, s8
-; GFX6-NEXT: s_sub_i32 s12, 0, s9
+; GFX6-NEXT: s_sub_i32 s12, 0, s8
+; GFX6-NEXT: s_sub_i32 s13, 0, s9
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s10
; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s11
-; GFX6-NEXT: v_mul_f32_e32 v0, s13, v0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, s13, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX6-NEXT: v_mul_lo_u32 v2, s2, v0
-; GFX6-NEXT: s_mov_b32 s2, -1
-; GFX6-NEXT: v_mul_lo_u32 v4, s12, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, s12, v0
+; GFX6-NEXT: v_mul_lo_u32 v4, s13, v1
; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v4, v1
; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s8
-; GFX6-NEXT: v_mul_f32_e32 v2, s13, v3
+; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s9
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v5
; GFX6-NEXT: s_sub_i32 s4, 0, s11
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT: v_mul_f32_e32 v3, s13, v4
+; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v4
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s9, v1
; GFX6-NEXT: v_mul_hi_u32 v2, s6, v2
; GFX8-LABEL: test_udivrem_v4:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
-; GFX8-NEXT: s_mov_b32 s12, 0x4f7ffffe
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX8-NEXT: v_cvt_f32_u32_e32 v3, s10
; GFX8-NEXT: v_cvt_f32_u32_e32 v5, s11
-; GFX8-NEXT: v_mul_f32_e32 v0, s12, v0
+; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_f32_e32 v1, s12, v1
+; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX8-NEXT: v_mul_lo_u32 v2, s2, v0
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v4, v1
; GFX8-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX8-NEXT: v_mul_lo_u32 v0, v0, s8
-; GFX8-NEXT: v_mul_f32_e32 v2, s12, v3
+; GFX8-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v3
; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX8-NEXT: v_mul_lo_u32 v1, v1, s9
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s8, v0
+; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s8, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: v_mul_lo_u32 v3, s2, v2
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s9, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
; GFX8-NEXT: v_mul_hi_u32 v3, v2, v3
; GFX8-NEXT: v_rcp_iflag_f32_e32 v4, v5
; GFX8-NEXT: s_sub_i32 s2, 0, s11
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2
-; GFX8-NEXT: v_mul_f32_e32 v3, s12, v4
+; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v4
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s9, v1
; GFX8-NEXT: v_mul_hi_u32 v2, s6, v2
; CHECK-LABEL: test_urem_odd:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: s_movk_i32 s4, 0x1fff
-; CHECK-NEXT: s_movk_i32 s5, 0x667
-; CHECK-NEXT: v_and_b32_e32 v0, s4, v0
+; CHECK-NEXT: v_and_b32_e32 v0, 0x1fff, v0
+; CHECK-NEXT: s_movk_i32 s4, 0x667
; CHECK-NEXT: v_mul_u32_u24_e32 v0, 0xccd, v0
-; CHECK-NEXT: v_and_b32_e32 v0, s4, v0
-; CHECK-NEXT: v_cmp_gt_u32_e32 vcc, s5, v0
+; CHECK-NEXT: v_and_b32_e32 v0, 0x1fff, v0
+; CHECK-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31]
%urem = urem i13 %X, 5
; CHECK-LABEL: test_urem_negative_odd:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: s_movk_i32 s4, 0x1ff
-; CHECK-NEXT: v_and_b32_e32 v0, s4, v0
+; CHECK-NEXT: v_and_b32_e32 v0, 0x1ff, v0
; CHECK-NEXT: v_mul_u32_u24_e32 v0, 0x133, v0
-; CHECK-NEXT: v_and_b32_e32 v0, s4, v0
+; CHECK-NEXT: v_and_b32_e32 v0, 0x1ff, v0
; CHECK-NEXT: v_cmp_lt_u32_e32 vcc, 1, v0
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31]
; CHECK-LABEL: test_urem_vec:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: s_movk_i32 s4, 0x7ff
-; CHECK-NEXT: s_mov_b32 s5, 0x8311eb33
-; CHECK-NEXT: s_mov_b32 s6, 0x20140c
-; CHECK-NEXT: s_mov_b32 s7, 0xb6db6db7
-; CHECK-NEXT: s_mov_b32 s8, 0x24924924
-; CHECK-NEXT: s_mov_b32 s9, 0xaaaaaaab
-; CHECK-NEXT: s_mov_b32 s10, 0x2aaaaaaa
-; CHECK-NEXT: v_and_b32_e32 v0, s4, v0
-; CHECK-NEXT: v_and_b32_e32 v1, s4, v1
-; CHECK-NEXT: v_and_b32_e32 v2, s4, v2
-; CHECK-NEXT: v_mul_lo_u32 v2, v2, s5
-; CHECK-NEXT: v_mul_lo_u32 v1, v1, s7
-; CHECK-NEXT: v_mul_lo_u32 v0, v0, s9
+; CHECK-NEXT: v_and_b32_e32 v0, 0x7ff, v0
+; CHECK-NEXT: v_and_b32_e32 v1, 0x7ff, v1
+; CHECK-NEXT: v_and_b32_e32 v2, 0x7ff, v2
+; CHECK-NEXT: s_mov_b32 s4, 0x8311eb33
+; CHECK-NEXT: s_mov_b32 s5, 0x20140c
+; CHECK-NEXT: s_mov_b32 s6, 0xb6db6db7
+; CHECK-NEXT: s_mov_b32 s7, 0x24924924
+; CHECK-NEXT: s_mov_b32 s8, 0xaaaaaaab
+; CHECK-NEXT: s_mov_b32 s9, 0x2aaaaaaa
+; CHECK-NEXT: v_mul_lo_u32 v2, v2, s4
+; CHECK-NEXT: v_mul_lo_u32 v1, v1, s6
+; CHECK-NEXT: v_mul_lo_u32 v0, v0, s8
; CHECK-NEXT: v_add_i32_e32 v2, vcc, 0xf9dc299a, v2
; CHECK-NEXT: v_add_i32_e32 v1, vcc, 0x49249249, v1
; CHECK-NEXT: v_alignbit_b32 v0, v0, v0, 1
-; CHECK-NEXT: v_cmp_lt_u32_e32 vcc, s10, v0
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc, s9, v0
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; CHECK-NEXT: v_cmp_lt_u32_e32 vcc, s8, v1
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc, s7, v1
; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_cmp_lt_u32_e32 vcc, s6, v2
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc, s5, v2
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31]
%urem = urem <3 x i11> %X, <i11 6, i11 7, i11 -5>
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshr_b32 s4, s5, 1
-; GCN-NEXT: s_lshr_b32 s5, s9, 1
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5
-; GCN-NEXT: v_cvt_f32_u32_e32 v2, s4
-; GCN-NEXT: s_lshr_b32 s6, s11, 1
-; GCN-NEXT: v_cvt_f32_u32_e32 v3, s6
-; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v0
-; GCN-NEXT: s_lshr_b32 s7, s7, 1
-; GCN-NEXT: v_cvt_f32_u32_e32 v5, s7
-; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v3
-; GCN-NEXT: v_mul_f32_e32 v4, v2, v4
-; GCN-NEXT: v_trunc_f32_e32 v4, v4
-; GCN-NEXT: v_cvt_u32_f32_e32 v7, v4
-; GCN-NEXT: v_mad_f32 v2, -v4, v0, v2
+; GCN-NEXT: s_lshr_b32 s4, s9, 1
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4
+; GCN-NEXT: s_lshr_b32 s5, s5, 1
+; GCN-NEXT: s_lshr_b32 s6, s7, 1
+; GCN-NEXT: s_lshr_b32 s7, s11, 1
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, s5
+; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GCN-NEXT: v_cvt_f32_u32_e32 v4, s7
+; GCN-NEXT: v_cvt_f32_u32_e32 v5, s6
+; GCN-NEXT: v_mul_f32_e32 v3, v2, v3
+; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v4
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mad_f32 v2, -v3, v0, v2
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0
; GCN-NEXT: v_mul_f32_e32 v2, v5, v6
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v7, vcc
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s5
; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v4, v2
-; GCN-NEXT: v_mad_f32 v2, -v2, v3, v5
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, v2, s6
-; GCN-NEXT: s_brev_b32 s4, -2
-; GCN-NEXT: v_and_b32_e32 v0, s4, v0
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GCN-NEXT: v_mad_f32 v2, -v2, v4, v5
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s4
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GCN-NEXT: v_mul_lo_u32 v2, v2, s7
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
+; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, s6, v2
+; GCN-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
; GCN-NEXT: v_mov_b32_e32 v3, v1
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s7, v2
-; GCN-NEXT: v_and_b32_e32 v2, s4, v2
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NEXT: s_endpgm
;
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: s_lshr_b32 s4, s5, 1
-; GCN-IR-NEXT: s_lshr_b32 s5, s9, 1
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s5
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s4
-; GCN-IR-NEXT: s_lshr_b32 s6, s11, 1
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v3, s6
-; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v0
-; GCN-IR-NEXT: s_lshr_b32 s7, s7, 1
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v5, s7
-; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v6, v3
-; GCN-IR-NEXT: v_mul_f32_e32 v4, v2, v4
-; GCN-IR-NEXT: v_trunc_f32_e32 v4, v4
-; GCN-IR-NEXT: v_cvt_u32_f32_e32 v7, v4
-; GCN-IR-NEXT: v_mad_f32 v2, -v4, v0, v2
+; GCN-IR-NEXT: s_lshr_b32 s4, s9, 1
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4
+; GCN-IR-NEXT: s_lshr_b32 s5, s5, 1
+; GCN-IR-NEXT: s_lshr_b32 s6, s7, 1
+; GCN-IR-NEXT: s_lshr_b32 s7, s11, 1
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s5
+; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v4, s7
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v5, s6
+; GCN-IR-NEXT: v_mul_f32_e32 v3, v2, v3
+; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v6, v4
+; GCN-IR-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-IR-NEXT: v_mad_f32 v2, -v3, v0, v2
+; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v3
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0
; GCN-IR-NEXT: v_mul_f32_e32 v2, v5, v6
-; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v7, vcc
-; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s5
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT: v_cvt_u32_f32_e32 v4, v2
-; GCN-IR-NEXT: v_mad_f32 v2, -v2, v3, v5
-; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
-; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3
-; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
-; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s6
-; GCN-IR-NEXT: s_brev_b32 s4, -2
-; GCN-IR-NEXT: v_and_b32_e32 v0, s4, v0
+; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
+; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GCN-IR-NEXT: v_mad_f32 v2, -v2, v4, v5
+; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
+; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
+; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s7
+; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
+; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s6, v2
+; GCN-IR-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
; GCN-IR-NEXT: v_mov_b32_e32 v3, v1
-; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s7, v2
-; GCN-IR-NEXT: v_and_b32_e32 v2, s4, v2
; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
%1 = lshr <2 x i64> %x, <i64 33, i64 33>
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshr_b32 s4, s5, 1
-; GCN-NEXT: s_lshr_b32 s5, s9, 1
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5
-; GCN-NEXT: v_cvt_f32_u32_e32 v2, s4
-; GCN-NEXT: s_lshr_b32 s6, s11, 9
-; GCN-NEXT: v_cvt_f32_u32_e32 v3, s6
-; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v0
-; GCN-NEXT: s_lshr_b32 s7, s7, 9
-; GCN-NEXT: v_cvt_f32_u32_e32 v5, s7
-; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v3
-; GCN-NEXT: v_mul_f32_e32 v4, v2, v4
-; GCN-NEXT: v_trunc_f32_e32 v4, v4
-; GCN-NEXT: v_cvt_u32_f32_e32 v7, v4
-; GCN-NEXT: v_mad_f32 v2, -v4, v0, v2
+; GCN-NEXT: s_lshr_b32 s4, s9, 1
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4
+; GCN-NEXT: s_lshr_b32 s5, s5, 1
+; GCN-NEXT: s_lshr_b32 s6, s7, 9
+; GCN-NEXT: s_lshr_b32 s7, s11, 9
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, s5
+; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GCN-NEXT: v_cvt_f32_u32_e32 v4, s7
+; GCN-NEXT: v_cvt_f32_u32_e32 v5, s6
+; GCN-NEXT: v_mul_f32_e32 v3, v2, v3
+; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v4
+; GCN-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-NEXT: v_mad_f32 v2, -v3, v0, v2
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0
; GCN-NEXT: v_mul_f32_e32 v2, v5, v6
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v7, vcc
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s5
; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v4, v2
-; GCN-NEXT: v_mad_f32 v2, -v2, v3, v5
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, v2, s6
-; GCN-NEXT: s_brev_b32 s4, -2
-; GCN-NEXT: v_and_b32_e32 v0, s4, v0
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GCN-NEXT: v_mad_f32 v2, -v2, v4, v5
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s4
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GCN-NEXT: v_mul_lo_u32 v2, v2, s7
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
+; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, s6, v2
+; GCN-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
; GCN-NEXT: v_mov_b32_e32 v3, v1
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s7, v2
-; GCN-NEXT: v_and_b32_e32 v2, s4, v2
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NEXT: s_endpgm
;
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: s_lshr_b32 s4, s5, 1
-; GCN-IR-NEXT: s_lshr_b32 s5, s9, 1
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s5
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s4
-; GCN-IR-NEXT: s_lshr_b32 s6, s11, 9
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v3, s6
-; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v0
-; GCN-IR-NEXT: s_lshr_b32 s7, s7, 9
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v5, s7
-; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v6, v3
-; GCN-IR-NEXT: v_mul_f32_e32 v4, v2, v4
-; GCN-IR-NEXT: v_trunc_f32_e32 v4, v4
-; GCN-IR-NEXT: v_cvt_u32_f32_e32 v7, v4
-; GCN-IR-NEXT: v_mad_f32 v2, -v4, v0, v2
+; GCN-IR-NEXT: s_lshr_b32 s4, s9, 1
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4
+; GCN-IR-NEXT: s_lshr_b32 s5, s5, 1
+; GCN-IR-NEXT: s_lshr_b32 s6, s7, 9
+; GCN-IR-NEXT: s_lshr_b32 s7, s11, 9
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s5
+; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v4, s7
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v5, s6
+; GCN-IR-NEXT: v_mul_f32_e32 v3, v2, v3
+; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v6, v4
+; GCN-IR-NEXT: v_trunc_f32_e32 v3, v3
+; GCN-IR-NEXT: v_mad_f32 v2, -v3, v0, v2
+; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v3
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0
; GCN-IR-NEXT: v_mul_f32_e32 v2, v5, v6
-; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v7, vcc
-; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s5
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT: v_cvt_u32_f32_e32 v4, v2
-; GCN-IR-NEXT: v_mad_f32 v2, -v2, v3, v5
-; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
-; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3
-; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
-; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s6
-; GCN-IR-NEXT: s_brev_b32 s4, -2
-; GCN-IR-NEXT: v_and_b32_e32 v0, s4, v0
+; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
+; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GCN-IR-NEXT: v_mad_f32 v2, -v2, v4, v5
+; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
+; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
+; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s7
+; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
+; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s6, v2
+; GCN-IR-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
; GCN-IR-NEXT: v_mov_b32_e32 v3, v1
-; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s7, v2
-; GCN-IR-NEXT: v_and_b32_e32 v2, s4, v2
; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
%1 = lshr <2 x i64> %x, <i64 33, i64 41>
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
-; GCN-NEXT: v_mul_f32_e32 v1, s5, v1
+; GCN-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
; GCN-NEXT: v_mad_f32 v1, -v1, v0, s5
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
-; GCN-IR-NEXT: v_mul_f32_e32 v1, s5, v1
+; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s5
; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0
; GCN-NEXT: s_mov_b32 s4, 0x41c00000
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1
-; GCN-NEXT: v_mul_f32_e32 v2, s4, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x41c00000, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
; GCN-NEXT: v_mad_f32 v2, -v2, v1, s4
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v0
; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1
-; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2
+; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x41c00000, v2
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
; GCN-IR-NEXT: v_mad_f32 v2, -v2, v1, s4
; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0
; GCN-NEXT: s_mov_b32 s4, 0x47000000
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1
-; GCN-NEXT: v_mul_f32_e32 v2, s4, v2
+; GCN-NEXT: v_mul_f32_e32 v2, 0x47000000, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
; GCN-NEXT: v_mad_f32 v2, -v2, v1, s4
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v0
; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1
-; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2
+; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x47000000, v2
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
; GCN-IR-NEXT: v_mad_f32 v2, -v2, v1, s4
; GFX6-LABEL: v_usubsat_i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_movk_i32 s4, 0xff
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-NEXT: v_max_u32_e32 v0, v0, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX6-LABEL: v_usubsat_i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_max_u32_e32 v0, v0, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX6-LABEL: v_usubsat_v2i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v3
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_max_u32_e32 v1, v1, v4
; GFX6-NEXT: v_max_u32_e32 v0, v0, v2
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; GFX6-LABEL: v_usubsat_v3i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v6, s4, v4
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v4
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_max_u32_e32 v1, v1, v6
; GFX6-NEXT: v_max_u32_e32 v0, v0, v3
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
-; GFX6-NEXT: v_and_b32_e32 v5, s4, v5
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-LABEL: v_usubsat_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v9, s4, v5
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_and_b32_e32 v9, 0xffff, v5
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_max_u32_e32 v1, v1, v9
; GFX6-NEXT: v_max_u32_e32 v0, v0, v4
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5
-; GFX6-NEXT: v_and_b32_e32 v8, s4, v7
-; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
-; GFX6-NEXT: v_and_b32_e32 v6, s4, v6
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v7
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
-; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v1, v2, v0
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshl_or_b32 v1, v0, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v0, v2, v3
-; GFX9-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: shuffle_v4f16_1100:
; GFX9-NEXT: ; kill: killed $vgpr0 killed $vgpr1
; GFX9-NEXT: v_mov_b32_e32 v0, 0xffff
; GFX9-NEXT: ; kill: killed $vgpr2 killed $vgpr3
-; GFX9-NEXT: v_and_b32_e32 v1, v0, v4
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_and_b32_sdwa v2, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-NEXT: v_lshl_or_b32 v0, v5, 16, v1