LoongArch: update test cases about TLS

diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c
index 4035ea2..b6e62f0 100644 (file)
--- a/bfd/elfnn-loongarch.c
+++ b/bfd/elfnn-loongarch.c
@@ -145,14 +145,12 @@ struct loongarch_elf_link_hash_table
 #define elf_backend_rela_normal 1
 #define elf_backend_default_execstack 0
 
-#define IS_LOONGARCH_TLS_DESC_RELOC(R_TYPE)    \
-  ((R_TYPE) == R_LARCH_TLS_DESC_PC_HI20        \
-   || (R_TYPE) == R_LARCH_TLS_DESC_PC_LO12  \
-   || (R_TYPE) == R_LARCH_TLS_DESC_LD \
-   || (R_TYPE) == R_LARCH_TLS_DESC_CALL)
-
-#define IS_LOONGARCH_TLS_IE_RELOC(R_TYPE) \
-  ((R_TYPE) == R_LARCH_TLS_IE_PC_HI20 \
+#define IS_LOONGARCH_TLS_TRANS_RELOC(R_TYPE)  \
+  ((R_TYPE) == R_LARCH_TLS_DESC_PC_HI20              \
+   || (R_TYPE) == R_LARCH_TLS_DESC_PC_LO12    \
+   || (R_TYPE) == R_LARCH_TLS_DESC_LD        \
+   || (R_TYPE) == R_LARCH_TLS_DESC_CALL              \
+   || (R_TYPE) == R_LARCH_TLS_IE_PC_HI20      \
    || (R_TYPE) == R_LARCH_TLS_IE_PC_LO12)
 
 /* Generate a PLT header.  */
@@ -642,15 +640,20 @@ loongarch_reloc_got_type (unsigned int r_type)
 
 /* Return true if tls type transition can be performed.  */
 static bool
-loongarch_can_relax_tls (struct bfd_link_info *info, unsigned int r_type,
-                        struct elf_link_hash_entry *h, bfd *input_bfd,
-                        unsigned long r_symndx)
+loongarch_can_trans_tls (bfd *input_bfd,
+                         struct bfd_link_info *info,
+                         struct elf_link_hash_entry *h,
+                         const Elf_Internal_Rela *rel,
+                         unsigned int r_type)
 {
   char symbol_tls_type;
   unsigned int reloc_got_type;
+  unsigned int r_symndx = ELFNN_R_SYM (rel->r_info);
 
-  if (! (IS_LOONGARCH_TLS_DESC_RELOC (r_type)
-        || IS_LOONGARCH_TLS_IE_RELOC (r_type)))
+  /* Only TLS DESC/IE in normal code mode will perform type
+     transition.  */
+  if (! (IS_LOONGARCH_TLS_TRANS_RELOC (r_type)
+         && ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX))
     return false;
 
   symbol_tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx);
@@ -707,11 +710,13 @@ loongarch_tls_transition_without_check (struct bfd_link_info *info,
 }
 
 static unsigned int
-loongarch_tls_transition (struct bfd_link_info *info, unsigned int r_type,
-                         struct elf_link_hash_entry *h, bfd *input_bfd,
-                         unsigned long r_symndx)
+loongarch_tls_transition (bfd *input_bfd,
+                         struct bfd_link_info *info,
+                         struct elf_link_hash_entry *h,
+                         const Elf_Internal_Rela *rel,
+                         unsigned int r_type)
 {
-  if (! loongarch_can_relax_tls (info, r_type, h, input_bfd,r_symndx))
+  if (! loongarch_can_trans_tls (input_bfd, info, h, rel, r_type))
     return r_type;
 
   return loongarch_tls_transition_without_check (info, r_type, h);
@@ -818,7 +823,10 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
       int need_dynreloc = 0;
       int only_need_pcrel = 0;
 
-      r_type = loongarch_tls_transition (info, r_type, h, abfd, r_symndx);
+      /* Type transitions are only possible with relocations accompanied
+        by R_LARCH_RELAX.  */
+      if (rel + 1 != relocs + sec->reloc_count)
+       r_type = loongarch_tls_transition (abfd, info, h, rel, r_type);
       switch (r_type)
        {
        case R_LARCH_GOT_PC_HI20:
@@ -2538,7 +2546,7 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info,
 
 /* Transition instruction sequence to relax instruction sequence.  */
 static bool
-loongarch_tls_relax (bfd *abfd, asection *sec, Elf_Internal_Rela *rel,
+loongarch_tls_perform_trans (bfd *abfd, asection *sec, Elf_Internal_Rela *rel,
                    int r_type, struct elf_link_hash_entry *h,
                    struct bfd_link_info *info)
 {
@@ -2659,7 +2667,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
       const char *name;
       bfd_reloc_status_type r = bfd_reloc_ok;
       bool is_ie, is_desc, is_undefweak, unresolved_reloc, defined_local;
-      unsigned int relaxed_r_type;
+      unsigned int trans_r_type = r_type;
       bool resolved_local, resolved_dynly, resolved_to_const;
       char tls_type;
       bfd_vma relocation, off, ie_off, desc_off;
@@ -2791,14 +2799,17 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 
       BFD_ASSERT (!resolved_local || defined_local);
 
-      relaxed_r_type = loongarch_tls_transition (info, r_type, h, input_bfd, r_symndx);
-      if (relaxed_r_type != r_type)
+      if (rel + 1 != relend)
+       trans_r_type = loongarch_tls_transition (input_bfd, info, h,
+                                               rel, r_type);
+      if (trans_r_type != r_type)
       {
-       howto = loongarch_elf_rtype_to_howto (input_bfd, relaxed_r_type);
+       howto = loongarch_elf_rtype_to_howto (input_bfd, trans_r_type);
        BFD_ASSERT (howto != NULL);
 
-       if (loongarch_tls_relax (input_bfd, input_section, rel, r_type, h, info))
-         r_type = relaxed_r_type;
+       if (loongarch_tls_perform_trans (input_bfd, input_section,
+                                       rel, r_type, h, info))
+         r_type = trans_r_type;
       }
 
       is_desc = false;
@@ -4553,7 +4564,8 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
              || R_LARCH_TLS_GD_PC_HI20 == r_type
              || R_LARCH_TLS_DESC_PC_HI20 == r_type)
            {
-             if (loongarch_can_relax_tls (info, r_type, h, abfd, r_symndx))
+             if (i + 1 != sec->reloc_count
+                 && loongarch_can_trans_tls (abfd, info, h, rel, r_type))
                continue;
              else
                {
@@ -4597,7 +4609,8 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
              || R_LARCH_TLS_GD_PC_HI20 == r_type
              || R_LARCH_TLS_DESC_PC_HI20 == r_type)
            {
-             if (loongarch_can_relax_tls (info, r_type, h, abfd, r_symndx))
+             if (i + 1 != sec->reloc_count
+                 && loongarch_can_trans_tls (abfd, info, h, rel, r_type))
                continue;
              else
                {

diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
index e0aff36..af4426b 100644 (file)
--- a/gas/config/tc-loongarch.c
+++ b/gas/config/tc-loongarch.c
@@ -724,8 +724,12 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
                }
 
              /* Only one register macros (used in normal code model)
-                emit R_LARCH_RELAX.  */
+                emit R_LARCH_RELAX.
+                LARCH_opts.ase_labs and LARCH_opts.ase_gabs are used
+                to generate the code model of absolute addresses, and
+                we do not relax this code model.  */
              if (LARCH_opts.relax && (ip->expand_from_macro & 1)
+                   && ! (LARCH_opts.ase_labs | LARCH_opts.ase_gabs)
                    && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_type
                        || BFD_RELOC_LARCH_PCALA_LO12 == reloc_type
                        || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_type
@@ -733,7 +737,11 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
                        || BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_type
                        || BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_type
                        || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_type
-                       || BFD_RELOC_LARCH_TLS_DESC_PC_LO12 == reloc_type))
+                       || BFD_RELOC_LARCH_TLS_DESC_PC_LO12 == reloc_type
+                       || BFD_RELOC_LARCH_TLS_DESC_LD == reloc_type
+                       || BFD_RELOC_LARCH_TLS_DESC_CALL == reloc_type
+                       || BFD_RELOC_LARCH_TLS_IE_PC_HI20 == reloc_type
+                       || BFD_RELOC_LARCH_TLS_IE_PC_LO12 == reloc_type))
                {
                  ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX;
                  ip->reloc_info[ip->reloc_num].value = const_0;
@@ -1088,7 +1096,12 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip)
          || BFD_RELOC_LARCH_TLS_LE_ADD_R == reloc_info[0].type
          || BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_info[0].type
          || BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_info[0].type
-         || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_info[0].type))
+         || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_info[0].type
+         || BFD_RELOC_LARCH_TLS_DESC_PC_LO12 == reloc_info[0].type
+         || BFD_RELOC_LARCH_TLS_DESC_LD == reloc_info[0].type
+         || BFD_RELOC_LARCH_TLS_DESC_CALL == reloc_info[0].type
+         || BFD_RELOC_LARCH_TLS_IE_PC_HI20 == reloc_info[0].type
+         || BFD_RELOC_LARCH_TLS_IE_PC_LO12 == reloc_info[0].type))
     {
       frag_wane (frag_now);
       frag_new (0);

diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas/loongarch/macro_op.d
index 47f8f45..9d69643 100644 (file)
--- a/gas/testsuite/gas/loongarch/macro_op.d
+++ b/gas/testsuite/gas/loongarch/macro_op.d
@@ -57,8 +57,10 @@ Disassembly of section .text:
                        4c: R_LARCH_TLS_LE_LO12 TLS1
   50:  1a000004        pcalau12i       \$a0, 0
                        50: R_LARCH_TLS_IE_PC_HI20      TLS1
+                       50: R_LARCH_RELAX       \*ABS\*
   54:  28c00084        ld.d            \$a0, \$a0, 0
                        54: R_LARCH_TLS_IE_PC_LO12      TLS1
+                       54: R_LARCH_RELAX       \*ABS\*
   58:  1a000004        pcalau12i       \$a0, 0
                        58: R_LARCH_TLS_LD_PC_HI20      TLS1
                        58: R_LARCH_RELAX       \*ABS\*

diff --git a/gas/testsuite/gas/loongarch/macro_op_32.d b/gas/testsuite/gas/loongarch/macro_op_32.d
index a7349aa..f8aaacd 100644 (file)
--- a/gas/testsuite/gas/loongarch/macro_op_32.d
+++ b/gas/testsuite/gas/loongarch/macro_op_32.d
@@ -53,8 +53,10 @@ Disassembly of section .text:
                        44: R_LARCH_TLS_LE_LO12 TLS1
   48:  1a000004        pcalau12i       \$a0, 0
                        48: R_LARCH_TLS_IE_PC_HI20      TLS1
+                       48: R_LARCH_RELAX       \*ABS\*
   4c:  28800084        ld.w            \$a0, \$a0, 0
                        4c: R_LARCH_TLS_IE_PC_LO12      TLS1
+                       4c: R_LARCH_RELAX       \*ABS\*
   50:  1a000004        pcalau12i       \$a0, 0
                        50: R_LARCH_TLS_LD_PC_HI20      TLS1
                        50: R_LARCH_RELAX       \*ABS\*

diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d
index 5c823ba..6a81e82 100644 (file)
--- a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d
+++ b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d
@@ -28,10 +28,8 @@ Disassembly of section .text:
                        1c: R_LARCH_ABS64_HI12  .L1
   20:  1a000004        pcalau12i       \$a0, 0
                        20: R_LARCH_PCALA_HI20  .L1
-                       20: R_LARCH_RELAX       \*ABS\*
   24:  02c00084        addi.d          \$a0, \$a0, 0
                        24: R_LARCH_PCALA_LO12  .L1
-                       24: R_LARCH_RELAX       \*ABS\*
   28:  14000004        lu12i.w         \$a0, 0
                        28: R_LARCH_GOT_HI20    .L1
   2c:  03800084        ori             \$a0, \$a0, 0x0

diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32.d b/gas/testsuite/gas/loongarch/tlsdesc_32.d
index eddcc5e..6c9558d 100644 (file)
--- a/gas/testsuite/gas/loongarch/tlsdesc_32.d
+++ b/gas/testsuite/gas/loongarch/tlsdesc_32.d
@@ -23,5 +23,7 @@ Disassembly of section .text:
                        14: R_LARCH_RELAX       \*ABS\*
   18:  28800081        ld.w            \$ra, \$a0, 0
                        18: R_LARCH_TLS_DESC_LD var
+                       18: R_LARCH_RELAX       \*ABS\*
   1c:  4c000021        jirl            \$ra, \$ra, 0
                        1c: R_LARCH_TLS_DESC_CALL       var
+                       1c: R_LARCH_RELAX       \*ABS\*

diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32.s b/gas/testsuite/gas/loongarch/tlsdesc_32.s
index ef6aee9..19d768a 100644 (file)
--- a/gas/testsuite/gas/loongarch/tlsdesc_32.s
+++ b/gas/testsuite/gas/loongarch/tlsdesc_32.s
@@ -8,5 +8,5 @@
        # R_LARCH_TLS_DESC_CALL var
        jirl    $ra,$ra,%desc_call(var)
 
-       # test macro, pcalau12i + addi.w => pcaddi
+       # with R_LARCH_RELAX
        la.tls.desc     $a0,var

diff --git a/gas/testsuite/gas/loongarch/tlsdesc_64.d b/gas/testsuite/gas/loongarch/tlsdesc_64.d
index 2a2829c..8fc9e88 100644 (file)
--- a/gas/testsuite/gas/loongarch/tlsdesc_64.d
+++ b/gas/testsuite/gas/loongarch/tlsdesc_64.d
@@ -24,5 +24,7 @@ Disassembly of section .text:
                        14: R_LARCH_RELAX       \*ABS\*
   18:  28c00081        ld.d            \$ra, \$a0, 0
                        18: R_LARCH_TLS_DESC_LD var
+                       18: R_LARCH_RELAX       \*ABS\*
   1c:  4c000021        jirl            \$ra, \$ra, 0
                        1c: R_LARCH_TLS_DESC_CALL       var
+                       1c: R_LARCH_RELAX       \*ABS\*

diff --git a/gas/testsuite/gas/loongarch/tlsdesc_64.s b/gas/testsuite/gas/loongarch/tlsdesc_64.s
index 9d0ccb1..f515442 100644 (file)
--- a/gas/testsuite/gas/loongarch/tlsdesc_64.s
+++ b/gas/testsuite/gas/loongarch/tlsdesc_64.s
@@ -8,5 +8,5 @@
        # R_LARCH_TLS_DESC_CALL var
        jirl    $ra,$ra,%desc_call(var)
 
-       # test macro, pcalau12i + addi.d => pcaddi
+       # with R_LARCH_RELAX
        la.tls.desc     $a0,var

diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.d b/ld/testsuite/ld-loongarch-elf/desc-ie.d
index 32e3505..8b184a6 100644 (file)
--- a/ld/testsuite/ld-loongarch-elf/desc-ie.d
+++ b/ld/testsuite/ld-loongarch-elf/desc-ie.d
@@ -1,16 +1,29 @@
 #as:
-#ld: -shared -z norelro -e 0x0 --hash-style=both
+#ld: -shared -z norelro -e0 --hash-style=both
 #objdump: -dr
 #skip: loongarch32-*-*
 
 .*:     file format .*
 
+
 Disassembly of section .text:
 
-0+230 <fn1>:
- 230:  1a000084        pcalau12i       \$a0, 4
- 234:  28cd6084        ld.d            \$a0, \$a0, 856
- 238:  03400000        nop.*
- 23c:  03400000        nop.*
- 240:  1a000084        pcalau12i       \$a0, 4
- 244:  28cd6081        ld.d            \$ra, \$a0, 856
+[0-9a-f]+ <fn1>:
+ +[0-9a-f]+:   1a000084        pcalau12i       \$a0, .*
+ +[0-9a-f]+:   28ce2084        ld.d            \$a0, \$a0, .*
+ +[0-9a-f]+:   03400000        nop
+ +[0-9a-f]+:   03400000        nop
+ +[0-9a-f]+:   1a000084        pcalau12i       \$a0, .*
+ +[0-9a-f]+:   28ce2084        ld.d            \$a0, \$a0, .*
+ +[0-9a-f]+:   1a000084        pcalau12i       \$a0, .*
+ +[0-9a-f]+:   02ce2005        li.d            \$a1, .*
+ +[0-9a-f]+:   16000005        lu32i.d         \$a1, 0
+ +[0-9a-f]+:   030000a5        lu52i.d         \$a1, \$a1, .*
+ +[0-9a-f]+:   00109484        add.d           \$a0, \$a0, \$a1
+ +[0-9a-f]+:   28c00081        ld.d            \$ra, \$a0, 0
+ +[0-9a-f]+:   4c000021        jirl            \$ra, \$ra, 0
+ +[0-9a-f]+:   1a000084        pcalau12i       \$a0, .*
+ +[0-9a-f]+:   02ce2005        li.d            \$a1, .*
+ +[0-9a-f]+:   16000005        lu32i.d         \$a1, .*
+ +[0-9a-f]+:   030000a5        lu52i.d         \$a1, \$a1, .*
+ +[0-9a-f]+:   380c1484        ldx.d           \$a0, \$a0, \$a1

diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.s b/ld/testsuite/ld-loongarch-elf/desc-ie.s
index 7f5772b..e85a16d 100644 (file)
--- a/ld/testsuite/ld-loongarch-elf/desc-ie.s
+++ b/ld/testsuite/ld-loongarch-elf/desc-ie.s
@@ -9,10 +9,9 @@ fn1:
 
        # Use DESC and IE to access the same symbol,
        # DESC will relax to IE.
-       pcalau12i       $a0,%desc_pc_hi20(var)
-       addi.d  $a0,$a0,%desc_pc_lo12(var)
-       ld.d    $ra,$a0,%desc_ld(var)
-       jirl    $ra,$ra,%desc_call(var)
+       la.tls.desc $a0,var
+       la.tls.ie   $a0,var
 
-       pcalau12i       $a0,%ie_pc_hi20(var)
-       ld.d            $ra,$a0,%ie_pc_lo12(var)
+       # extreme cmodel do not do transition.
+       la.tls.desc $a0,$a1,var
+       la.tls.ie   $a0,$a1,var

diff --git a/ld/testsuite/ld-loongarch-elf/desc-le.d b/ld/testsuite/ld-loongarch-elf/desc-le.d
index b4ca9f8..688701f 100644 (file)
--- a/ld/testsuite/ld-loongarch-elf/desc-le.d
+++ b/ld/testsuite/ld-loongarch-elf/desc-le.d
@@ -1,5 +1,5 @@
 #as:
-#ld: -z norelro -e 0x0
+#ld: -z norelro -e0
 #objdump: -dr
 #skip: loongarch32-*-*
 
@@ -8,8 +8,15 @@
 
 Disassembly of section .text:
 
-0+1200000e8 <fn1>:
-   1200000e8:  14000004        lu12i.w         \$a0, 0
-   1200000ec:  03800084        ori             \$a0, \$a0, 0x0
-   1200000f0:  03400000        nop.*
-   1200000f4:  03400000        nop.*
+[0-9a-f]+ <fn1>:
+   +[0-9a-f]+: 14000004        lu12i.w         \$a0, .*
+   +[0-9a-f]+: 03800084        ori             \$a0, \$a0, .*
+   +[0-9a-f]+: 03400000        nop
+   +[0-9a-f]+: 03400000        nop
+   +[0-9a-f]+: 1a000084        pcalau12i       \$a0, .*
+   +[0-9a-f]+: 02c4e005        li.d            \$a1, .*
+   +[0-9a-f]+: 16000005        lu32i.d         \$a1, .*
+   +[0-9a-f]+: 030000a5        lu52i.d         \$a1, \$a1, .*
+   +[0-9a-f]+: 00109484        add.d           \$a0, \$a0, \$a1
+   +[0-9a-f]+: 28c00081        ld.d            \$ra, \$a0, 0
+   +[0-9a-f]+: 4c000021        jirl            \$ra, \$ra, 0

diff --git a/ld/testsuite/ld-loongarch-elf/desc-le.s b/ld/testsuite/ld-loongarch-elf/desc-le.s
index 9ffaa2d..de6ab41 100644 (file)
--- a/ld/testsuite/ld-loongarch-elf/desc-le.s
+++ b/ld/testsuite/ld-loongarch-elf/desc-le.s
@@ -8,7 +8,7 @@ var:
 fn1:
 
        # DESC will relax to LE.
-       pcalau12i       $a0,%desc_pc_hi20(var)
-       addi.d  $a0,$a0,%desc_pc_lo12(var)
-       ld.d    $ra,$a0,%desc_ld(var)
-       jirl    $ra,$ra,%desc_call(var)
+       la.tls.desc $a0,var
+
+       # extreme cmodel do not do transition.
+       la.tls.desc $a0,$a1,var

diff --git a/ld/testsuite/ld-loongarch-elf/ie-le.d b/ld/testsuite/ld-loongarch-elf/ie-le.d
index 42694d7..28f3a66 100644 (file)
--- a/ld/testsuite/ld-loongarch-elf/ie-le.d
+++ b/ld/testsuite/ld-loongarch-elf/ie-le.d
@@ -1,5 +1,5 @@
 #as:
-#ld: -z norelro -e 0x0
+#ld: -z norelro -e0
 #objdump: -dr
 #skip: loongarch32-*-*
 
@@ -8,6 +8,11 @@
 
 Disassembly of section .text:
 
-0+1200000e8 <fn1>:
-   1200000e8:  14000004        lu12i.w         \$a0, 0
-   1200000ec:  03800084        ori             \$a0, \$a0, 0x0
+[0-9a-f]+ <fn1>:
+   +[0-9a-f]+: 14000004        lu12i.w         \$a0, .*
+   +[0-9a-f]+: 03800084        ori             \$a0, \$a0, .*
+   +[0-9a-f]+: 1a000084        pcalau12i       \$a0, .*
+   +[0-9a-f]+: 02c44005        li.d            \$a1, .*
+   +[0-9a-f]+: 16000005        lu32i.d         \$a1, .*
+   +[0-9a-f]+: 030000a5        lu52i.d         \$a1, \$a1, .*
+   +[0-9a-f]+: 380c1484        ldx.d           \$a0, \$a0, \$a1

diff --git a/ld/testsuite/ld-loongarch-elf/ie-le.s b/ld/testsuite/ld-loongarch-elf/ie-le.s
index 795c7ce..e582a2d 100644 (file)
--- a/ld/testsuite/ld-loongarch-elf/ie-le.s
+++ b/ld/testsuite/ld-loongarch-elf/ie-le.s
@@ -6,6 +6,7 @@ var:
        .global fn1
        .type   gn1,@function
 fn1:
-       # expect IE to relax LE.
-       pcalau12i       $a0,%ie_pc_hi20(var)
-       ld.d            $a0,$a0,%ie_pc_lo12(var)
+       # expect IE to relax LE in nomal cmodel.
+       la.tls.ie       $a0,var
+       # extreme cmodel do not do transition.
+       la.tls.ie       $a0,$a1,var

diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d
index c949391..46b849a 100644 (file)
--- a/ld/testsuite/ld-loongarch-elf/macro_op.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op.d
@@ -144,8 +144,10 @@ Disassembly of section .text:
 [      ]+f8: R_LARCH_TLS_LE_LO12[      ]+TLS1
 [      ]+fc:[  ]+1a000004[     ]+pcalau12i[    ]+\$a0, 0
 [      ]+fc: R_LARCH_TLS_IE_PC_HI20[   ]+TLS1
+[      ]+fc: R_LARCH_RELAX[    ]+\*ABS\*
 [      ]+100:[         ]+28c00084[     ]+ld.d[         ]+\$a0, \$a0, 0
 [      ]+100: R_LARCH_TLS_IE_PC_LO12[  ]+TLS1
+[      ]+100: R_LARCH_RELAX[   ]+\*ABS\*
 [      ]+104:[         ]+1a000004[     ]+pcalau12i[    ]+\$a0, 0
 [      ]+104: R_LARCH_TLS_IE_PC_HI20[  ]+TLS1
 [      ]+108:[         ]+02c00005[     ]+li.d[         ]+\$a1, 0

diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.d b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
index a7349aa..f8aaacd 100644 (file)
--- a/ld/testsuite/ld-loongarch-elf/macro_op_32.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
@@ -53,8 +53,10 @@ Disassembly of section .text:
                        44: R_LARCH_TLS_LE_LO12 TLS1
   48:  1a000004        pcalau12i       \$a0, 0
                        48: R_LARCH_TLS_IE_PC_HI20      TLS1
+                       48: R_LARCH_RELAX       \*ABS\*
   4c:  28800084        ld.w            \$a0, \$a0, 0
                        4c: R_LARCH_TLS_IE_PC_LO12      TLS1
+                       4c: R_LARCH_RELAX       \*ABS\*
   50:  1a000004        pcalau12i       \$a0, 0
                        50: R_LARCH_TLS_LD_PC_HI20      TLS1
                        50: R_LARCH_RELAX       \*ABS\*