[RyuJIT/ARM32] Unassign double register properly at BB entry
authorHyung-Kyu Choi <hk0110.choi@samsung.com>
Thu, 8 Jun 2017 09:33:12 +0000 (18:33 +0900)
committerHyung-Kyu Choi <hk0110.choi@samsung.com>
Wed, 21 Jun 2017 00:05:03 +0000 (09:05 +0900)
When updating var locations at basic block entry, we should
unassign double register properly for TYP_DOUBLE interval.

Signed-off-by: Hyung-Kyu Choi <hk0110.choi@samsung.com>
Commit migrated from https://github.com/dotnet/coreclr/commit/02f11738345521f0f736333b278dd0d14d6cf3b7

src/coreclr/src/jit/lsra.cpp

index f496315..319195e 100644 (file)
@@ -7005,15 +7005,21 @@ void LinearScan::processBlockStartLocations(BasicBlock* currentBlock, bool alloc
                 // Is there another interval currently assigned to this register?  If so unassign it.
                 if (assignedInterval != nullptr)
                 {
+#ifdef _TARGET_ARM_
+                    if (assignedInterval->assignedReg == targetRegRecord || isSecondHalfReg(targetRegRecord, assignedInterval))
+#else
                     if (assignedInterval->assignedReg == targetRegRecord)
+#endif
                     {
+                        regNumber assignedRegNum = assignedInterval->assignedReg->regNum;
+
                         // If the interval is active, it will be set to active when we reach its new
                         // register assignment (which we must not yet have done, or it wouldn't still be
                         // assigned to this register).
                         assignedInterval->isActive = false;
-                        unassignPhysReg(targetRegRecord, nullptr);
+                        unassignPhysReg(assignedInterval->assignedReg, nullptr);
                         if (allocationPass && assignedInterval->isLocalVar &&
-                            inVarToRegMap[assignedInterval->getVarIndex(compiler)] == targetReg)
+                            inVarToRegMap[assignedInterval->getVarIndex(compiler)] == assignedRegNum)
                         {
                             inVarToRegMap[assignedInterval->getVarIndex(compiler)] = REG_STK;
                         }