socfpga: arria10: Allow dcache_enable before relocation

Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).

Since commit 503eea451903 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
with the XN bit set causes a page fault. Override dram_bank_mmu_setup
to disable XN in the OCRAM and setup DRAM dcache before relocation.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index 0ed2adfd84a36f7a3e356dd76266b8ccfa2dadc7..7ce888d1979796d9579e3dbf7dc026e1e3eaa570 100644 (file)
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -246,3 +246,29 @@ int qspi_flash_software_reset(void)
        return 0;
 }
 #endif
+
+void dram_bank_mmu_setup(int bank)
+{
+       struct bd_info *bd = gd->bd;
+       u32 start, size;
+       int i;
+
+       /* If we're still in OCRAM, don't set the XN bit on it */
+       if (!(gd->flags & GD_FLG_RELOC)) {
+               set_section_dcache(
+                       CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
+                       DCACHE_WRITETHROUGH);
+       }
+
+       /*
+        * The default implementation of this function allows the DRAM dcache
+        * to be enabled only after relocation. However, to speed up ECC
+        * initialization, we want to be able to enable DRAM dcache before
+        * relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram
+        * is set first).
+        */
+       start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
+       size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
+       for (i = start; i < start + size; i++)
+               set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+}