ret <2 x i1> %cmp
}
+define i1 @icmp_shl_1_V_sle_0(i32 %V) {
+; CHECK-LABEL: @icmp_shl_1_V_sle_0(
+; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[V:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[SHL]], 1
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %shl = shl i32 1, %V
+ %cmp = icmp sle i32 %shl, 0
+ ret i1 %cmp
+}
+
+define <2 x i1> @icmp_shl_1_V_sle_0_vec(<2 x i32> %V) {
+; CHECK-LABEL: @icmp_shl_1_V_sle_0_vec(
+; CHECK-NEXT: [[SHL:%.*]] = shl nuw <2 x i32> <i32 1, i32 1>, [[V:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[SHL]], <i32 1, i32 1>
+; CHECK-NEXT: ret <2 x i1> [[CMP]]
+;
+ %shl = shl <2 x i32> <i32 1, i32 1>, %V
+ %cmp = icmp sle <2 x i32> %shl, <i32 0, i32 0>
+ ret <2 x i1> %cmp
+}
+
+define i1 @icmp_shl_1_V_sgt_0(i32 %V) {
+; CHECK-LABEL: @icmp_shl_1_V_sgt_0(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[V:%.*]], 31
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %shl = shl i32 1, %V
+ %cmp = icmp sgt i32 %shl, 0
+ ret i1 %cmp
+}
+
+define <2 x i1> @icmp_shl_1_V_sgt_0_vec(<2 x i32> %V) {
+; CHECK-LABEL: @icmp_shl_1_V_sgt_0_vec(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[V:%.*]], <i32 31, i32 31>
+; CHECK-NEXT: ret <2 x i1> [[CMP]]
+;
+ %shl = shl <2 x i32> <i32 1, i32 1>, %V
+ %cmp = icmp sgt <2 x i32> %shl, <i32 0, i32 0>
+ ret <2 x i1> %cmp
+}
+
define i1 @or_icmp_eq_B_0_icmp_ult_A_B(i64 %a, i64 %b) {
; CHECK-LABEL: @or_icmp_eq_B_0_icmp_ult_A_B(
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[B:%.*]], -1