intel/fs: also allow vec8+ vectorization of load_global_const_block_intel
authorLionel Landwerlin <lionel.g.landwerlin@intel.com>
Fri, 24 Mar 2023 11:29:59 +0000 (13:29 +0200)
committerMarge Bot <emma+marge@anholt.net>
Wed, 5 Apr 2023 12:32:56 +0000 (12:32 +0000)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

src/intel/compiler/brw_nir.c

index 777e3e2..749b046 100644 (file)
@@ -1301,7 +1301,8 @@ brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
    if (bit_size > 32)
       return false;
 
-   if (low->intrinsic == nir_intrinsic_load_ssbo_uniform_block_intel ||
+   if (low->intrinsic == nir_intrinsic_load_global_const_block_intel ||
+       low->intrinsic == nir_intrinsic_load_ssbo_uniform_block_intel ||
        low->intrinsic == nir_intrinsic_load_shared_uniform_block_intel) {
       if (num_components > 4) {
          if (!util_is_power_of_two_nonzero(num_components))