#define AMD_PMC_STB_INDEX_ADDRESS 0xF8
#define AMD_PMC_STB_INDEX_DATA 0xFC
#define AMD_PMC_STB_PMI_0 0x03E30600
-#define AMD_PMC_STB_PREDEF 0xC6000001
+#define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001
+#define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002
/* STB S2D(Spill to DRAM) has different message port offset */
#define STB_SPILL_TO_DRAM 0xBE
}
if (enable_stb) {
- rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF);
+ rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_PREPARE);
if (rc)
dev_err(pdev->dev, "error writing to STB: %d\n", rc);
}
/* Dump the IdleMask to see the blockers */
amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
- /* Write data incremented by 1 to distinguish in stb_read */
if (enable_stb) {
- rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF + 1);
+ rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_RESTORE);
if (rc)
dev_err(pdev->dev, "error writing to STB: %d\n", rc);
}