Same as ARM, but use a different opcode in the instruction selection.
llvm-svn: 353151
return selectShift(ARM_AM::ShiftOpc::lsl, MIB);
}
case G_GEP:
- I.setDesc(TII.get(ARM::ADDrr));
+ I.setDesc(TII.get(STI.isThumb2() ? ARM::t2ADDrr : ARM::ADDrr));
MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
break;
case G_FRAME_INDEX:
{s32, p0, 32},
{p0, p0, 32}});
+ getActionDefinitionsBuilder(G_GEP).legalFor({{p0, s32}});
+
if (ST.isThumb()) {
// FIXME: merge with the code for non-Thumb.
computeTables();
.clampScalar(0, s32, s32);
}
- getActionDefinitionsBuilder(G_GEP).legalFor({{p0, s32}});
-
getActionDefinitionsBuilder(G_SELECT).legalForCartesianProduct({s32, p0},
{s1});
# RUN: llc -mtriple thumb-- -mattr=+v6t2 -run-pass=legalizer %s -o - | FileCheck %s
--- |
define void @test_legal_loads_stores() { ret void }
+
+ define void @test_gep() { ret void }
...
---
name: test_legal_loads_stores
G_STORE %6(p0), %0(p0) :: (store 4)
BX_RET 14, $noreg
...
+---
+name: test_gep
+# CHECK-LABEL: name: test_gep
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ %1(s32) = COPY $r1
+
+ ; CHECK: {{%[0-9]+}}:_(p0) = G_GEP {{%[0-9]+}}, {{%[0-9]+}}(s32)
+ %2(p0) = G_GEP %0, %1(s32)
+
+ $r0 = COPY %2(p0)
+ BX_RET 14, $noreg, implicit $r0
+...
define void @test_load_from_stack() { ret void }
define void @test_load_store_64() #0 { ret void }
- define void @test_gep() { ret void }
-
define void @test_constants_s64() { ret void }
define void @test_icmp_s8() { ret void }
BX_RET 14, $noreg
...
---
-name: test_gep
-# CHECK-LABEL: name: test_gep
-legalized: false
-# CHECK: legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
-body: |
- bb.0:
- liveins: $r0, $r1
-
- %0(p0) = COPY $r0
- %1(s32) = COPY $r1
-
- ; CHECK: {{%[0-9]+}}:_(p0) = G_GEP {{%[0-9]+}}, {{%[0-9]+}}(s32)
- %2(p0) = G_GEP %0, %1(s32)
-
- $r0 = COPY %2(p0)
- BX_RET 14, $noreg, implicit $r0
-...
----
name: test_constants_s64
# CHECK-LABEL: name: test_constants_s64
legalized: false
define void @test_s8() { ret void }
define void @test_s16() { ret void }
define void @test_s32() { ret void }
+
+ define void @test_gep() { ret void }
...
---
name: test_s8
BX_RET 14, $noreg
; CHECK: BX_RET 14, $noreg
...
+---
+name: test_gep
+# CHECK-LABEL: name: test_gep
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+body: |
+ bb.0:
+ liveins: $r0, $r1
+
+ %0(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gprnopc = COPY $r0
+
+ %1(s32) = COPY $r1
+ ; CHECK: [[OFF:%[0-9]+]]:rgpr = COPY $r1
+
+ %2(p0) = G_GEP %0, %1(s32)
+ ; CHECK: [[GEP:%[0-9]+]]:gprnopc = t2ADDrr [[PTR]], [[OFF]], 14, $noreg, $noreg
+
+ $r0 = COPY %2(p0)
+ ; CHECK: $r0 = COPY [[GEP]]
+
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+...