arm64: dts: ti: k3-j784s4: Add MCSPI nodes

J784S4 has 8 MCSPI instances in the main domain and 3 instances
in the MCU domain. Add the DT nodes for all the 11 instances and
keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2
by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out
externally.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
Link: https://lore.kernel.org/r/20230321082827.14274-5-vaishnav.a@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 8c1474a..e9169eb 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -1024,4 +1024,92 @@
                bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
                status = "disabled";
        };
+
+       main_spi0: spi@2100000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x02100000 0x00 0x400>;
+               interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 376 1>;
+               status = "disabled";
+       };
+
+       main_spi1: spi@2110000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x02110000 0x00 0x400>;
+               interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 377 1>;
+               status = "disabled";
+       };
+
+       main_spi2: spi@2120000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x02120000 0x00 0x400>;
+               interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 378 1>;
+               status = "disabled";
+       };
+
+       main_spi3: spi@2130000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x02130000 0x00 0x400>;
+               interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 379 1>;
+               status = "disabled";
+       };
+
+       main_spi4: spi@2140000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x02140000 0x00 0x400>;
+               interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 380 1>;
+               status = "disabled";
+       };
+
+       main_spi5: spi@2150000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x02150000 0x00 0x400>;
+               interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 381 1>;
+               status = "disabled";
+       };
+
+       main_spi6: spi@2160000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x02160000 0x00 0x400>;
+               interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 382 1>;
+               status = "disabled";
+       };
+
+       main_spi7: spi@2170000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x02170000 0x00 0x400>;
+               interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 383 1>;
+               status = "disabled";
+       };
 };

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
index 64bd3de..f04fcb6 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
@@ -204,6 +204,39 @@
                status = "disabled";
        };
 
+       mcu_spi0: spi@40300000 {
+               compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+               reg = <0x00 0x040300000 0x00 0x400>;
+               interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 384 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 384 0>;
+               status = "disabled";
+       };
+
+       mcu_spi1: spi@40310000 {
+               compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+               reg = <0x00 0x040310000 0x00 0x400>;
+               interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 385 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 385 0>;
+               status = "disabled";
+       };
+
+       mcu_spi2: spi@40320000 {
+               compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+               reg = <0x00 0x040320000 0x00 0x400>;
+               interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 386 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 386 0>;
+               status = "disabled";
+       };
+
        mcu_navss: bus@28380000{
                compatible = "simple-bus";
                #address-cells = <2>;