write_reg(dev, P2_MDIOCR, MDIOCR_RADDR(loc) |
MDIOCR_FADDR(phy_id) | MDIOCR_READ);
- time_out = get_timer(0) + (CFG_HZ / 100);
+ time_out = get_timer(0) + (CFG_HZ * 100);
while ((read_reg(dev, P2_MDIOCR) & MDIOCR_VALID) == 0){
if (get_timer(0) > time_out) {
return -EIO;
write_reg(dev, P2_MDIOCR, MDIOCR_RADDR(loc) |
MDIOCR_FADDR(phy_id) | MDIOCR_WRITE);
- time_out = get_timer(0) + (CFG_HZ / 100);
+ time_out = get_timer(0) + (CFG_HZ * 100);
while ((read_reg(dev, P2_MDIOCR) & MDIOCR_VALID) == 0){
if (get_timer(0) > time_out) {
return -EIO;
write_reg(dev, P0_PSR, PSR_RESET);
write_reg(dev, P0_PSR, PSR_RESET_CLR);
- time_out = get_timer(0) + (CFG_HZ / 100);
+ time_out = get_timer(0) + (CFG_HZ * 100);
while (!(read_reg(dev, P0_PSR) & PSR_DEV_READY)){
if (get_timer(0) > time_out) {
return -ENXIO;
burst_len = ((rxlen + sizeof(struct rx_header) + 3) & 0xFFFC) >> 1;
write_reg(dev, P0_RXBCR1, (burst_len | RXBCR1_RXB_START));
- time_out = get_timer(0) + (CFG_HZ / 100);
+ time_out = get_timer(0) + (CFG_HZ * 100);
while ((read_reg(dev, P0_RXBCR2) & RXBCR2_RXB_READY) == 0) {
if (get_timer(0) > time_out) {
write_reg(dev, P0_RXBCR1, RXBCR1_RXB_DISCARD);
/* Receive RX Header, data and padding */
ax88796c_read_fifo_pio(dev, (unsigned char*)&rx_packet[0], burst_len * 2);
- time_out = get_timer(0) + (CFG_HZ / 100);
+ time_out = get_timer(0) + (CFG_HZ * 100);
while ((read_reg(dev, P0_RXBCR2) & RXBCR2_RXB_IDLE) == 0) {
if (get_timer(0) > time_out) {
goto error_out;
ax88796c_write_fifo_pio(dev, (unsigned char*)&tx_packet,
TX_HDR_SIZE + length + EOP_SIZE + align_count);
- time_out = get_timer(0) + (CFG_HZ / 100);
+ time_out = get_timer(0) + (CFG_HZ * 100);
while ((read_reg(dev, P0_TSNR) & TSNR_TXB_IDLE) == 0){
if (get_timer(0) > time_out) {
goto error_out;