[v4l2] [add vin path]

diff --git a/drivers/media/platform/starfive/v4l2_driver/sc2235.c b/drivers/media/platform/starfive/v4l2_driver/sc2235.c
index 045f406..1fec4c9 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/sc2235.c
+++ b/drivers/media/platform/starfive/v4l2_driver/sc2235.c
@@ -248,7 +248,6 @@ static struct reg_value sc2235_init_tbl_1080p_7fps[] = {
     {0x3908,0x11,0,0},
     {0x391b,0x4d,0,0},
     {0x391e,0x00,0,0},
-    {0x3d08,0x02,0,0},
     {0x3e01,0x46,0,0},
     {0x3e03,0x0b,0,0},
     {0x3f00,0x07,0,0},
@@ -263,8 +262,6 @@ static struct reg_value sc2235_init_tbl_1080p_7fps[] = {
     {0x3301,0x0a,0,0},
     {0x3631,0x88,0,0},
     {0x366f,0x2f,0,0},
-
-    {0x3d08,0x02,0,0},//hs-vs polity
 };
 
 static struct reg_value sc2235_setting_1080P_1920_1080[] = {
@@ -786,18 +783,12 @@ static int sc2235_set_framefmt(struct sc2235_dev *sensor,
 static int sc2235_restore_mode(struct sc2235_dev *sensor)
 {
        int ret;
-       unsigned int hs_polity = 1;             /* 1: valid when high; 0: valid when low */
-    unsigned int vs_polity = 1;             /* 1: valid when high; 0: valid when low */
-       unsigned char val;
-       
+
        /* first load the initial register values */
        ret = sc2235_load_regs(sensor, &sc2235_mode_init_data);
        if (ret < 0)
                return ret;
        sensor->last_mode = &sc2235_mode_init_data;
-       val = (vs_polity<<1)|((!hs_polity)<<2);
-       sc2235_write_reg16(sensor, 0x3d08, val);
-
        /* now restore the last capture mode */
        ret = sc2235_set_mode(sensor);
        if (ret < 0)

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_dvp.c b/drivers/media/platform/starfive/v4l2_driver/stf_dvp.c
index f8ea890..c289c54 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_dvp.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_dvp.c
@@ -15,10 +15,10 @@
 static const struct dvp_format dvp_formats_st7110[] = {
        { MEDIA_BUS_FMT_YUYV8_2X8, 16},
        { MEDIA_BUS_FMT_RGB565_2X8_LE, 16},
-       { MEDIA_BUS_FMT_SRGGB10_1X10, 12},
-       { MEDIA_BUS_FMT_SGRBG10_1X10, 12},
-       { MEDIA_BUS_FMT_SGBRG10_1X10, 12},
-       { MEDIA_BUS_FMT_SBGGR10_1X10, 12},
+       { MEDIA_BUS_FMT_SRGGB10_1X10, 16},
+       { MEDIA_BUS_FMT_SGRBG10_1X10, 16},
+       { MEDIA_BUS_FMT_SGBRG10_1X10, 16},
+       { MEDIA_BUS_FMT_SBGGR10_1X10, 16},
 };
 
 static int dvp_find_format(u32 code,

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_dvp_hw_ops.c b/drivers/media/platform/starfive/v4l2_driver/stf_dvp_hw_ops.c
index 04233ab..78a4228 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_dvp_hw_ops.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_dvp_hw_ops.c
@@ -95,9 +95,9 @@ static int stf_dvp_config_set(struct stf_dvp_dev *dvp_dev)
        if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
                polarities |= BIT(3);
        print_reg(ST_DVP, vin->sysctrl_base, SYSCONSAIF_SYSCFG_36);
-       reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
-               BIT(1) 
-               | BIT(3),
+       reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36, 
+               U0_VIN_CNFG_DVP_HS_POS 
+               | U0_VIN_CNFG_DVP_VS_POS,
                polarities);
        print_reg(ST_DVP, vin->sysctrl_base, SYSCONSAIF_SYSCFG_36);
 
@@ -118,10 +118,11 @@ static int stf_dvp_config_set(struct stf_dvp_dev *dvp_dev)
                data_shift = 0;
                break;
        };
-       print_reg(ST_DVP, vin->sysctrl_base, SYSCTRL_VIN_RW_CTRL);
+       print_reg(ST_DVP, vin->sysctrl_base, SYSCONSAIF_SYSCFG_28);
        reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
-                       UO_VIN_CNFG_AXIWR0_PIXEL_HEIGH_BIT_SEL, data_shift << 15);
-       print_reg(ST_DVP, vin->sysctrl_base, SYSCTRL_VIN_RW_CTRL);
+               UO_VIN_CNFG_AXIWR0_PIXEL_HEIGH_BIT_SEL, 
+               data_shift << 15);
+       print_reg(ST_DVP, vin->sysctrl_base, SYSCONSAIF_SYSCFG_28);
 
        return 0;
 }
@@ -135,16 +136,18 @@ static int set_vin_axiwr_pix_ct(struct stf_vin_dev *vin, u8 bpp)
        if (cnfg_axiwr_pix_ct == 2)
                value = 1;
        else if (cnfg_axiwr_pix_ct == 4)
-               value = 2;
+               value = 1;
        else if (cnfg_axiwr_pix_ct == 8)
                value = 0;
        else
                return 0;
 
-       print_reg(ST_DVP, vin->sysctrl_base, SYSCTRL_VIN_RW_CTRL);
-       reg_set_bit(vin->sysctrl_base,
-                       SYSCTRL_VIN_RW_CTRL, BIT(1) | BIT(0), value);
-       print_reg(ST_DVP, vin->sysctrl_base, SYSCTRL_VIN_RW_CTRL);
+       print_reg(ST_DVP, vin->sysctrl_base, SYSCONSAIF_SYSCFG_28);
+       reg_set_bit(vin->sysctrl_base, 
+               SYSCONSAIF_SYSCFG_28, 
+               U0_VIN_CNFG_AXIWR0_PIX_CT, 
+               value<<13);
+       print_reg(ST_DVP, vin->sysctrl_base, SYSCONSAIF_SYSCFG_28);
 
        return cnfg_axiwr_pix_ct;
 
@@ -160,7 +163,10 @@ static int stf_dvp_set_format(struct stf_dvp_dev *dvp_dev,
                pix_ct = set_vin_axiwr_pix_ct(vin, bpp);
                val = (pix_width / pix_ct) - 1;
                print_reg(ST_DVP, vin->sysctrl_base, SYSCTRL_VIN_WR_PIX_TOTAL);
-               reg_write(vin->sysctrl_base, SYSCTRL_VIN_WR_PIX_TOTAL, val);
+               reg_set_bit(vin->sysctrl_base, 
+                       SYSCONSAIF_SYSCFG_28, 
+                       U0_VIN_CNFG_AXIWR0_PIX_CNT_END, 
+                       val << 2);
                print_reg(ST_DVP, vin->sysctrl_base, SYSCTRL_VIN_WR_PIX_TOTAL);
 
        }
@@ -174,43 +180,27 @@ static int stf_dvp_stream_set(struct stf_dvp_dev *dvp_dev, int on)
 
        switch (dvp_dev->s_type) {
        case SENSOR_VIN:
-#if 0
-               /*View segment register (2.7.4.1.ispv2 ) is vin RD WR related (data stream not
-                through ISP, directly to DDR, or take data from DDR) 2021 1110*/
-               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_0, U0_VIN_CNFG_AXIRD_AXI_CNT_END, 0x0);
-               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_4, U0_VIN_CNFG_AXIRD_END_ADDR, 0x0);
-               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_8,     U0_VIN_CNFG_AXIRD_LINE_CNT_END, 0x0);
-               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_8,     U0_VIN_CNFG_AXIRD_LINE_CNT_START, 0x0);
-               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_12, U0_VIN_CNFG_AXIRD_PIX_CNT_END 
-                       | U0_VIN_CNFG_AXIRD_PIX_CNT_START 
-                       | U0_VIN_CNFG_AXIRD_PIX_CT, 0x0);
-               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_16, U0_VIN_CNFG_AXIRD_START_ADDR, 0x0);
-               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_20, U0_VIN_CNFG_AXIWR0_CHANNEL_SEL
-                       | U0_VIN_CNFG_AXIWR0_EN, 0x0);
-               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_24, U0_VIN_CNFG_AXIWR0_END_ADDR, 0x0);
-               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28, U0_VIN_CNFG_AXIWR0_PIXEL_HITH_BIT_SEL 
-                       | U0_VIN_CNFG_AXIWR0_PIX_CNT_CNT_END
-                       | U0_VIN_CNFG_AXIWR0_PIX_CNT_CT
-                       | SYSCONSAIF_SYSCFG_28, 0x0);
-               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_32, U0_VIN_CNFG_AXIWR0_START_ADDR, 0x0);
-               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_8,     U0_VIN_CNFG_AXIRD_INTR_MASK, 0x0);
-               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_0, U0_VIN_CNFG_AXI_DVP_EN, 0x0);
-               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_36, U0_VIN_CNFG_COLOR_BAR_EN, 0x0);
-#endif 
-               reg_set_bit(vin->sysctrl_base,
-                               SYSCTRL_VIN_AXI_CTRL, BIT(0), on);
-               reg_set_bit(vin->clkgen_base,
-                               CLK_VIN_AXI_WR_CTRL,
-                               BIT(25) | BIT(24), 2 << 24);
+               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_36, 
+                       U0_VIN_CNFG_ISP_DVP_EN0,
+                       0);
+               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_0, 
+                       U0_VIN_CNFG_AXI_DVP_EN, 
+                       1<<2);
                break;
        case SENSOR_ISP0:
-               reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
-                       BIT(U0_VIN_CNFG_ISP_DVP_EN0), 
-                       !!on<<U0_VIN_CNFG_ISP_DVP_EN0); 
-               reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36, 
-                       BIT(U0_VIN_CNFG_DVP_SWAP_EN), 0x0);       
-               reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36, 
-                       BIT(U0_VIN_CNFG_GEN_EN_AXIRD), 0x0);
+               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_36, 
+                       U0_VIN_CNFG_ISP_DVP_EN0, 
+                       !!on<<5);
+               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_0, 
+                       U0_VIN_CNFG_AXI_DVP_EN, 
+                       0);
+               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_36, 
+                       U0_VIN_CNFG_DVP_SWAP_EN,
+                       0);
+               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_36, 
+                       U0_VIN_CNFG_GEN_EN_AXIRD, 
+                       0);
+
                break;
        case SENSOR_ISP1:
                st_err(ST_DVP, "please check dvp_dev s_type:%d\n", dvp_dev->s_type);

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_isp_hw_ops.c b/drivers/media/platform/starfive/v4l2_driver/stf_isp_hw_ops.c
index dd6a466..dc4bfba 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_isp_hw_ops.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_isp_hw_ops.c
@@ -14,7 +14,7 @@
 #include <linux/delay.h>
 
 static const regval_t isp_sc2235_reg_config_list[] = {
-       {0x00000014, 0x0000000c, 0, 0},
+       {0x00000014, 0x00000008, 0, 0},
 //     {0x00000018, 0x000011BB, 0, 0},
        {0x00000A1C, 0x00000032, 0, 0},
 //     {0x0000001C, 0x00000000, 0, 0},

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_vin.c b/drivers/media/platform/starfive/v4l2_driver/stf_vin.c
index 068cc72..4fb883b 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_vin.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_vin.c
@@ -92,6 +92,7 @@ int stf_vin_subdev_init(struct stfcamss *stfcamss)
                st_err(ST_VIN, "failed to request isp0 irq\n");
                goto out;
        }
+#if 0 
 
        ret = devm_request_irq(dev,
                        vin->isp1_irq, vin_dev->hw_ops->vin_isp_irq_handler,
@@ -103,7 +104,7 @@ int stf_vin_subdev_init(struct stfcamss *stfcamss)
 
        vin_dev->hw_ops->vin_wr_irq_enable(vin_dev, 1);
        vin_dev->hw_ops->vin_wr_irq_enable(vin_dev, 0);
-#if 0
+
        /* Reset device */
        /*Do not configure the CLK before powering on the device,
        add vin_power_on() to vin_set_power() 2021 1111 */

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c b/drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c
index f9b3328..88ea10a 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c
@@ -40,23 +40,25 @@ static int vin_rstgen_assert_reset(struct stf_vin_dev *vin)
 
 static void vin_intr_clear(void __iomem * sysctrl_base)
 {
-       reg_set_bit(sysctrl_base, SYSCTRL_VIN_INTP_CTRL, BIT(0), 0x1);
-       reg_set_bit(sysctrl_base, SYSCTRL_VIN_INTP_CTRL, BIT(0), 0x0);
+
+       reg_set_bit(sysctrl_base, SYSCONSAIF_SYSCFG_28, 
+               U0_VIN_CNFG_AXIWR0_INTR_CLEAN, 
+               0x1);
+       reg_set_bit(sysctrl_base, SYSCONSAIF_SYSCFG_28, 
+               U0_VIN_CNFG_AXIWR0_INTR_CLEAN, 
+               0x0);
 }
 
 static irqreturn_t stf_vin_wr_irq_handler(int irq, void *priv)
 {
-#if 0
-
        static struct vin_params params;
        static struct vin_params vparams;
        struct stf_vin2_dev *vin_dev = priv;
        struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
 
        vin_dev->hw_ops->isr_buffer_done(&vin_dev->line[VIN_LINE_WR], &params);
-
        vin_intr_clear(vin->sysctrl_base);
-#endif
+
        return IRQ_HANDLED;
 }
 
@@ -98,52 +100,11 @@ static int stf_vin_clk_init(struct stf_vin2_dev *vin_dev)
        return 0;
 
 }
-extern  void stf_dvp_io_pad_config(struct stf_vin_dev *vin);
-void stf_do_port_configure(struct stfcamss *stfcamss)
-{
-       struct stf_vin_dev *vin = stfcamss->vin;
-       struct device *dev = stfcamss->dev;
-       struct device_node *node = NULL;
-       struct device_node *remote = NULL;
-
-       for_each_endpoint_of_node(dev->of_node, node) {
-               struct stfcamss_async_subdev *csd;
-               struct v4l2_async_subdev *asd;
-
-               if (!of_device_is_available(node))
-                       continue;
-               remote = of_graph_get_remote_port_parent(node);
-               if (!remote)
-                       st_err(ST_VIN, "Cannot get remote parent1\n");
-               
-               list_for_each_entry(asd, &stfcamss->notifier.asd_list, asd_list) {
-                       csd = container_of(asd, struct stfcamss_async_subdev, asd);
-                       switch(csd->port){
-                               case CSI2RX0_PORT_NUMBER:
-                               case CSI2RX1_PORT_NUMBER:
-                                       break;
-                               case DVP_SENSOR_PORT_NUMBER:
-                                       stf_dvp_io_pad_config(vin);
-                                       break;
-                               case CSI2RX0_SENSOR_PORT_NUMBER:
-                               case CSI2RX1_SENSOR_PORT_NUMBER:
-                                       break;
-                               default:
-                                       break;
-                       }
-               }
 
-               of_node_put(remote);
-               if (IS_ERR(asd)) {
-                               st_err(ST_CAMSS, "Cannot get remote parent2\n");
-               }
-       }
-}
 static int stf_vin_clk_enable(struct stf_vin2_dev *vin_dev)
 {
 
        struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
-       //stf_do_port_configure(vin_dev->stfcamss);
 
        reg_set_bit(vin->clkgen_base, CLK_DOM4_APB_FUNC, CLK_MUX_SEL, 0x8);
        reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PCLK, CLK_U0_VIN_PCLK_ICG, 0x1<<31);
@@ -197,19 +158,16 @@ static int stf_vin_config_set(struct stf_vin2_dev *vin_dev)
 static int stf_vin_wr_stream_set(struct stf_vin2_dev *vin_dev, int on)
 {
 
-#if 0
        struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
 
-       print_reg(ST_VIN, vin->sysctrl_base, SYSCTRL_VIN_AXI_CTRL);
+       print_reg(ST_VIN, vin->sysctrl_base, SYSCONSAIF_SYSCFG_20);
        if (on) {
-               reg_set(vin->sysctrl_base,
-                               SYSCTRL_VIN_AXI_CTRL, BIT(1));
+               reg_set(vin->sysctrl_base, SYSCONSAIF_SYSCFG_20, U0_VIN_CNFG_AXIWR0_EN);          
        } else {
-               reg_clear(vin->sysctrl_base,
-                               SYSCTRL_VIN_AXI_CTRL, BIT(1));
+               //reg_clear(vin->sysctrl_base, SYSCONSAIF_SYSCFG_20, U0_VIN_CNFG_AXIWR0_EN);
+               ;
        }
-       print_reg(ST_VIN, vin->sysctrl_base, SYSCTRL_VIN_AXI_CTRL);
-#endif
+       print_reg(ST_VIN, vin->sysctrl_base, SYSCONSAIF_SYSCFG_20);
 
        return 0;
 }
@@ -218,36 +176,36 @@ static void stf_vin_wr_irq_enable(struct stf_vin2_dev *vin_dev,
                int enable)
 {
 
-#if 0
+
        struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
-       unsigned int mask_value = 0, value = 0;
+       unsigned int value = 0;
 
        if (enable) {
-               // value = ~((0x1 << 4) | (0x1 << 20));
-               value = ~(0x1 << 4);
-
-               reg_set_bit(vin->sysctrl_base,
-                               SYSCTRL_VIN_INTP_CTRL, BIT(4), value);
+               value = ~(0x1 << 1);
+               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28, 
+                       U0_VIN_CNFG_AXIWR0_MASK, 
+                       value);
        } else {
-               /* mask and clear vin interrupt */
-               // mask_value = (0x1 << 4) | (0x1 << 20);
-               // value = 0x1 | (0x1 << 16) | mask_value;
-               reg_set_bit(vin->sysctrl_base,
-                               SYSCTRL_VIN_INTP_CTRL, BIT(0), 0x1);
-               reg_set_bit(vin->sysctrl_base,
-                               SYSCTRL_VIN_INTP_CTRL, BIT(0), 0x0);
-
-               value = 0x1 << 4;
-               reg_set_bit(vin->sysctrl_base,
-                               SYSCTRL_VIN_INTP_CTRL, BIT(4), value);
+               /* clear vin interrupt */
+               value = 0x1 << 1;
+               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28, 
+                       U0_VIN_CNFG_AXIWR0_INTR_CLEAN, 
+                       0x1);
+               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28, 
+                       U0_VIN_CNFG_AXIWR0_INTR_CLEAN, 
+                       0x0);
+               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28, 
+                       U0_VIN_CNFG_AXIWR0_MASK, 
+                       value);
        }
-#endif
+
 }
 
 static void stf_vin_power_on(struct stf_vin2_dev *vin_dev,     int enable)
 {
        struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
-
+       u32 reg = 0;
+       
        if(enable){
                reg_write(vin->pmu_test, SW_DEST_POWER_ON, (0x1<<5));
                reg_write(vin->pmu_test, SW_ENCOURAGE, 0xff);
@@ -259,14 +217,17 @@ static void stf_vin_power_on(struct stf_vin2_dev *vin_dev,        int enable)
                reg_clear_rst(vin->sys_crg, 0x2FCU,0x30CU, (0x1 << 9));
                reg_clear_rst(vin->sys_crg, 0x2FCU,0x30CU, (0x1 << 10));        
        } else {
-               reg_assert_rst(vin->sys_crg, 0x2FCU ,0x30cu, BIT(9));  //u0_dom_isp_top_disable
-               reg_assert_rst(vin->sys_crg, 0x2FCU ,0x30cu, BIT(10)); 
-               reg_set_bit(vin->sys_crg, 0xccu, BIT(31), 0x0);
-               reg_set_bit(vin->sys_crg, 0xd0u, BIT(31), 0x0);
-               reg_write(vin->pmu_test, SW_DEST_POWER_ON, (0x1<<5));
-               reg_write(vin->pmu_test, SW_ENCOURAGE, 0xff);
-               reg_write(vin->pmu_test, SW_ENCOURAGE, 0x0a);
-               reg_write(vin->pmu_test, SW_ENCOURAGE, 0xa0);
+               reg = reg_read(vin->sysctrl_base, SYSCONSAIF_SYSCFG_36);
+               if(reg && U0_VIN_CNFG_ISP_DVP_EN0) {
+                       reg_assert_rst(vin->sys_crg, 0x2FCU ,0x30cu, BIT(9));  
+                       reg_assert_rst(vin->sys_crg, 0x2FCU ,0x30cu, BIT(10)); 
+                       reg_set_bit(vin->sys_crg, 0xccu, BIT(31), 0x0);
+                       reg_set_bit(vin->sys_crg, 0xd0u, BIT(31), 0x0);
+                       reg_write(vin->pmu_test, SW_DEST_POWER_ON, (0x1<<5));
+                       reg_write(vin->pmu_test, SW_ENCOURAGE, 0xff);
+                       reg_write(vin->pmu_test, SW_ENCOURAGE, 0x0a);
+                       reg_write(vin->pmu_test, SW_ENCOURAGE, 0xa0);
+               }
        }
 }
 
@@ -290,26 +251,18 @@ static void stf_vin_wr_rd_set_addr(struct stf_vin2_dev *vin_dev,
 void stf_vin_wr_set_ping_addr(struct stf_vin2_dev *vin_dev,
                dma_addr_t addr)
 {
-
-#if 0
-
        struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
 
        /* set the start address */
-       reg_write(vin->sysctrl_base, SYSCTRL_VIN_WR_START_ADDR, (long)addr);
-#endif
+       reg_write(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_24, (long)addr);
 }
 
 void stf_vin_wr_set_pong_addr(struct stf_vin2_dev *vin_dev, dma_addr_t addr)
 {
-
-#if 0
-
        struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
 
        /* set the start address */
-       reg_write(vin->sysctrl_base, SYSCTRL_VIN_RD_END_ADDR, (long)addr);
-#endif
+       reg_write(vin->sysctrl_base, SYSCONSAIF_SYSCFG_32, (long)addr);
 }
 
 void stf_vin_isp_set_yuv_addr(struct stf_vin2_dev *vin_dev, int isp_id,

diff --git a/include/video/stf-vin.h b/include/video/stf-vin.h
index 8c323ae..405cfc6 100755 (executable)
--- a/include/video/stf-vin.h
+++ b/include/video/stf-vin.h
@@ -148,6 +148,8 @@
 
 //sys control REG DEFINE
 #define SYSCONSAIF_SYSCFG_0                                            0X0
+#define U0_VIN_SCFG_SRAM_CONFIG     (BIT(0) | BIT(1))
+
 #define SYSCONSAIF_SYSCFG_4                    0x4
 #define U0_VIN_CNFG_AXIRD_END_ADDR 0xffffffff
 #define SYSCONSAIF_SYSCFG_8                    0x8
@@ -163,16 +165,26 @@
 #define U0_VIN_CNFG_AXIWR0_EN          BIT(4)
 #define U0_VIN_CNFG_AXIWR0_CHANNEL_SEL (BIT(0) | BIT(1) | BIT(2) | BIT(3))
 #define SYSCONSAIF_SYSCFG_24           0x18
+#define U0_VIN_CNFG_AXIWR0_END_ADDR 0xFFFFFFFF
+
 #define SYSCONSAIF_SYSCFG_28           0x1c
-#define UO_VIN_CNFG_AXIWR0_PIXEL_HEIGH_BIT_SEL (BIT(15 | BIT(16)))
+#define U0_VIN_CNFG_AXIWR0_INTR_CLEAN BIT(0)
+#define U0_VIN_CNFG_AXIWR0_MASK                BIT(1)
+#define U0_VIN_CNFG_AXIWR0_PIX_CNT_END (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12))
+#define U0_VIN_CNFG_AXIWR0_PIX_CT (BIT(13) | BIT(14))
+#define UO_VIN_CNFG_AXIWR0_PIXEL_HEIGH_BIT_SEL (BIT(15) | BIT(16))
 #define SYSCONSAIF_SYSCFG_32           0x20
 
 #define SYSCONSAIF_SYSCFG_36                   0x24
+#define UO_VIN_CNFG_COLOR_BAR_EN       BIT(0)
 #define U0_VIN_CNFG_DVP_HS_POS         (0x1<<1)
-#define U0_VIN_CNFG_DVP_SWAP_EN                2
+#define U0_VIN_CNFG_DVP_SWAP_EN                BIT(2)
 #define U0_VIN_CNFG_DVP_VS_POS         (0x1<<3)
-#define U0_VIN_CNFG_GEN_EN_AXIRD       4
-#define U0_VIN_CNFG_ISP_DVP_EN0                5
+#define U0_VIN_CNFG_GEN_EN_AXIRD       BIT(4)
+#define U0_VIN_CNFG_ISP_DVP_EN0                BIT(5)
+#define U0_VIN_CNFG_MIPI_BYTE_EN_ISP0  (BIT(6) |BIT(7))
+#define U0_VIN_CNFG_P_I_MIPI_CHANNEL_SEL0      (BIT(8) |BIT(9) | BIT(10) | BIT(11))
+#define U0_VIN_CNFG_P_I_MIPI_HEADER_EN0 BIT(12)
 
 #define U0_VIN_CNFG_PIX_NUM                    (0x1<<13 | 0x1<<14 | 0x1<<15 | 0x1<<16)
 #define U0_VIN_CNFG_AXIRD_AXI_CNT_END  (BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13))
@@ -185,7 +197,7 @@
 #define U0_VIN_CNFG_AXIWR0_PIX_CNT_CT (BIT(13) | BIT(14))
 #define U0_VIN_CNFG_AXIWR0_PIX_CNT_CNT_END (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12))
 #define U0_VIN_CNFG_AXIWR0_PIXEL_HITH_BIT_SEL (BIT(15) | BIT(16))
-#define U0_VIN_CNFG_AXIWR0_END_ADDR 0xFFFFFFFF
+
 #define SYSCTRL_REG4               0x10
 #define SYSCTRL_DPHY_CTRL              0x14
 #define SYSCTRL_VIN_AXI_CTRL       0x18