spinlock_t lock;
};
-static void *amd_fch_gpio_addr(struct amd_fch_gpio_priv *priv,
- unsigned int gpio)
+static void __iomem *amd_fch_gpio_addr(struct amd_fch_gpio_priv *priv,
+ unsigned int gpio)
{
return priv->base + priv->pdata->gpio_reg[gpio]*sizeof(u32);
}
{
unsigned long flags;
struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
- void *ptr = amd_fch_gpio_addr(priv, offset);
+ void __iomem *ptr = amd_fch_gpio_addr(priv, offset);
spin_lock_irqsave(&priv->lock, flags);
writel_relaxed(readl_relaxed(ptr) & ~AMD_FCH_GPIO_FLAG_DIRECTION, ptr);
{
unsigned long flags;
struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
- void *ptr = amd_fch_gpio_addr(priv, gpio);
+ void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
spin_lock_irqsave(&priv->lock, flags);
writel_relaxed(readl_relaxed(ptr) | AMD_FCH_GPIO_FLAG_DIRECTION, ptr);
int ret;
unsigned long flags;
struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
- void *ptr = amd_fch_gpio_addr(priv, gpio);
+ void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
spin_lock_irqsave(&priv->lock, flags);
ret = (readl_relaxed(ptr) & AMD_FCH_GPIO_FLAG_DIRECTION);
{
unsigned long flags;
struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
- void *ptr = amd_fch_gpio_addr(priv, gpio);
+ void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
u32 mask;
spin_lock_irqsave(&priv->lock, flags);
unsigned long flags;
int ret;
struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
- void *ptr = amd_fch_gpio_addr(priv, offset);
+ void __iomem *ptr = amd_fch_gpio_addr(priv, offset);
spin_lock_irqsave(&priv->lock, flags);
ret = (readl_relaxed(ptr) & AMD_FCH_GPIO_FLAG_READ);