[ARM] Fix bxns mask

Bit 7 of BXNS is a fixed bit which distinguish it from BLXNS. Yet it is
not set in the disassembler entry mask. This commit fixes that.

2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>

opcodes/
	* arm-dis.c (thumb_opcodes): Fix BXNS mask.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f1e0863..9469b82 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       * arm-dis.c (thumb_opcodes): Fix BXNS mask.
+
 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 
        * wasm32-dis.c (print_insn_wasm32): Rename `index' local

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 5efe031..afa9410 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2530,7 +2530,7 @@ static const struct opcode16 thumb_opcodes[] =
 
   /* ARMv8-M Security Extensions instructions.  */
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
-  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
 
   /* ARM V8 instructions.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},