radv: Calculate tess patches and LDS use outside the backend compilers.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>

diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp
index 0cbbd9d..371c5cc 100644 (file)
--- a/src/amd/compiler/aco_instruction_selection_setup.cpp
+++ b/src/amd/compiler/aco_instruction_selection_setup.cpp
@@ -468,28 +468,8 @@ setup_tcs_info(isel_context *ctx, nir_shader *nir, nir_shader *vs)
    ctx->tcs_num_inputs = ctx->program->info->tcs.num_linked_inputs;
    ctx->tcs_num_outputs = ctx->program->info->tcs.num_linked_outputs;
    ctx->tcs_num_patch_outputs = ctx->program->info->tcs.num_linked_patch_outputs;
-
-   ctx->tcs_num_patches = get_tcs_num_patches(
-                             ctx->args->options->key.tcs.input_vertices,
-                             nir->info.tess.tcs_vertices_out,
-                             ctx->tcs_num_inputs,
-                             ctx->tcs_num_outputs,
-                             ctx->tcs_num_patch_outputs,
-                             ctx->args->options->tess_offchip_block_dw_size,
-                             ctx->args->options->chip_class,
-                             ctx->args->options->family);
-   unsigned lds_size = calculate_tess_lds_size(
-                             ctx->args->options->chip_class,
-                             ctx->args->options->key.tcs.input_vertices,
-                             nir->info.tess.tcs_vertices_out,
-                             ctx->tcs_num_inputs,
-                             ctx->tcs_num_patches,
-                             ctx->tcs_num_outputs,
-                             ctx->tcs_num_patch_outputs);
-
-   ctx->args->shader_info->tcs.num_patches = ctx->tcs_num_patches;
-   ctx->args->shader_info->tcs.num_lds_blocks = lds_size;
-   ctx->program->config->lds_size = lds_size; /* Already in blocks of the encoding granule */
+   ctx->tcs_num_patches = ctx->args->shader_info->tcs.num_patches;
+   ctx->program->config->lds_size = ctx->args->shader_info->tcs.num_lds_blocks;
 }
 
 void

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 3aa646c..2f889e9 100644 (file)
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -3986,18 +3986,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
                        ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
                        ctx.abi.store_tcs_outputs = store_tcs_output;
                        ctx.tcs_num_inputs = ctx.args->shader_info->tcs.num_linked_inputs;
-                       unsigned tcs_num_outputs = ctx.args->shader_info->tcs.num_linked_outputs;
-                       unsigned tcs_num_patch_outputs = ctx.args->shader_info->tcs.num_linked_patch_outputs;
-                       ctx.tcs_num_patches =
-                               get_tcs_num_patches(
-                                       ctx.args->options->key.tcs.input_vertices,
-                                       ctx.shader->info.tess.tcs_vertices_out,
-                                       ctx.tcs_num_inputs,
-                                       tcs_num_outputs,
-                                       tcs_num_patch_outputs,
-                                       ctx.args->options->tess_offchip_block_dw_size,
-                                       ctx.args->options->chip_class,
-                                       ctx.args->options->family);
+                       ctx.tcs_num_patches = args->shader_info->tcs.num_patches;
                } else if (shaders[shader_idx]->info.stage == MESA_SHADER_TESS_EVAL) {
                        ctx.abi.load_tess_varyings = load_tes_input;
                        ctx.abi.load_tess_coord = load_tess_coord;
@@ -4096,21 +4085,6 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
                           args->options->key.vs_common_out.as_ngg) {
                        gfx10_ngg_gs_emit_epilogue_2(&ctx);
                }
-
-               if (shaders[shader_idx]->info.stage == MESA_SHADER_TESS_CTRL) {
-                       unsigned tcs_num_outputs = ctx.args->shader_info->tcs.num_linked_outputs;
-                       unsigned tcs_num_patch_outputs = ctx.args->shader_info->tcs.num_linked_patch_outputs;
-                       args->shader_info->tcs.num_patches = ctx.tcs_num_patches;
-                       args->shader_info->tcs.num_lds_blocks =
-                               calculate_tess_lds_size(
-                                       ctx.args->options->chip_class,
-                                       ctx.args->options->key.tcs.input_vertices,
-                                       ctx.shader->info.tess.tcs_vertices_out,
-                                       ctx.tcs_num_inputs,
-                                       ctx.tcs_num_patches,
-                                       tcs_num_outputs,
-                                       tcs_num_patch_outputs);
-               }
        }
 
        LLVMBuildRetVoid(ctx.ac.builder);

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index b998a13..702ac25 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3351,6 +3351,40 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline,
                        }
                        NIR_PASS_V(nir[i], nir_lower_memory_model);
 
+                       if (i == MESA_SHADER_TESS_CTRL) {
+                               /* Copy correct primitive mode from TES info. */
+                               nir[i]->info.tess.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
+
+                               /* Number of tessellation patches processed per workgroup in the current pipeline. */
+                               unsigned tcs_num_patches =
+                                       get_tcs_num_patches(
+                                               pipeline_key->tess_input_vertices,
+                                               nir[i]->info.tess.tcs_vertices_out,
+                                               infos[i].tcs.num_linked_inputs,
+                                               infos[i].tcs.num_linked_outputs,
+                                               infos[i].tcs.num_linked_patch_outputs,
+                                               device->tess_offchip_block_dw_size,
+                                               device->physical_device->rad_info.chip_class,
+                                               device->physical_device->rad_info.family);
+
+                               /* LDS size used by VS+TCS for storing TCS inputs and outputs. */
+                               unsigned tcs_lds_size =
+                                       calculate_tess_lds_size(
+                                               device->physical_device->rad_info.chip_class,
+                                               pipeline_key->tess_input_vertices,
+                                               nir[i]->info.tess.tcs_vertices_out,
+                                               infos[i].tcs.num_linked_inputs,
+                                               tcs_num_patches,
+                                               infos[i].tcs.num_linked_outputs,
+                                               infos[i].tcs.num_linked_patch_outputs);
+
+                               infos[i].tcs.num_patches = tcs_num_patches;
+                               infos[i].tcs.num_lds_blocks = tcs_lds_size;
+                       } else if (i == MESA_SHADER_TESS_EVAL) {
+                               /* Copy num_patches from TCS info. */
+                               keys[i].tes.num_patches = infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
+                       }
+
                        bool lower_to_scalar = false;
 
                        nir_load_store_vectorize_options vectorize_opts = {