rtw89: pci: add L1 settings

Configure L1 settings of enter and exit.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220325060055.58482-8-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c
index 5112b2d..dcf907b 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/pci.c
+++ b/drivers/net/wireless/realtek/rtw89/pci.c
@@ -1935,6 +1935,22 @@ static void rtw89_pci_gen2_force_ib(struct rtw89_dev *rtwdev)
                          B_AX_SYSON_DIS_PMCR_AX_WRMSK);
 }
 
+static void rtw89_pci_l1_ent_lat(struct rtw89_dev *rtwdev)
+{
+       if (rtwdev->chip->chip_id != RTL8852C)
+               return;
+
+       rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL_V1, B_AX_SEL_REQ_ENTR_L1);
+}
+
+static void rtw89_pci_wd_exit_l1(struct rtw89_dev *rtwdev)
+{
+       if (rtwdev->chip->chip_id != RTL8852C)
+               return;
+
+       rtw89_write32_set(rtwdev, R_AX_PCIE_PS_CTRL_V1, B_AX_DMAC0_EXIT_L1_EN);
+}
+
 static void rtw89_pci_set_sic(struct rtw89_dev *rtwdev)
 {
        if (rtwdev->chip->chip_id == RTL8852C)
@@ -2228,6 +2244,8 @@ static int rtw89_pci_ops_mac_pre_init(struct rtw89_dev *rtwdev)
        rtw89_pci_autoload_hang(rtwdev);
        rtw89_pci_l12_vmain(rtwdev);
        rtw89_pci_gen2_force_ib(rtwdev);
+       rtw89_pci_l1_ent_lat(rtwdev);
+       rtw89_pci_wd_exit_l1(rtwdev);
        rtw89_pci_set_sic(rtwdev);
        rtw89_pci_set_lbc(rtwdev);
        rtw89_pci_set_io_rcy(rtwdev);

diff --git a/drivers/net/wireless/realtek/rtw89/pci.h b/drivers/net/wireless/realtek/rtw89/pci.h
index 805fc3e..a085d1f 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/pci.h
+++ b/drivers/net/wireless/realtek/rtw89/pci.h
@@ -38,6 +38,13 @@
 #define R_AX_MDIO_WDATA                        0x10A4
 #define R_AX_MDIO_RDATA                        0x10A6
 
+#define R_AX_PCIE_PS_CTRL_V1           0x3008
+#define B_AX_CMAC_EXIT_L1_EN           BIT(7)
+#define B_AX_DMAC0_EXIT_L1_EN          BIT(6)
+#define B_AX_SEL_XFER_PENDING          BIT(3)
+#define B_AX_SEL_REQ_ENTR_L1           BIT(2)
+#define B_AX_SEL_REQ_EXIT_L1           BIT(0)
+
 #define R_AX_PCIE_BG_CLR               0x303C
 #define B_AX_BG_CLR_ASYNC_M3           BIT(4)