Merge drm/drm-next into drm-intel-gt-next

In order to get the GSC Support merged on drm-intel-gt-next
in a clean fashion we needed this ATS-M patch to avoid
conflict in i915_pci.c:

commit 412c942bdfae ("drm/i915/ats-m: add ATS-M platform info")

--

Fixing a silent conflict on drivers/gpu/drm/i915/gt/intel_gt_gmch.c:
-       if (!intel_vtd_active(i915))
+       if (!i915_vtd_active(i915))

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --cc Documentation/gpu/i915.rst
Simple merge

diff --cc drivers/gpu/drm/i915/Makefile
Simple merge

diff --cc drivers/gpu/drm/i915/display/intel_dpt.c
Simple merge

diff --cc drivers/gpu/drm/i915/display/intel_fb.c
Simple merge

diff --cc drivers/gpu/drm/i915/display/intel_plane_initial.c
Simple merge

diff --cc drivers/gpu/drm/i915/gem/i915_gem_context.c
Simple merge

diff --cc drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
Simple merge

diff --cc drivers/gpu/drm/i915/gem/i915_gem_lmem.c
Simple merge

diff --cc drivers/gpu/drm/i915/gem/i915_gem_object.c
Simple merge

diff --cc drivers/gpu/drm/i915/gem/i915_gem_region.c
Simple merge

diff --cc drivers/gpu/drm/i915/gem/i915_gem_shmem.c
Simple merge

diff --cc drivers/gpu/drm/i915/gem/i915_gem_stolen.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_engine_cs.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_execlists_submission.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_ggtt.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_gt_gmch.c
index 64e9ad41cf6622a266c1fd33009ddfb0a3afe5c9,0000000000000000000000000000000000000000..18e488672d1b3e6c3cb887384cc4e8f615ded3d1
mode 100644,000000..100644
--- 1/drivers/gpu/drm/i915/gt/intel_gt_gmch.c
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_gmch.c
@@@ -1,654 -1,0 +1,654 @@@
-       if (!intel_vtd_active(i915))
 +// SPDX-License-Identifier: MIT
 +/*
 + * Copyright © 2022 Intel Corporation
 + */
 +
 +#include <drm/intel-gtt.h>
 +#include <drm/i915_drm.h>
 +
 +#include <linux/agp_backend.h>
 +#include <linux/stop_machine.h>
 +
 +#include "i915_drv.h"
 +#include "intel_gt_gmch.h"
 +#include "intel_gt_regs.h"
 +#include "intel_gt.h"
 +#include "i915_utils.h"
 +
 +#include "gen8_ppgtt.h"
 +
 +struct insert_page {
 +      struct i915_address_space *vm;
 +      dma_addr_t addr;
 +      u64 offset;
 +      enum i915_cache_level level;
 +};
 +
 +static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
 +{
 +      writeq(pte, addr);
 +}
 +
 +static void nop_clear_range(struct i915_address_space *vm,
 +                          u64 start, u64 length)
 +{
 +}
 +
 +static u64 snb_pte_encode(dma_addr_t addr,
 +                        enum i915_cache_level level,
 +                        u32 flags)
 +{
 +      gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
 +
 +      switch (level) {
 +      case I915_CACHE_L3_LLC:
 +      case I915_CACHE_LLC:
 +              pte |= GEN6_PTE_CACHE_LLC;
 +              break;
 +      case I915_CACHE_NONE:
 +              pte |= GEN6_PTE_UNCACHED;
 +              break;
 +      default:
 +              MISSING_CASE(level);
 +      }
 +
 +      return pte;
 +}
 +
 +static u64 ivb_pte_encode(dma_addr_t addr,
 +                        enum i915_cache_level level,
 +                        u32 flags)
 +{
 +      gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
 +
 +      switch (level) {
 +      case I915_CACHE_L3_LLC:
 +              pte |= GEN7_PTE_CACHE_L3_LLC;
 +              break;
 +      case I915_CACHE_LLC:
 +              pte |= GEN6_PTE_CACHE_LLC;
 +              break;
 +      case I915_CACHE_NONE:
 +              pte |= GEN6_PTE_UNCACHED;
 +              break;
 +      default:
 +              MISSING_CASE(level);
 +      }
 +
 +      return pte;
 +}
 +
 +static u64 byt_pte_encode(dma_addr_t addr,
 +                        enum i915_cache_level level,
 +                        u32 flags)
 +{
 +      gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
 +
 +      if (!(flags & PTE_READ_ONLY))
 +              pte |= BYT_PTE_WRITEABLE;
 +
 +      if (level != I915_CACHE_NONE)
 +              pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 +
 +      return pte;
 +}
 +
 +static u64 hsw_pte_encode(dma_addr_t addr,
 +                        enum i915_cache_level level,
 +                        u32 flags)
 +{
 +      gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
 +
 +      if (level != I915_CACHE_NONE)
 +              pte |= HSW_WB_LLC_AGE3;
 +
 +      return pte;
 +}
 +
 +static u64 iris_pte_encode(dma_addr_t addr,
 +                         enum i915_cache_level level,
 +                         u32 flags)
 +{
 +      gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
 +
 +      switch (level) {
 +      case I915_CACHE_NONE:
 +              break;
 +      case I915_CACHE_WT:
 +              pte |= HSW_WT_ELLC_LLC_AGE3;
 +              break;
 +      default:
 +              pte |= HSW_WB_ELLC_LLC_AGE3;
 +              break;
 +      }
 +
 +      return pte;
 +}
 +
 +static void gen5_ggtt_insert_page(struct i915_address_space *vm,
 +                                dma_addr_t addr,
 +                                u64 offset,
 +                                enum i915_cache_level cache_level,
 +                                u32 unused)
 +{
 +      unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 +              AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 +
 +      intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
 +}
 +
 +static void gen6_ggtt_insert_page(struct i915_address_space *vm,
 +                                dma_addr_t addr,
 +                                u64 offset,
 +                                enum i915_cache_level level,
 +                                u32 flags)
 +{
 +      struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 +      gen6_pte_t __iomem *pte =
 +              (gen6_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
 +
 +      iowrite32(vm->pte_encode(addr, level, flags), pte);
 +
 +      ggtt->invalidate(ggtt);
 +}
 +
 +static void gen8_ggtt_insert_page(struct i915_address_space *vm,
 +                                dma_addr_t addr,
 +                                u64 offset,
 +                                enum i915_cache_level level,
 +                                u32 flags)
 +{
 +      struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 +      gen8_pte_t __iomem *pte =
 +              (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
 +
 +      gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));
 +
 +      ggtt->invalidate(ggtt);
 +}
 +
 +static void gen5_ggtt_insert_entries(struct i915_address_space *vm,
 +                                   struct i915_vma_resource *vma_res,
 +                                   enum i915_cache_level cache_level,
 +                                   u32 unused)
 +{
 +      unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 +              AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 +
 +      intel_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT,
 +                                  flags);
 +}
 +
 +/*
 + * Binds an object into the global gtt with the specified cache level.
 + * The object will be accessible to the GPU via commands whose operands
 + * reference offsets within the global GTT as well as accessible by the GPU
 + * through the GMADR mapped BAR (i915->mm.gtt->gtt).
 + */
 +static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
 +                                   struct i915_vma_resource *vma_res,
 +                                   enum i915_cache_level level,
 +                                   u32 flags)
 +{
 +      struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 +      gen6_pte_t __iomem *gte;
 +      gen6_pte_t __iomem *end;
 +      struct sgt_iter iter;
 +      dma_addr_t addr;
 +
 +      gte = (gen6_pte_t __iomem *)ggtt->gsm;
 +      gte += vma_res->start / I915_GTT_PAGE_SIZE;
 +      end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
 +
 +      for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
 +              iowrite32(vm->pte_encode(addr, level, flags), gte++);
 +      GEM_BUG_ON(gte > end);
 +
 +      /* Fill the allocated but "unused" space beyond the end of the buffer */
 +      while (gte < end)
 +              iowrite32(vm->scratch[0]->encode, gte++);
 +
 +      /*
 +       * We want to flush the TLBs only after we're certain all the PTE
 +       * updates have finished.
 +       */
 +      ggtt->invalidate(ggtt);
 +}
 +
 +static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 +                                   struct i915_vma_resource *vma_res,
 +                                   enum i915_cache_level level,
 +                                   u32 flags)
 +{
 +      const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);
 +      struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 +      gen8_pte_t __iomem *gte;
 +      gen8_pte_t __iomem *end;
 +      struct sgt_iter iter;
 +      dma_addr_t addr;
 +
 +      /*
 +       * Note that we ignore PTE_READ_ONLY here. The caller must be careful
 +       * not to allow the user to override access to a read only page.
 +       */
 +
 +      gte = (gen8_pte_t __iomem *)ggtt->gsm;
 +      gte += vma_res->start / I915_GTT_PAGE_SIZE;
 +      end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
 +
 +      for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
 +              gen8_set_pte(gte++, pte_encode | addr);
 +      GEM_BUG_ON(gte > end);
 +
 +      /* Fill the allocated but "unused" space beyond the end of the buffer */
 +      while (gte < end)
 +              gen8_set_pte(gte++, vm->scratch[0]->encode);
 +
 +      /*
 +       * We want to flush the TLBs only after we're certain all the PTE
 +       * updates have finished.
 +       */
 +      ggtt->invalidate(ggtt);
 +}
 +
 +static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
 +{
 +      /*
 +       * Make sure the internal GAM fifo has been cleared of all GTT
 +       * writes before exiting stop_machine(). This guarantees that
 +       * any aperture accesses waiting to start in another process
 +       * cannot back up behind the GTT writes causing a hang.
 +       * The register can be any arbitrary GAM register.
 +       */
 +      intel_uncore_posting_read_fw(vm->gt->uncore, GFX_FLSH_CNTL_GEN6);
 +}
 +
 +static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
 +{
 +      struct insert_page *arg = _arg;
 +
 +      gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
 +      bxt_vtd_ggtt_wa(arg->vm);
 +
 +      return 0;
 +}
 +
 +static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
 +                                        dma_addr_t addr,
 +                                        u64 offset,
 +                                        enum i915_cache_level level,
 +                                        u32 unused)
 +{
 +      struct insert_page arg = { vm, addr, offset, level };
 +
 +      stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
 +}
 +
 +static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
 +{
 +      struct insert_entries *arg = _arg;
 +
 +      gen8_ggtt_insert_entries(arg->vm, arg->vma_res, arg->level, arg->flags);
 +      bxt_vtd_ggtt_wa(arg->vm);
 +
 +      return 0;
 +}
 +
 +static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
 +                                           struct i915_vma_resource *vma_res,
 +                                           enum i915_cache_level level,
 +                                           u32 flags)
 +{
 +      struct insert_entries arg = { vm, vma_res, level, flags };
 +
 +      stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
 +}
 +
 +void intel_gt_gmch_gen5_chipset_flush(struct intel_gt *gt)
 +{
 +      intel_gtt_chipset_flush();
 +}
 +
 +static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
 +{
 +      intel_gtt_chipset_flush();
 +}
 +
 +static void gen5_ggtt_clear_range(struct i915_address_space *vm,
 +                                       u64 start, u64 length)
 +{
 +      intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
 +}
 +
 +static void gen6_ggtt_clear_range(struct i915_address_space *vm,
 +                                u64 start, u64 length)
 +{
 +      struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 +      unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
 +      unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
 +      gen6_pte_t scratch_pte, __iomem *gtt_base =
 +              (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
 +      const int max_entries = ggtt_total_entries(ggtt) - first_entry;
 +      int i;
 +
 +      if (WARN(num_entries > max_entries,
 +               "First entry = %d; Num entries = %d (max=%d)\n",
 +               first_entry, num_entries, max_entries))
 +              num_entries = max_entries;
 +
 +      scratch_pte = vm->scratch[0]->encode;
 +      for (i = 0; i < num_entries; i++)
 +              iowrite32(scratch_pte, &gtt_base[i]);
 +}
 +
 +static void gen8_ggtt_clear_range(struct i915_address_space *vm,
 +                                u64 start, u64 length)
 +{
 +      struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 +      unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
 +      unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
 +      const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
 +      gen8_pte_t __iomem *gtt_base =
 +              (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
 +      const int max_entries = ggtt_total_entries(ggtt) - first_entry;
 +      int i;
 +
 +      if (WARN(num_entries > max_entries,
 +               "First entry = %d; Num entries = %d (max=%d)\n",
 +               first_entry, num_entries, max_entries))
 +              num_entries = max_entries;
 +
 +      for (i = 0; i < num_entries; i++)
 +              gen8_set_pte(&gtt_base[i], scratch_pte);
 +}
 +
 +static void gen5_gmch_remove(struct i915_address_space *vm)
 +{
 +      intel_gmch_remove();
 +}
 +
 +static void gen6_gmch_remove(struct i915_address_space *vm)
 +{
 +      struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 +
 +      iounmap(ggtt->gsm);
 +      free_scratch(vm);
 +}
 +
 +/*
 + * Certain Gen5 chipsets require idling the GPU before
 + * unmapping anything from the GTT when VT-d is enabled.
 + */
 +static bool needs_idle_maps(struct drm_i915_private *i915)
 +{
 +      /*
 +       * Query intel_iommu to see if we need the workaround. Presumably that
 +       * was loaded first.
 +       */
++      if (!i915_vtd_active(i915))
 +              return false;
 +
 +      if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915))
 +              return true;
 +
 +      if (GRAPHICS_VER(i915) == 12)
 +              return true; /* XXX DMAR fault reason 7 */
 +
 +      return false;
 +}
 +
 +static unsigned int gen6_gttmmadr_size(struct drm_i915_private *i915)
 +{
 +      /*
 +       * GEN6: GTTMMADR size is 4MB and GTTADR starts at 2MB offset
 +       * GEN8: GTTMMADR size is 16MB and GTTADR starts at 8MB offset
 +       */
 +      GEM_BUG_ON(GRAPHICS_VER(i915) < 6);
 +      return (GRAPHICS_VER(i915) < 8) ? SZ_4M : SZ_16M;
 +}
 +
 +static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 +{
 +      snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 +      snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 +      return snb_gmch_ctl << 20;
 +}
 +
 +static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
 +{
 +      bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
 +      bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
 +      if (bdw_gmch_ctl)
 +              bdw_gmch_ctl = 1 << bdw_gmch_ctl;
 +
 +#ifdef CONFIG_X86_32
 +      /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * I915_GTT_PAGE_SIZE */
 +      if (bdw_gmch_ctl > 4)
 +              bdw_gmch_ctl = 4;
 +#endif
 +
 +      return bdw_gmch_ctl << 20;
 +}
 +
 +static unsigned int gen6_gttadr_offset(struct drm_i915_private *i915)
 +{
 +      return gen6_gttmmadr_size(i915) / 2;
 +}
 +
 +static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 +{
 +      struct drm_i915_private *i915 = ggtt->vm.i915;
 +      struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 +      phys_addr_t phys_addr;
 +      u32 pte_flags;
 +      int ret;
 +
 +      GEM_WARN_ON(pci_resource_len(pdev, 0) != gen6_gttmmadr_size(i915));
 +      phys_addr = pci_resource_start(pdev, 0) + gen6_gttadr_offset(i915);
 +
 +      /*
 +       * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range
 +       * will be dropped. For WC mappings in general we have 64 byte burst
 +       * writes when the WC buffer is flushed, so we can't use it, but have to
 +       * resort to an uncached mapping. The WC issue is easily caught by the
 +       * readback check when writing GTT PTE entries.
 +       */
 +      if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 11)
 +              ggtt->gsm = ioremap(phys_addr, size);
 +      else
 +              ggtt->gsm = ioremap_wc(phys_addr, size);
 +      if (!ggtt->gsm) {
 +              drm_err(&i915->drm, "Failed to map the ggtt page table\n");
 +              return -ENOMEM;
 +      }
 +
 +      kref_init(&ggtt->vm.resv_ref);
 +      ret = setup_scratch_page(&ggtt->vm);
 +      if (ret) {
 +              drm_err(&i915->drm, "Scratch setup failed\n");
 +              /* iounmap will also get called at remove, but meh */
 +              iounmap(ggtt->gsm);
 +              return ret;
 +      }
 +
 +      pte_flags = 0;
 +      if (i915_gem_object_is_lmem(ggtt->vm.scratch[0]))
 +              pte_flags |= PTE_LM;
 +
 +      ggtt->vm.scratch[0]->encode =
 +              ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]),
 +                                  I915_CACHE_NONE, pte_flags);
 +
 +      return 0;
 +}
 +
 +int intel_gt_gmch_gen5_probe(struct i915_ggtt *ggtt)
 +{
 +      struct drm_i915_private *i915 = ggtt->vm.i915;
 +      phys_addr_t gmadr_base;
 +      int ret;
 +
 +      ret = intel_gmch_probe(i915->bridge_dev, to_pci_dev(i915->drm.dev), NULL);
 +      if (!ret) {
 +              drm_err(&i915->drm, "failed to set up gmch\n");
 +              return -EIO;
 +      }
 +
 +      intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
 +
 +      ggtt->gmadr =
 +              (struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
 +
 +      ggtt->vm.alloc_pt_dma = alloc_pt_dma;
 +      ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
 +
 +      if (needs_idle_maps(i915)) {
 +              drm_notice(&i915->drm,
 +                         "Flushing DMA requests before IOMMU unmaps; performance may be degraded\n");
 +              ggtt->do_idle_maps = true;
 +      }
 +
 +      ggtt->vm.insert_page = gen5_ggtt_insert_page;
 +      ggtt->vm.insert_entries = gen5_ggtt_insert_entries;
 +      ggtt->vm.clear_range = gen5_ggtt_clear_range;
 +      ggtt->vm.cleanup = gen5_gmch_remove;
 +
 +      ggtt->invalidate = gmch_ggtt_invalidate;
 +
 +      ggtt->vm.vma_ops.bind_vma    = intel_ggtt_bind_vma;
 +      ggtt->vm.vma_ops.unbind_vma  = intel_ggtt_unbind_vma;
 +
 +      if (unlikely(ggtt->do_idle_maps))
 +              drm_notice(&i915->drm,
 +                         "Applying Ironlake quirks for intel_iommu\n");
 +
 +      return 0;
 +}
 +
 +int intel_gt_gmch_gen6_probe(struct i915_ggtt *ggtt)
 +{
 +      struct drm_i915_private *i915 = ggtt->vm.i915;
 +      struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 +      unsigned int size;
 +      u16 snb_gmch_ctl;
 +
 +      ggtt->gmadr = intel_pci_resource(pdev, 2);
 +      ggtt->mappable_end = resource_size(&ggtt->gmadr);
 +
 +      /*
 +       * 64/512MB is the current min/max we actually know of, but this is
 +       * just a coarse sanity check.
 +       */
 +      if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
 +              drm_err(&i915->drm, "Unknown GMADR size (%pa)\n",
 +                      &ggtt->mappable_end);
 +              return -ENXIO;
 +      }
 +
 +      pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 +
 +      size = gen6_get_total_gtt_size(snb_gmch_ctl);
 +      ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
 +
 +      ggtt->vm.alloc_pt_dma = alloc_pt_dma;
 +      ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
 +
 +      ggtt->vm.clear_range = nop_clear_range;
 +      if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
 +              ggtt->vm.clear_range = gen6_ggtt_clear_range;
 +      ggtt->vm.insert_page = gen6_ggtt_insert_page;
 +      ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
 +      ggtt->vm.cleanup = gen6_gmch_remove;
 +
 +      ggtt->invalidate = gen6_ggtt_invalidate;
 +
 +      if (HAS_EDRAM(i915))
 +              ggtt->vm.pte_encode = iris_pte_encode;
 +      else if (IS_HASWELL(i915))
 +              ggtt->vm.pte_encode = hsw_pte_encode;
 +      else if (IS_VALLEYVIEW(i915))
 +              ggtt->vm.pte_encode = byt_pte_encode;
 +      else if (GRAPHICS_VER(i915) >= 7)
 +              ggtt->vm.pte_encode = ivb_pte_encode;
 +      else
 +              ggtt->vm.pte_encode = snb_pte_encode;
 +
 +      ggtt->vm.vma_ops.bind_vma    = intel_ggtt_bind_vma;
 +      ggtt->vm.vma_ops.unbind_vma  = intel_ggtt_unbind_vma;
 +
 +      return ggtt_probe_common(ggtt, size);
 +}
 +
 +static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
 +{
 +      gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
 +      gmch_ctrl &= SNB_GMCH_GGMS_MASK;
 +
 +      if (gmch_ctrl)
 +              return 1 << (20 + gmch_ctrl);
 +
 +      return 0;
 +}
 +
 +int intel_gt_gmch_gen8_probe(struct i915_ggtt *ggtt)
 +{
 +      struct drm_i915_private *i915 = ggtt->vm.i915;
 +      struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 +      unsigned int size;
 +      u16 snb_gmch_ctl;
 +
 +      /* TODO: We're not aware of mappable constraints on gen8 yet */
 +      if (!HAS_LMEM(i915)) {
 +              ggtt->gmadr = intel_pci_resource(pdev, 2);
 +              ggtt->mappable_end = resource_size(&ggtt->gmadr);
 +      }
 +
 +      pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 +      if (IS_CHERRYVIEW(i915))
 +              size = chv_get_total_gtt_size(snb_gmch_ctl);
 +      else
 +              size = gen8_get_total_gtt_size(snb_gmch_ctl);
 +
 +      ggtt->vm.alloc_pt_dma = alloc_pt_dma;
 +      ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
 +      ggtt->vm.lmem_pt_obj_flags = I915_BO_ALLOC_PM_EARLY;
 +
 +      ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
 +      ggtt->vm.cleanup = gen6_gmch_remove;
 +      ggtt->vm.insert_page = gen8_ggtt_insert_page;
 +      ggtt->vm.clear_range = nop_clear_range;
 +      if (intel_scanout_needs_vtd_wa(i915))
 +              ggtt->vm.clear_range = gen8_ggtt_clear_range;
 +
 +      ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
 +
 +      /*
 +       * Serialize GTT updates with aperture access on BXT if VT-d is on,
 +       * and always on CHV.
 +       */
 +      if (intel_vm_no_concurrent_access_wa(i915)) {
 +              ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
 +              ggtt->vm.insert_page    = bxt_vtd_ggtt_insert_page__BKL;
 +              ggtt->vm.bind_async_flags =
 +                      I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
 +      }
 +
 +      ggtt->invalidate = gen8_ggtt_invalidate;
 +
 +      ggtt->vm.vma_ops.bind_vma    = intel_ggtt_bind_vma;
 +      ggtt->vm.vma_ops.unbind_vma  = intel_ggtt_unbind_vma;
 +
 +      ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
 +
 +      setup_private_pat(ggtt->vm.gt->uncore);
 +
 +      return ggtt_probe_common(ggtt, size);
 +}
 +
 +int intel_gt_gmch_gen5_enable_hw(struct drm_i915_private *i915)
 +{
 +      if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
 +              return -EIO;
 +
 +      return 0;
 +}

diff --cc drivers/gpu/drm/i915/gt/intel_gt_pm.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_gt_regs.h
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_gtt.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_gtt.h
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_rc6.c
index 4f11f28816f1ac6ae2cee6b1fe507236bb6871a8,63db136cbc272270c3922a7c3e07cf6ef9b52010..b4770690e794af4889b8936d745efb6052ed7aab
--- 1/drivers/gpu/drm/i915/gt/intel_rc6.c
--- 2/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@@ -4,8 -4,8 +4,9 @@@
   */
  
  #include <linux/pm_runtime.h>
+ #include <linux/string_helpers.h>
  
 +#include "gem/i915_gem_region.h"
  #include "i915_drv.h"
  #include "i915_reg.h"
  #include "i915_vgpu.h"

diff --cc drivers/gpu/drm/i915/gt/intel_reset.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_rps.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_sseu.c
index 726d48b24ae735507b80639b860b3c76a02dda5f,614915ffbd370453b09ddd4cf7b8edbd73657e41..9881a6790574add9e872acd07362178e940a5c2d
--- 1/drivers/gpu/drm/i915/gt/intel_sseu.c
--- 2/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@@ -718,14 -713,15 +720,15 @@@ void intel_sseu_dump(const struct sseu_
        drm_printf(p, "EU total: %u\n", sseu->eu_total);
        drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
        drm_printf(p, "has slice power gating: %s\n",
-                  yesno(sseu->has_slice_pg));
+                  str_yes_no(sseu->has_slice_pg));
        drm_printf(p, "has subslice power gating: %s\n",
-                  yesno(sseu->has_subslice_pg));
-       drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
+                  str_yes_no(sseu->has_subslice_pg));
+       drm_printf(p, "has EU power gating: %s\n",
+                  str_yes_no(sseu->has_eu_pg));
  }
  
 -void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
 -                             struct drm_printer *p)
 +static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
 +                                  struct drm_printer *p)
  {
        int s, ss;
  

diff --cc drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_debugfs.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_driver.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_drv.h
index fd8a4235fd974c5a8ad07f4773b39b9efb015c1f,ce2cd6491d6d6f3de8ed633337cb898345867d31..9274417cd87afde261917182a274405ab73cff05
--- 1/drivers/gpu/drm/i915/i915_drv.h
--- 2/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@@ -1412,14 -1363,6 +1377,9 @@@ IS_SUBPLATFORM(const struct drm_i915_pr
  #define HAS_GUC_DEPRIVILEGE(dev_priv) \
        (INTEL_INFO(dev_priv)->has_guc_deprivilege)
  
- static inline bool run_as_guest(void)
- {
-       return !hypervisor_is_type(X86_HYPER_NATIVE);
- }
- 
 +#define HAS_PERCTX_PREEMPT_CTRL(i915) \
 +      ((GRAPHICS_VER(i915) >= 9) &&  GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
 +
  #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
                                              IS_ALDERLAKE_S(dev_priv))
  

diff --cc drivers/gpu/drm/i915/i915_gpu_error.c
index 7d09f92695af46389f2e8c7401d080105b919f59,d0e7ee7b07df437df565c92df04971a9170c0b9a..0512c66fa4f3f1fd48dcd4e60c454deb51fa6ea2
--- 1/drivers/gpu/drm/i915/i915_gpu_error.c
--- 2/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@@ -704,33 -713,26 +707,33 @@@ static void err_print_gt_info(struct dr
        struct drm_printer p = i915_error_printer(m);
  
        intel_gt_info_print(&gt->info, &p);
 -      intel_sseu_print_topology(&gt->info.sseu, &p);
 +      intel_sseu_print_topology(gt->_gt->i915, &gt->info.sseu, &p);
  }
  
 -static void err_print_gt(struct drm_i915_error_state_buf *m,
 -                       struct intel_gt_coredump *gt)
 +static void err_print_gt_display(struct drm_i915_error_state_buf *m,
 +                               struct intel_gt_coredump *gt)
 +{
 +      err_printf(m, "IER: 0x%08x\n", gt->ier);
 +      err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr);
 +}
 +
 +static void err_print_gt_global_nonguc(struct drm_i915_error_state_buf *m,
 +                                     struct intel_gt_coredump *gt)
  {
 -      const struct intel_engine_coredump *ee;
        int i;
  
-       err_printf(m, "GT awake: %s\n", yesno(gt->awake));
+       err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake));
        err_printf(m, "EIR: 0x%08x\n", gt->eir);
 -      err_printf(m, "IER: 0x%08x\n", gt->ier);
 +      err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);
 +
        for (i = 0; i < gt->ngtier; i++)
                err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]);
 -      err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);
 -      err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake);
 -      err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr);
 +}
  
 -      for (i = 0; i < gt->nfence; i++)
 -              err_printf(m, "  fence[%d] = %08llx\n", i, gt->fence[i]);
 +static void err_print_gt_global(struct drm_i915_error_state_buf *m,
 +                              struct intel_gt_coredump *gt)
 +{
 +      err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake);
  
        if (IS_GRAPHICS_VER(m->i915, 6, 11)) {
                err_printf(m, "ERROR: 0x%08x\n", gt->error);
@@@ -843,43 -826,13 +846,35 @@@ static void __err_print_to_sgl(struct d
  
        err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
  
-       if (HAS_DMC(m->i915)) {
-               struct intel_dmc *dmc = &m->i915->dmc;
+       intel_dmc_print_error_state(m, m->i915);
  
-               err_printf(m, "DMC loaded: %s\n",
-                          yesno(intel_dmc_has_payload(m->i915) != 0));
-               err_printf(m, "DMC fw version: %d.%d\n",
-                          DMC_VERSION_MAJOR(dmc->version),
-                          DMC_VERSION_MINOR(dmc->version));
-       }
- 
-       err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
-       err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
+       err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock));
+       err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended));
  
 -      if (error->gt)
 -              err_print_gt(m, error->gt);
 +      if (error->gt) {
 +              bool print_guc_capture = false;
 +
 +              if (error->gt->uc && error->gt->uc->is_guc_capture)
 +                      print_guc_capture = true;
 +
 +              err_print_gt_display(m, error->gt);
 +              err_print_gt_global_nonguc(m, error->gt);
 +              err_print_gt_fences(m, error->gt);
 +
 +              /*
 +               * GuC dumped global, eng-class and eng-instance registers together
 +               * as part of engine state dump so we print in err_print_gt_engines
 +               */
 +              if (!print_guc_capture)
 +                      err_print_gt_global(m, error->gt);
 +
 +              err_print_gt_engines(m, error->gt);
 +
 +              if (error->gt->uc)
 +                      err_print_uc(m, error->gt->uc);
 +
 +              err_print_gt_info(m, error->gt);
 +      }
  
        if (error->overlay)
                intel_overlay_print_error_state(m, error->overlay);

diff --cc drivers/gpu/drm/i915/i915_gpu_error.h
index 72d86071c0d1b67e30e7f46fabec36b43c18e809,88ce3a08f555fead14596fb992d9b8cc0d9cdba1..a611abacd9c2c089e3d1278e6d4eac24a6a148f9
--- 1/drivers/gpu/drm/i915/i915_gpu_error.h
--- 2/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@@ -298,8 -281,14 +298,14 @@@ void i915_disable_error_state(struct dr
  
  #else
  
+ __printf(2, 3)
+ static inline void
+ i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
+ {
+ }
+ 
  static inline void
 -i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask)
 +i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
  {
  }
  

diff --cc drivers/gpu/drm/i915/i915_params.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_reg.h
Simple merge

diff --cc drivers/gpu/drm/i915/intel_memory_region.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_memory_region.h
Simple merge

diff --cc drivers/gpu/drm/i915/intel_uncore.c
Simple merge