#define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
#define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
-#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
-#define PHY_WAIT_MICRO_SECONDS 10
-
/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET 0x2
/* Wait for all Rx activity to terminate. */
/* Check port cause register that all Rx queues are stopped */
while (rdl(mp, RXQ_COMMAND(port_num)) & 0xFF)
- udelay(PHY_WAIT_MICRO_SECONDS);
+ udelay(10);
}
return queues;
/* Wait for all Tx activity to terminate. */
/* Check port cause register that all Tx queues are stopped */
while (rdl(mp, TXQ_COMMAND(port_num)) & 0xFF)
- udelay(PHY_WAIT_MICRO_SECONDS);
+ udelay(10);
/* Wait for Tx FIFO to empty */
while (rdl(mp, PORT_STATUS(port_num)) & ETH_PORT_TX_FIFO_EMPTY)
- udelay(PHY_WAIT_MICRO_SECONDS);
+ udelay(10);
}
return queues;
/* wait for the SMI register to become available */
for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) {
- if (i == PHY_WAIT_ITERATIONS) {
+ if (i == 1000) {
printk("%s: PHY busy timeout\n", mp->dev->name);
goto out;
}
- udelay(PHY_WAIT_MICRO_SECONDS);
+ udelay(10);
}
writel((phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ,
/* now wait for the data to be valid */
for (i = 0; !(readl(smi_reg) & ETH_SMI_READ_VALID); i++) {
- if (i == PHY_WAIT_ITERATIONS) {
+ if (i == 1000) {
printk("%s: PHY read timeout\n", mp->dev->name);
goto out;
}
- udelay(PHY_WAIT_MICRO_SECONDS);
+ udelay(10);
}
*value = readl(smi_reg) & 0xffff;
/* wait for the SMI register to become available */
for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) {
- if (i == PHY_WAIT_ITERATIONS) {
+ if (i == 1000) {
printk("%s: PHY busy timeout\n", mp->dev->name);
goto out;
}
- udelay(PHY_WAIT_MICRO_SECONDS);
+ udelay(10);
}
writel((phy_addr << 16) | (phy_reg << 21) |