Merge tag 'v3.10-rc2' into drm-intel-next-queued

Backmerge Linux 3.10-rc2 since the various (rather trivial) conflicts
grew a bit out of hand. intel_dp.c has the only real functional
conflict since the logic changed while dev_priv->edp.bpp was moved
around.

Also squash in a whitespace fixup from Ben Widawsky for
i915_gem_gtt.c, git seems to do something pretty strange in there
(which I don't fully understand tbh).

Conflicts:
	drivers/gpu/drm/i915/i915_reg.h
	drivers/gpu/drm/i915/intel_dp.c

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --cc drivers/gpu/drm/Makefile
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem_gtt.c
index 85b3d5d,bdb0d77..ddad13f
--- 1/drivers/gpu/drm/i915/i915_gem_gtt.c
--- 2/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@@ -269,16 -233,8 +269,15 @@@ static int gen6_ppgtt_init(struct i915_
        /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
         * entries. For aliasing ppgtt support we just steal them at the end for
         * now. */
-       first_pd_entry_in_global_pt =
-               gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
 -       first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);
++      first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);
  
 +      if (IS_HASWELL(dev)) {
 +              ppgtt->pte_encode = hsw_pte_encode;
 +      } else if (IS_VALLEYVIEW(dev)) {
 +              ppgtt->pte_encode = byt_pte_encode;
 +      } else {
 +              ppgtt->pte_encode = gen6_pte_encode;
 +      }
        ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
        ppgtt->enable = gen6_ppgtt_enable;
        ppgtt->clear_range = gen6_ppgtt_clear_range;

diff --cc drivers/gpu/drm/i915/i915_reg.h
index 7af7ae6,2d6b62e..e4cf382
--- 1/drivers/gpu/drm/i915/i915_reg.h
--- 2/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@@ -2785,19 -2646,18 +2783,20 @@@
   * which is after the LUTs, so we want the bytes for our color format.
   * For our current usage, this is always 3, one byte for R, G and B.
   */
 -#define _PIPEA_GMCH_DATA_M                    0x70050
 -#define _PIPEB_GMCH_DATA_M                    0x71050
 +#define _PIPEA_DATA_M_G4X     0x70050
 +#define _PIPEB_DATA_M_G4X     0x71050
  
  /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
- #define   PIPE_GMCH_DATA_M_TU_SIZE_MASK               (0x3f << 25)
- #define   PIPE_GMCH_DATA_M_TU_SIZE_SHIFT      25
+ #define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */
 +#define  TU_SIZE_SHIFT                25
+ #define  TU_SIZE_MASK           (0x3f << 25)
  
- #define   PIPE_GMCH_DATA_M_MASK                       (0xffffff)
+ #define  DATA_LINK_M_N_MASK   (0xffffff)
+ #define  DATA_LINK_N_MAX      (0x800000)
  
 -#define _PIPEA_GMCH_DATA_N                    0x70054
 -#define _PIPEB_GMCH_DATA_N                    0x71054
 +#define _PIPEA_DATA_N_G4X     0x70054
 +#define _PIPEB_DATA_N_G4X     0x71054
 +#define   PIPE_GMCH_DATA_N_MASK                       (0xffffff)
  
  /*
   * Computing Link M and N values for the Display Port link

diff --cc drivers/gpu/drm/i915/intel_crt.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_ddi.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_display.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_dp.c
index 2bb4009,3d704b7..6ba9f09
--- 1/drivers/gpu/drm/i915/intel_dp.c
--- 2/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@@ -720,18 -701,9 +720,9 @@@ intel_dp_compute_config(struct intel_en
  
        /* Walk through all bpp values. Luckily they're all nicely spaced with 2
         * bpc in between. */
-       bpp = pipe_config->pipe_bpp;
- 
-       /*
-        * eDP panels are really fickle, try to enfore the bpp the firmware
-        * recomments. This means we'll up-dither 16bpp framebuffers on
-        * high-depth panels.
-        */
-       if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
-               DRM_DEBUG_KMS("forcing bpp for eDP panel to BIOS-provided %i\n",
-                             dev_priv->vbt.edp_bpp);
-               bpp = dev_priv->vbt.edp_bpp;
-       }
+       bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
 -      if (is_edp(intel_dp) && dev_priv->edp.bpp)
 -              bpp = min_t(int, bpp, dev_priv->edp.bpp);
++      if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
++              bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
  
        for (; bpp >= 6*3; bpp -= 2*3) {
                mode_rate = intel_dp_link_required(target_clock, bpp);
@@@ -782,10 -755,6 +774,8 @@@ found
                               target_clock, adjusted_mode->clock,
                               &pipe_config->dp_m_n);
  
-       pipe_config->pipe_bpp = bpp;
- 
 +      intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 +
        return true;
  }
  
@@@ -1400,15 -1379,8 +1390,16 @@@ static void intel_enable_dp(struct inte
        ironlake_edp_panel_on(intel_dp);
        ironlake_edp_panel_vdd_off(intel_dp, true);
        intel_dp_complete_link_train(intel_dp);
+       intel_dp_stop_link_train(intel_dp);
        ironlake_edp_backlight_on(intel_dp);
 +
 +      if (IS_VALLEYVIEW(dev)) {
 +              struct intel_digital_port *dport =
 +                      enc_to_dig_port(&encoder->base);
 +              int channel = vlv_dport_to_channel(dport);
 +
 +              vlv_wait_port_ready(dev_priv, channel);
 +      }
  }
  
  static void intel_pre_enable_dp(struct intel_encoder *encoder)

diff --cc drivers/gpu/drm/i915/intel_drv.h
Simple merge

diff --cc drivers/gpu/drm/i915/intel_dvo.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_hdmi.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_opregion.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_pm.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_sdvo.c
Simple merge