di: aptimise di flow, add some protection [1/1]

PD#SWPL-3976

Problem:
To prevent “stall when access DDR through memory interface”

Solution:
1.aptimise NRWR register access flow
2.add arb on/off and status check
3.add reset protect
4.add nr_en disable before arb status check
5.add nr_write_done sel
6.modify VPU_WRARB_MODE_L2C1 from vlsi feijun's suggest

Verify:
tl1, txlx

Change-Id: Ifb0f4f0502d957ffb2b07805575c27f4166d5717
Signed-off-by: Yong Qin <yong.qin@amlogic.com>

diff --git a/drivers/amlogic/media/common/vpu/vpu_power_init.c b/drivers/amlogic/media/common/vpu/vpu_power_init.c
index 07c5c84..7858607 100644 (file)
--- a/drivers/amlogic/media/common/vpu/vpu_power_init.c
+++ b/drivers/amlogic/media/common/vpu/vpu_power_init.c
@@ -60,7 +60,8 @@ void vpu_module_init_config(void)
        vpu_vcbus_write(VPU_RDARB_MODE_L1C1, 0x210000);
        vpu_vcbus_write(VPU_RDARB_MODE_L1C2, 0x10000);
        vpu_vcbus_write(VPU_RDARB_MODE_L2C1, 0x900000);
-       vpu_vcbus_write(VPU_WRARB_MODE_L2C1, 0x20000);
+       /*from vlsi feijun*/
+       vpu_vcbus_write(VPU_WRARB_MODE_L2C1, 0x170000/*0x20000*/);
 
        if (vpu_debug_print_flag)
                VPUPR("%s finish\n", __func__);

diff --git a/drivers/amlogic/media/deinterlace/deinterlace.c b/drivers/amlogic/media/deinterlace/deinterlace.c
index 5e793b8..c78ccab 100644 (file)
--- a/drivers/amlogic/media/deinterlace/deinterlace.c
+++ b/drivers/amlogic/media/deinterlace/deinterlace.c
@@ -129,7 +129,7 @@ static di_dev_t *de_devp;
 static dev_t di_devno;
 static struct class *di_clsp;
 
-static const char version_s[] = "2019-02-26a";
+static const char version_s[] = "2019-02-27a";
 
 static int bypass_state = 1;
 static int bypass_all;
@@ -3382,7 +3382,7 @@ static bool pps_en;
 module_param_named(pps_en, pps_en, bool, 0644);
 static unsigned int pps_position = 1;
 module_param_named(pps_position, pps_position, uint, 0644);
-static unsigned int pre_enable_mask = 3;
+static unsigned int pre_enable_mask = 3;/*bit0:ma bit1:mc*/
 module_param_named(pre_enable_mask, pre_enable_mask, uint, 0644);
 
 static unsigned char pre_de_buf_config(void)
@@ -4297,6 +4297,10 @@ static irqreturn_t de_irq(int irq, void *dev_instance)
                trace_di_pre("PRE-IRQ-0",
                        di_pre_stru.field_count_for_cont,
                        di_pre_stru.irq_time[0]);
+               /*add from valsi wang.feng*/
+               di_arb_sw(false);
+               di_arb_sw(true);
+
                if (mcpre_en) {
                        get_mcinfo_from_reg_in_irq();
                        if ((is_meson_gxlx_cpu() &&
@@ -6177,6 +6181,8 @@ static void di_reg_process_irq(void)
                        de_devp->flags |= DI_VPU_CLKB_SET;
                        enable_di_pre_mif(false, mcpre_en);
                        di_pre_gate_control(true, mcpre_en);
+                       di_rst_protect(true);/*2019-01-22 by VLSI feng.wang*/
+                       di_pre_nr_wr_done_sel(true);
                        nr_gate_control(true);
                } else {
                        /* if mcdi enable DI_CLKG_CTRL should be 0xfef60000 */

diff --git a/drivers/amlogic/media/deinterlace/deinterlace_hw.c b/drivers/amlogic/media/deinterlace/deinterlace_hw.c
index 0b1bf38..2c157bf 100644 (file)
--- a/drivers/amlogic/media/deinterlace/deinterlace_hw.c
+++ b/drivers/amlogic/media/deinterlace/deinterlace_hw.c
@@ -643,13 +643,34 @@ static void set_di_nrwr_mif(struct DI_SIM_MIF_s *nrwr_mif,
        /* wr ext en from gxtvbb */
        RDMA_WR_BITS(DI_NRWR_Y, 1, 15, 1);
        RDMA_WR_BITS(DI_NRWR_Y, 3, 30, 2);
+       #if 0
        RDMA_WR(DI_NRWR_CTRL, nrwr_mif->canvas_num|
                        (urgent<<16)|
                        2<<26 |
                        1<<30);
+       #endif
        RDMA_WR_BITS(DI_NRWR_Y, nrwr_mif->bit_mode&0x1, 14, 1);
+       #if 0
        if ((nrwr_mif->bit_mode&0x3) == 0x3)
                RDMA_WR_BITS(DI_NRWR_CTRL, 0x3, 22, 2);
+       #endif
+
+       /*fix 1080i crash when di work on low speed*/
+       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL) &&
+                               ((nrwr_mif->bit_mode&0x3) == 0x3)) {
+               RDMA_WR(DI_NRWR_CTRL, nrwr_mif->canvas_num|
+                       (urgent<<16)|
+                       3<<22 |
+                       1<<24 |
+                       2<<26 |/*burst_lim 1->2 2->4*/
+                       1<<30); /* urgent bit 16 */
+       } else {
+               RDMA_WR(DI_NRWR_CTRL, nrwr_mif->canvas_num|
+                       (urgent<<16)|
+                       1<<24 |
+                       2<<26 |/*burst_lim 1->2 2->4*/
+                       1<<30); /* urgent bit 16 */
+       }
 }
 
 void di_interrupt_ctrl(unsigned char ma_en,
@@ -3363,6 +3384,130 @@ void di_post_gate_control(bool gate)
        }
 
 }
+
+void di_async_reset(void)      /*2019-01-17 add for debug*/
+{
+       /*wrmif async reset*/
+       RDMA_WR_BITS(VIUB_SW_RESET, 1, 14, 1);
+       RDMA_WR_BITS(VIUB_SW_RESET, 0, 14, 1);
+}
+
+void di_pre_rst_frame(void)
+{
+       RDMA_WR(DI_PRE_CTRL, Rd(DI_PRE_CTRL) | (1 << 31));
+}
+
+void di_pre_nr_enable(bool on)
+{
+       if (on)
+               RDMA_WR_BITS(DI_PRE_CTRL, 1, 0, 1);
+       else
+               RDMA_WR_BITS(DI_PRE_CTRL, 0, 0, 1);
+}
+
+void di_pre_nr_wr_done_sel(bool on)
+{
+       if (on) /*wait till response finish*/
+               RDMA_WR_BITS(DI_CANVAS_URGENT0, 1, 8, 1);
+       else
+               RDMA_WR_BITS(DI_CANVAS_URGENT0, 0, 0, 1);
+
+}
+
+void di_rst_protect(bool on)
+{
+       if (on)
+               RDMA_WR_BITS(DI_NRWR_Y, 1, 15, 1);
+       else
+               RDMA_WR_BITS(DI_NRWR_Y, 0, 15, 1);
+}
+
+/*bit 10,12,16,18 [3:1]*/
+/*#define PRE_ID_MASK  (0x5140e) */
+#define PRE_ID_MASK    (0x51400)
+
+/*bit 8,10,14,16*/
+#define PRE_ID_MASK_TL1        (0x14500)
+
+bool di_pre_idle(void)
+{
+       bool ret = false;
+
+       if (is_meson_tl1_cpu()) {
+               if ((RDMA_RD(VPU_ARB_DBG_STAT_L1C1_TL1) &
+                       PRE_ID_MASK_TL1) == PRE_ID_MASK_TL1)
+                       ret = true;
+       } else {
+               if ((RDMA_RD(VPU_ARB_DBG_STAT_L1C1) &
+                       PRE_ID_MASK) == PRE_ID_MASK)
+                       ret = true;
+       }
+
+       return ret;
+}
+
+void di_arb_sw(bool on)
+{
+       int i;
+       u32 REG_VPU_WRARB_REQEN_SLV_L1C1;
+       u32 REG_VPU_RDARB_REQEN_SLV_L1C1;
+       u32 REG_VPU_ARB_DBG_STAT_L1C1;
+       u32 WRARB_onval;
+       u32 WRARB_offval;
+
+       if (is_meson_tl1_cpu()) {
+               REG_VPU_WRARB_REQEN_SLV_L1C1 = VPU_WRARB_REQEN_SLV_L1C1_TL1;
+               REG_VPU_RDARB_REQEN_SLV_L1C1 = VPU_RDARB_REQEN_SLV_L1C1_TL1;
+               REG_VPU_ARB_DBG_STAT_L1C1 = VPU_ARB_DBG_STAT_L1C1_TL1;
+               if (on)
+                       WRARB_onval = 0x3f;
+               else
+                       WRARB_offval = 0x3e;
+       } else {
+               REG_VPU_WRARB_REQEN_SLV_L1C1 = VPU_WRARB_REQEN_SLV_L1C1;
+               REG_VPU_RDARB_REQEN_SLV_L1C1 = VPU_RDARB_REQEN_SLV_L1C1;
+               REG_VPU_ARB_DBG_STAT_L1C1 = VPU_ARB_DBG_STAT_L1C1;
+               if (on)
+                       WRARB_onval = 0x3f;
+               else
+                       WRARB_offval = 0x2b;
+       }
+
+       if (on) {
+               RDMA_WR(REG_VPU_WRARB_REQEN_SLV_L1C1, WRARB_onval);
+               RDMA_WR(REG_VPU_RDARB_REQEN_SLV_L1C1, 0xffff);
+       } else {
+               /*close arb:*/
+               RDMA_WR(REG_VPU_WRARB_REQEN_SLV_L1C1, WRARB_offval);
+               RDMA_WR(REG_VPU_RDARB_REQEN_SLV_L1C1, 0xf1f1);
+
+               di_pre_nr_enable(false); /*by Feijun*/
+               /*check status*/
+               if (!di_pre_idle()) {
+                       pr_err("di:err1:0x[%x]\n",
+                               RDMA_RD(REG_VPU_ARB_DBG_STAT_L1C1));
+                       for (i = 0; i < 9; i++) {
+                               if (di_pre_idle())
+                                       break;
+                       }
+
+                       if (!di_pre_idle()) {
+                               di_pre_rst_frame();
+
+                               for (i = 0; i < 9; i++) {
+                                       if (di_pre_idle())
+                                               break;
+                               }
+                               if (!di_pre_idle())
+                                       pr_err("di:err2\n");
+
+                       }
+               }
+               if (di_pre_idle())
+                       di_async_reset();
+       }
+}
+
 /*
  * enable/disable mc pre mif mcinfo&mv
  */
@@ -3464,10 +3609,10 @@ static void di_pre_data_mif_ctrl(bool enable)
                }
                #endif
                /* nrwr no clk gate en=0 */
-               RDMA_WR_BITS(DI_NRWR_CTRL, 0, 24, 1);
+               /*RDMA_WR_BITS(DI_NRWR_CTRL, 0, 24, 1);*/
        } else {
                /* nrwr no clk gate en=1 */
-               RDMA_WR_BITS(DI_NRWR_CTRL, 1, 24, 1);
+               /*RDMA_WR_BITS(DI_NRWR_CTRL, 1, 24, 1);*/
                /* nr wr req en =0 */
                RDMA_WR_BITS(DI_PRE_CTRL, 0, 0, 1);
                /* disable input mif*/

diff --git a/drivers/amlogic/media/deinterlace/deinterlace_hw.h b/drivers/amlogic/media/deinterlace/deinterlace_hw.h
index dbaa344..eb30353 100644 (file)
--- a/drivers/amlogic/media/deinterlace/deinterlace_hw.h
+++ b/drivers/amlogic/media/deinterlace/deinterlace_hw.h
@@ -196,4 +196,8 @@ extern int di_print(const char *fmt, ...);
 extern void di_patch_post_update_mc(void);
 extern void di_patch_post_update_mc_sw(unsigned int cmd, bool on);
 
+extern void di_rst_protect(bool on);
+extern void di_pre_nr_wr_done_sel(bool on);
+extern void di_arb_sw(bool on);
+
 #endif

diff --git a/drivers/amlogic/media/deinterlace/register.h b/drivers/amlogic/media/deinterlace/register.h
index adeedbb..cc73dc2 100644 (file)
--- a/drivers/amlogic/media/deinterlace/register.h
+++ b/drivers/amlogic/media/deinterlace/register.h
@@ -43,8 +43,15 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr,
        unsigned int val, unsigned int start, unsigned int len);
 
 #define HHI_VPU_CLKB_CNTL      0x83
-#define VPU_WRARB_REQEN_SLV_L1C1       ((0x2795)) /* << 2) + 0xd0100000) */
-#define VPU_ARB_DBG_STAT_L1C1          ((0x27b4)) /* << 2) + 0xd0100000) */
+
+#define VPU_WRARB_REQEN_SLV_L1C1       0x2795
+#define VPU_RDARB_REQEN_SLV_L1C1       0x2791
+#define VPU_ARB_DBG_STAT_L1C1          0x27b4
+
+#define VPU_WRARB_REQEN_SLV_L1C1_TL1   0x2055
+#define VPU_RDARB_REQEN_SLV_L1C1_TL1   0x2051
+#define VPU_ARB_DBG_STAT_L1C1_TL1              0x205a
+
 
 #define VIUB_SW_RESET                                  0x2001
 #define VIUB_SW_RESET0                                 0x2002

diff --git a/include/linux/amlogic/media/registers/regs/vpp_regs.h b/include/linux/amlogic/media/registers/regs/vpp_regs.h
index b59bc6c..af2df43 100644 (file)
--- a/include/linux/amlogic/media/registers/regs/vpp_regs.h
+++ b/include/linux/amlogic/media/registers/regs/vpp_regs.h
@@ -251,5 +251,9 @@
 /* after g12b */
 #define SRSHARP0_SHARP_SYNC_CTRL 0x3eb0
 #define SRSHARP1_SHARP_SYNC_CTRL 0x3fb0
+
+#define VPU_RDARB_MODE_L2C1          0x279d
+#define VPU_WRARB_MODE_L2C1          0x27a2
+
 #endif