that clobbers r19. Fix pasto that overflowed sigcontext.v_reserve.
* sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S: Fix pasto
that clobbers r19.
* sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S: Fix pasto
that clobbers r19. Fix pasto that overflowed sigcontext.v_reserve.
* sysdeps/unix/sysv/linux/powerpc/powerpc64/getcontext.S:
Fix setting of sigcontext.v_regs. Fix pasto that clobbers r19.
Fix pasto that overflowed sigcontext.v_reserve.
* sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S:
Fix pasto that clobbers r19.
* sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S: Fix setting
of sigcontext.v_regs. Fix pasto that clobbers r19. Fix pasto that
overflowed sigcontext.v_reserve.
+2004-06-15 Steven Munroe <sjmunroe@us.ibm.com>
+
+ * sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext.S: Fix pasto
+ that clobbers r19. Fix pasto that overflowed sigcontext.v_reserve.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S: Fix pasto
+ that clobbers r19.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S: Fix pasto
+ that clobbers r19. Fix pasto that overflowed sigcontext.v_reserve.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc64/getcontext.S:
+ Fix setting of sigcontext.v_regs. Fix pasto that clobbers r19.
+ Fix pasto that overflowed sigcontext.v_reserve.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S:
+ Fix pasto that clobbers r19.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S: Fix setting
+ of sigcontext.v_regs. Fix pasto that clobbers r19. Fix pasto that
+ overflowed sigcontext.v_reserve.
+
2004-05-04 H.J. Lu <hongjiu.lu@intel.com>
[BZ #150]
addi r9,r9,32
stvx v18,0,r10
- stvx v11,0,r9
- addi r19,r10,32
+ stvx v19,0,r9
+ addi r10,r10,32
addi r9,r9,32
stvx v20,0,r10
addi r10,r10,32
addi r9,r9,32
- stvx v10,0,r10
- stvx v11,0,r9
- addi r10,r10,32
- addi r9,r9,32
-
mfvscr v0
mfspr r0,VRSAVE
stvx v0,0,r10
addi r9,r9,32
lvx v18,0,r10
- lvx v11,0,r9
- addi r19,r10,32
+ lvx v19,0,r9
+ addi r10,r10,32
addi r9,r9,32
lvx v20,0,r10
addi r9,r9,32
stvx v18,0,r10
- stvx v11,0,r9
- addi r19,r10,32
+ stvx v19,0,r9
+ addi r10,r10,32
addi r9,r9,32
stvx v20,0,r10
addi r10,r10,32
addi r9,r9,32
- stvx v10,0,r10
- stvx v11,0,r9
- addi r10,r10,32
- addi r9,r9,32
-
mfvscr v0
mfspr r0,VRSAVE
stvx v0,0,r10
addi r9,r9,32
lvx v18,0,r10
- lvx v11,0,r9
- addi r19,r10,32
+ lvx v19,0,r9
+ addi r10,r10,32
addi r9,r9,32
lvx v20,0,r10
stfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r3)
ld r5,.LC__dl_hwcap@toc(r2)
- li r10,0
# ifdef SHARED
/* Load _rtld-global._dl_hwcap. */
ld r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r5)
# else
ld r5,0(r5) /* Load extern _dl_hwcap. */
-# endif
- andis. r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
- beq L(has_no_vec)
-
+# endif
la r10,(SIGCONTEXT_V_RESERVE+8)(r3)
la r9,(SIGCONTEXT_V_RESERVE+24)(r3)
+
+ andis. r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
+
clrrdi r10,r10,4
+ beq L(has_no_vec)
clrrdi r9,r9,4
-
+ mr r5,r10 /* Capture *v_regs value in r5. */
+
stvx v0,0,r10
stvx v1,0,r9
addi r10,r10,32
addi r9,r9,32
stvx v18,0,r10
- stvx v11,0,r9
- addi r19,r10,32
+ stvx v19,0,r9
+ addi r10,r10,32
addi r9,r9,32
stvx v20,0,r10
addi r10,r10,32
addi r9,r9,32
- stvx v10,0,r10
- stvx v11,0,r9
- addi r10,r10,32
- addi r9,r9,32
-
mfvscr v0
mfspr r0,VRSAVE
stvx v0,0,r10
Store either a NULL or a quadword aligned pointer to the Vector register
array into *v_regs.
*/
- std r10,(SIGCONTEXT_V_REGS_PTR)(r3)
+ std r5,(SIGCONTEXT_V_REGS_PTR)(r3)
addi r5,r3,UCONTEXT_SIGMASK
li r4,0
addi r9,r9,32
lvx v18,0,r10
- lvx v11,0,r9
- addi r19,r10,32
+ lvx v19,0,r9
+ addi r10,r10,32
addi r9,r9,32
lvx v20,0,r10
stfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r3)
ld r8,.LC__dl_hwcap@toc(r2)
- li r10,0
#ifdef SHARED
/* Load _rtld-global._dl_hwcap. */
ld r8,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r8)
#else
ld r8,0(r8) /* Load extern _dl_hwcap. */
#endif
- andis. r8,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
- beq L(has_no_vec)
-
la r10,(SIGCONTEXT_V_RESERVE+8)(r3)
la r9,(SIGCONTEXT_V_RESERVE+24)(r3)
+
+ andis. r8,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
+
clrrdi r10,r10,4
+ beq L(has_no_vec)
+
clrrdi r9,r9,4
+ mr r8,r10 /* Capture *v_regs value in r5. */
stvx v0,0,r10
stvx v1,0,r9
addi r9,r9,32
stvx v18,0,r10
- stvx v11,0,r9
- addi r19,r10,32
+ stvx v19,0,r9
+ addi r10,r10,32
addi r9,r9,32
stvx v20,0,r10
addi r10,r10,32
addi r9,r9,32
- stvx v10,0,r10
- stvx v11,0,r9
- addi r10,r10,32
- addi r9,r9,32
-
mfvscr v0
mfspr r0,VRSAVE
stvx v0,0,r10
Store either a NULL or a quadword aligned pointer to the Vector register
array into *v_regs.
*/
- std r10,(SIGCONTEXT_V_REGS_PTR)(r3)
+ std r8,(SIGCONTEXT_V_REGS_PTR)(r3)
mr r31,r4
addi r5,r3,UCONTEXT_SIGMASK
addi r9,r9,32
lvx v18,0,r10
- lvx v11,0,r9
- addi r19,r10,32
+ lvx v19,0,r9
+ addi r10,r10,32
addi r9,r9,32
lvx v20,0,r10