# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_STARFIVE_JH7110) += jh7110-visionfive-v2.dtb jh7110-evb.dtb jh7110-fpga.dtb
+subdir-y += evb-overlay
+dtb-$(CONFIG_SOC_STARFIVE_JH7110) += jh7110-visionfive-v2.dtb \
+ jh7110-evb.dtb \
+ jh7110-fpga.dtb \
+ jh7110-evb-can-pdm-pwmdac.dtb \
+ jh7110-evb-dvp-rgb2hdmi.dtb \
+ jh7110-evb-pcie-i2s-sd.dtb \
+ jh7110-evb-spi-uart2.dtb \
+ jh7110-evb-uart1-rgb2hdmi.dtb \
+ jh7110-evb-uart4-emmc.dtb \
+ jh7110-evb-uart5-pwm-i2c-tdm.dtb
--- /dev/null
+&sound {\r
+\r
+ simple-audio-card,dai-link@1 {\r
+ reg = <0>;\r
+ format = "left_j";\r
+ bitclock-master = <&sndcpu0>;\r
+ frame-master = <&sndcpu0>;\r
+ status = "okay";\r
+\r
+ sndcpu0: cpu {\r
+ sound-dai = <&spdif0>;\r
+ };\r
+\r
+ codec {\r
+ sound-dai = <&spdif_transmitter>;\r
+ };\r
+ };\r
+\r
+};\r
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_STARFIVE_JH7110) += jh7110-evb-overlay-can.dtbo \
+ jh7110-evb-overlay-sdio.dtbo \
+ jh7110-evb-overlay-spi.dtbo \
+ jh7110-evb-overlay-uart4-emmc.dtbo \
+ jh7110-evb-overlay-uart5-pwm.dtbo \
+ jh7110-evb-overlay-rgb2hdmi.dtbo
--- /dev/null
+/dts-v1/;
+/plugin/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/starfive,jh7110-pinfunc.h>
+/ {
+ compatible = "starfive,jh7110";
+
+ //can0
+ fragment@0 {
+ target-path = "/soc/can@130d0000";
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ //can1
+ fragment@1 {
+ target-path = "/soc/can@130e0000";
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
+
+
--- /dev/null
+/dts-v1/;
+/plugin/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/starfive,jh7110-pinfunc.h>
+/ {
+ compatible = "starfive,jh7110";
+
+ //hdmi_output
+ fragment@0 {
+ target-path = "/soc/tda988x_pin";
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ //uart1
+ fragment@1 {
+ target-path = "/soc/serial@10010000";
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
+
+
--- /dev/null
+/dts-v1/;
+/plugin/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/starfive,jh7110-pinfunc.h>
+/ {
+ compatible = "starfive,jh7110";
+
+ //gpio
+ fragment@0 {
+ target-path = "/soc/gpio@13040000";
+ __overlay__ {
+ dt_sdcard1_pins: dt-sdcard1-pins {
+ sdcard1-pins0 {
+ sf,pins = <PAD_GPIO56>;
+ sf,pinmux = <PAD_GPIO56_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CCLK_OUT>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ sdcard1-pins1 {
+ sf,pins = <PAD_GPIO50>;
+ sf,pinmux = <PAD_GPIO50_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CCMD_OUT>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CCMD_OUT_EN>;
+ sf,pin-gpio-din = <GPI_SDIO1_CCMD_IN>;
+ };
+
+ sdcard1-pins2 {
+ sf,pins = <PAD_GPIO49>;
+ sf,pinmux = <PAD_GPIO49_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_0>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_0>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_0>;
+ };
+
+ sdcard1-pins3 {
+ sf,pins = <PAD_GPIO45>;
+ sf,pinmux = <PAD_GPIO45_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_1>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_1>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_1>;
+ };
+
+ sdcard1-pins4 {
+ sf,pins = <PAD_GPIO62>;
+ sf,pinmux = <PAD_GPIO62_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_2>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_2>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_2>;
+ };
+
+ sdcard1-pins5 {
+ sf,pins = <PAD_GPIO40>;
+ sf,pinmux = <PAD_GPIO40_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_3>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_3>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_3>;
+ };
+ };
+ };
+ };
+
+ //uart3
+ fragment@1 {
+ target-path = "/soc/serial@12000000";
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ //i2c0
+ fragment@2 {
+ target-path = "/soc/i2c@10030000";
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ //sdio1
+ fragment@3 {
+ target-path = "/soc/sdio1@16020000";
+ __overlay__ {
+ clock-frequency = <102400000>;
+ max-frequency = <100000000>;
+ card-detect-delay = <300>;
+ bus-width = <4>;
+ broken-cd;
+ cap-sd-highspeed;
+ post-power-on-delay-ms = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dt_sdcard1_pins>;
+ status = "okay";
+ };
+ };
+};
+
+
--- /dev/null
+/dts-v1/;
+/plugin/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/starfive,jh7110-pinfunc.h>
+/ {
+ compatible = "starfive,jh7110";
+
+ //spi0
+ fragment@0 {
+ target-path = "/soc/spi@10060000";
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ //spi1
+ fragment@1 {
+ target-path = "/soc/spi@10070000";
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ //spi2
+ fragment@2 {
+ target-path = "/soc/spi@10080000";
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+
+ //spi3
+ fragment@3 {
+ target-path = "/soc/spi@12070000";
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+
+ //spi4
+ fragment@4 {
+ target-path = "/soc/spi@12080000";
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+
+ //spi5
+ fragment@5 {
+ target-path = "/soc/spi@12090000";
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+
+ //spi6
+ fragment@6 {
+ target-path = "/soc/spi@120A0000";
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+
+ //uart2
+ fragment@7 {
+ target-path = "/soc/serial@10020000";
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
+
+
--- /dev/null
+/dts-v1/;
+/plugin/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/starfive,jh7110-pinfunc.h>
+/ {
+ compatible = "starfive,jh7110";
+
+ //gpio
+ fragment@0 {
+ target-path = "/soc/gpio@13040000";
+ __overlay__ {
+ dt_emmc0_pins: dt-emmc0-pins {
+ emmc0-pins-rest {
+ sf,pins = <PAD_GPIO22>;
+ sf,pinmux = <PAD_GPIO22_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO0_RST_N>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ dt_emmc1_pins: dt-emmc1-pins {
+ emmc1-pins0-rest {
+ sf,pins = <PAD_GPIO51>;
+ sf,pinmux = <PAD_GPIO51_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_RST_N>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ emmc1-pins1 {
+ sf,pins = <PAD_GPIO38>;
+ sf,pinmux = <PAD_GPIO38_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CCLK_OUT>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+
+ emmc1-pins2 {
+ sf,pins = <PAD_GPIO36>;
+ sf,pinmux = <PAD_GPIO36_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CCMD_OUT>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CCMD_OUT_EN>;
+ sf,pin-gpio-din = <GPI_SDIO1_CCMD_IN>;
+ };
+
+ emmc1-pins3 {
+ sf,pins = <PAD_GPIO43>;
+ sf,pinmux = <PAD_GPIO43_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_0>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_0>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_0>;
+ };
+
+ emmc1-pins4 {
+ sf,pins = <PAD_GPIO48>;
+ sf,pinmux = <PAD_GPIO48_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_1>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_1>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_1>;
+ };
+
+ emmc1-pins5 {
+ sf,pins = <PAD_GPIO53>;
+ sf,pinmux = <PAD_GPIO53_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_2>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_2>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_2>;
+ };
+
+ emmc1-pins6 {
+ sf,pins = <PAD_GPIO63>;
+ sf,pinmux = <PAD_GPIO63_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_3>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_3>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_3>;
+ };
+
+ emmc1-pins7 {
+ sf,pins = <PAD_GPIO52>;
+ sf,pinmux = <PAD_GPIO52_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_4>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_4>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_4>;
+ };
+
+ emmc1-pins8 {
+ sf,pins = <PAD_GPIO39>;
+ sf,pinmux = <PAD_GPIO39_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_5>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_5>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_5>;
+ };
+
+ emmc1-pins9 {
+ sf,pins = <PAD_GPIO46>;
+ sf,pinmux = <PAD_GPIO46_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_6>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_6>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_6>;
+ };
+
+ emmc1-pins10 {
+ sf,pins = <PAD_GPIO47>;
+ sf,pinmux = <PAD_GPIO47_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_7>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_7>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_7>;
+ };
+ };
+ };
+ };
+
+ //gpioa
+ fragment@1 {
+ target-path = "/soc/gpio@17020000";
+ __overlay__ {
+ dt_pwm_ch6to7_pins: dt-pwm-ch6to7-pins {
+ pwm-ch6-pins {
+ sf,pins = <PAD_RGPIO0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <U0_PWM_8CH_PTC_PWM_6>;
+ sf,pin-gpio-doen = <U0_PWM_8CH_PTC_OE_N_6>;
+ };
+
+ pwm-ch7-pins {
+ sf,pins = <PAD_RGPIO1>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <U0_PWM_8CH_PTC_PWM_7>;
+ sf,pin-gpio-doen = <U0_PWM_8CH_PTC_OE_N_7>;
+ };
+ };
+ };
+ };
+
+ //uart4
+ fragment@2 {
+ target-path = "/soc/serial@12010000";
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ //sdio1
+ fragment@3 {
+ target-path = "/soc/sdio1@16020000";
+ __overlay__ {
+ clock-frequency = <102400000>;
+ max-frequency = <100000000>;
+ card-detect-delay = <300>;
+ bus-width = <8>;
+ cap-mmc-hw-reset;
+ non-removable;
+ cap-mmc-highspeed;
+ post-power-on-delay-ms = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dt_emmc1_pins>;
+ status = "okay";
+ };
+ };
+
+ //ptc
+ fragment@4 {
+ target-path = "/soc/pwm@120d0000";
+ __overlay__ {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dt_pwm_ch6to7_pins>;
+ status = "okay";
+ };
+ };
+};
+
+
--- /dev/null
+/dts-v1/;
+/plugin/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/starfive,jh7110-pinfunc.h>
+/ {
+ compatible = "starfive,jh7110";
+
+ //gpio
+ fragment@0 {
+ target-path = "/soc/gpio@13040000";
+ __overlay__ {
+ dt_pwm_ch0to3_pins: dt-pwm-ch0to3-pins {
+ pwm_ch0-pins {
+ sf,pins = <PAD_GPIO45>;
+ sf,pinmux = <PAD_GPIO45_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_PTC0_PWM_0>;
+ sf,pin-gpio-doen = <OEN_PTC0_PWM_0_OE_N>;
+ };
+
+ pwm_ch1-pins {
+ sf,pins = <PAD_GPIO46>;
+ sf,pinmux = <PAD_GPIO46_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_PTC0_PWM_1>;
+ sf,pin-gpio-doen = <OEN_PTC0_PWM_1_OE_N>;
+ };
+
+ pwm_ch2-pins {
+ sf,pins = <PAD_GPIO47>;
+ sf,pinmux = <PAD_GPIO47_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_PTC0_PWM_2>;
+ sf,pin-gpio-doen = <OEN_PTC0_PWM_2_OE_N>;
+ };
+
+ pwm_ch3-pins {
+ sf,pins = <PAD_GPIO48>;
+ sf,pinmux = <PAD_GPIO48_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_PTC0_PWM_3>;
+ sf,pin-gpio-doen = <OEN_PTC0_PWM_3_OE_N>;
+ };
+ };
+ };
+ };
+
+ //gpioa
+ fragment@1 {
+ target-path = "/soc/gpio@17020000";
+ __overlay__ {
+ dt_pwm_ch4to5_pins: dt-pwm-ch4to5-pins {
+ pwm-ch4-pins {
+ sf,pins = <PAD_RGPIO0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <U0_PWM_8CH_PTC_PWM_4>;
+ sf,pin-gpio-doen = <U0_PWM_8CH_PTC_OE_N_4>;
+ };
+
+ pwm-ch5-pins {
+ sf,pins = <PAD_RGPIO1>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <U0_PWM_8CH_PTC_PWM_5>;
+ sf,pin-gpio-doen = <U0_PWM_8CH_PTC_OE_N_5>;
+ };
+ };
+ };
+ };
+
+ //uart5
+ fragment@2 {
+ target-path = "/soc/serial@12020000";
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ //ptc
+ fragment@3 {
+ target-path = "/soc/pwm@120d0000";
+ __overlay__ {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dt_pwm_ch0to3_pins &dt_pwm_ch4to5_pins>;
+ status = "okay";
+ };
+ };
+
+ //i2c0
+ fragment@4 {
+ target-path = "/soc/i2c@10030000";
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ //i2c1
+ fragment@5 {
+ target-path = "/soc/i2c@10040000";
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ //i2c3
+ fragment@6 {
+ target-path = "/soc/i2c@12030000";
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
+
+
/dts-v1/;
#include "jh7110.dtsi"
-#include "jh7110_pinctrl.dtsi"
+#include "jh7110-evb-pinctrl.dtsi"
/ {
aliases {
status = "okay";
};
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "disabled";
+};
+
&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
- status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ status = "disabled";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;
+ status = "disabled";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_pins>;
+ status = "disabled";
};
&dma {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "disabled";
-
};
&i2c2 {
auto_calc_scl_lhcnt;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
- status = "disabled";
+ status = "okay";
seeed_plane_i2c@45 {
compatible = "seeed_panel";
auto_calc_scl_lhcnt;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
- status = "okay";
-
- tda998x@70 {
- compatible = "nxp,tda998x";
- reg = <0x70>;
-
- port {
- tda998x_0_input: endpoint {
- remote-endpoint = <&hdmi_out>;
- };
- };
- };
+ status = "disabled";
};
&i2c4 {
};
};
};
+
+ tda998x@70 {
+ compatible = "nxp,tda998x";
+ reg = <0x70>;
+
+ port {
+ tda998x_0_input: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+ };
};
&i2c5 {
};
};
};
-/* default sd card */
+
&sdio0 {
- clock-frequency = <102400000>;
- max-frequency = <200000000>;
- card-detect-delay = <300>;
- bus-width = <4>;
- broken-cd;
- cap-sd-highspeed;
- post-power-on-delay-ms = <200>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdcard0_pins>;
- //cd-gpios = <&gpio 23 0>;
- status = "okay";
+ status = "disabled";
};
&sdio1 {
- clock-frequency = <4000000>;
- max-frequency = <1000000>;
- card-detect-delay = <300>;
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- cap-mmc-hw-reset;
- non-removable;
- enable-sdio-wakeup;
- keep-power-in-suspend;
- cap-mmc-highspeed;
- post-power-on-delay-ms = <200>;
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins>;
- status = "okay";
+ status = "disabled";
};
&vin_sysctl {
/* when use dvp open this pinctrl*/
- //pinctrl-names = "default";
- //pinctrl-0 = <&dvp_pins>;
status = "okay";
ports {
};
&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can1_pins>;
status = "disabled";
};
&tdm {
pinctrl-names = "default";
pinctrl-0 = <&tdm0_pins>;
- status = "okay";
+ status = "disabled";
};
&spdif0 {
- status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif0_pins>;
+ status = "disabled";
};
&pwmdac {
pinctrl-names = "default";
pinctrl-0 = <&pwmdac0_pins>;
- status = "okay";
+ status = "disabled";
};
&i2stx {
&pdm {
pinctrl-names = "default";
pinctrl-0 = <&pdm0_pins>;
- status = "okay";
+ status = "disabled";
};
&i2srx_mst {
pinctrl-names = "default";
pinctrl-0 = <&i2srx_clk_pins>;
- status = "okay";
+ status = "disabled";
};
&i2srx_3ch {
pinctrl-names = "default";
pinctrl-0 = <&i2srx_pins>;
- status = "okay";
+ status = "disabled";
};
&i2stx_4ch0 {
&i2stx_4ch1 {
pinctrl-names = "default";
pinctrl-0 = <&i2s_clk_pins &i2stx_pins>;
- status = "okay";
-};
-
-&ptc {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm_ch0_pins>;
- status = "okay";
+ status = "disabled";
};
&spdif_transmitter {
- status = "okay";
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+ status = "disabled";
};
&spdif_receiver {
- status = "okay";
+ compatible = "linux,spdif-dir";
+ #sound-dai-cells = <0>;
+ status = "disabled";
};
&pwmdac_codec {
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&ssp0_pins>;
- status = "okay";
+ status = "disabled";
spi_dev0: spi@0 {
compatible = "rohm,dh2228fv";
pinctrl-0 = <&pcie0_perst_default>;
pinctrl-1 = <&pcie0_perst_active>;
pinctrl-2 = <&pcie0_power_active>;
- status = "okay";
+ status = "disabled";
};
&pcie1 {
pinctrl-0 = <&pcie1_perst_default>;
pinctrl-1 = <&pcie1_perst_active>;
pinctrl-2 = <&pcie1_power_active>;
- status = "okay";
+ status = "disabled";
};
&mailbox_contrl0 {
};
&dc8200 {
- //pinctrl-names = "default";
- //pinctrl-0 = <&rgb_pad_pins>;
status = "okay";
dc_out: port {
&hdmi_output {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&rgb_pad_pins>;
ports {
#address-cells = <1>;
};
};
-&encoder {
+&tda988x_pin {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgb_pad_pins>;
status = "disabled";
+};
+
+&encoder {
+ status = "okay";
ports {
#address-cells = <1>;
};
&mipi_dsi {
- //pinctrl-names = "default";
- //pinctrl-0 = <&mipitx_pins>;
- status = "disabled";
+ status = "okay";
+};
+
+&mipi_dphy {
+ status = "okay";
+};
+
+&mipi_dphy {
+ status = "disabled";
};
&co_process {
pinctrl-names = "default";
pinctrl-0 = <&usb_pins>;
dr_mode = "host"; /*host or peripheral*/
- status = "okay";
+ status = "disabled";
};
&xrp {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-evb.dtsi"
+#include "codecs/sf_pdm.dtsi"
+#include "codecs/sf_pwmdac.dtsi"
+
+/ {
+ model = "StarFive JH7110 EVB";
+ compatible = "starfive,jh7110-evb", "starfive,jh7110";
+};
+
+/* default sd card */
+&sdio0 {
+ clock-frequency = <102400000>;
+ max-frequency = <200000000>;
+ card-detect-delay = <300>;
+ bus-width = <4>;
+ broken-cd;
+ cap-sd-highspeed;
+ post-power-on-delay-ms = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdcard0_pins>;
+ status = "okay";
+};
+
+&usbdrd30 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&pwmdac_codec {
+ status = "okay";
+};
+
+&pwmdac {
+ status = "okay";
+};
+
+&pdm {
+ status = "okay";
+};
+
+&i2srx_mst {
+ status = "okay";
+};
+
+&dmic_codec {
+ status = "okay";
+};
\ No newline at end of file
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-evb.dtsi"
+
+/ {
+ model = "StarFive JH7110 EVB";
+ compatible = "starfive,jh7110-evb", "starfive,jh7110";
+};
+
+&vin_sysctl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dvp_pins>;
+};
+
+&hdmi_output {
+ status = "okay";
+};
+
+&tda988x_pin {
+ status = "okay";
+};
+
+&encoder {
+ status = "disabled";
+};
+
+&mipi_dsi {
+ status = "disabled";
+};
+
+&mipi_dphy {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-evb.dtsi"
+#include "codecs/sf_wm8960.dtsi"
+
+/ {
+ model = "StarFive JH7110 EVB";
+ compatible = "starfive,jh7110-evb", "starfive,jh7110";
+};
+
+/* default sd card */
+&sdio0 {
+ clock-frequency = <102400000>;
+ max-frequency = <200000000>;
+ card-detect-delay = <300>;
+ bus-width = <4>;
+ broken-cd;
+ cap-sd-highspeed;
+ post-power-on-delay-ms = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdcard0_pins>;
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&sdio1 {
+ clock-frequency = <102400000>;
+ max-frequency = <100000000>;
+ card-detect-delay = <300>;
+ bus-width = <4>;
+ broken-cd;
+ cap-sd-highspeed;
+ post-power-on-delay-ms = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdcard1_pins>;
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2srx_3ch {
+ status = "okay";
+};
+
+&i2stx_4ch1 {
+ status = "okay";
+};
gmac0-pins-reset {
sf,pins = <PAD_GPIO13>;
sf,pinmux = <PAD_GPIO13_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_HIGH>;
sf,pin-gpio-doen = <OEN_LOW>;
};
gmac1_pins: gmac1-pins {
gmac1-pins0 {
sf,pins = <PAD_GMAC1_MDC>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_SMT(1)|GPIO_DS(3))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_SMT(1) | GPIO_DS(3))>;
sf,pin-syscon = <PADCFG_PAD_GMAC1_MDC_SYSCON IO_3_3V>;
};
};
uart0_pins: uart0-pins {
uart0-pins-tx {
sf,pins = <PAD_GPIO5>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_DS(3))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
sf,pin-gpio-dout = <GPO_UART0_SOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
uart0-pins-rx {
sf,pins = <PAD_GPIO6>;
sf,pinmux = <PAD_GPIO6_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_PU(1))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_UART0_SIN>;
};
uart1_pins: uart1-pins {
uart1-pins-tx {
- sf,pins = <PAD_GPIO41>;
- sf,pinmux = <PAD_GPIO41_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_DS(3))>;
+ sf,pins = <PAD_GPIO30>;
+ sf,pinmux = <PAD_GPIO30_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
sf,pin-gpio-dout = <GPO_UART1_SOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
uart1-pins-rx {
- sf,pins = <PAD_GPIO42>;
- sf,pinmux = <PAD_GPIO42_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_PU(1))>;
+ sf,pins = <PAD_GPIO31>;
+ sf,pinmux = <PAD_GPIO31_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_UART1_SIN>;
};
uart1-pins-cts {
- sf,pins = <PAD_GPIO43>;
- sf,pinmux = <PAD_GPIO43_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO29>;
+ sf,pinmux = <PAD_GPIO29_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_UART1_CTS_N>;
};
uart1-pins-rts {
- sf,pins = <PAD_GPIO40>;
- sf,pinmux = <PAD_GPIO40_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO27>;
+ sf,pinmux = <PAD_GPIO27_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_UART1_RTS_N>;
sf,pin-gpio-doen = <OEN_LOW>;
uart2_pins: uart2-pins {
uart2-pins-tx {
- sf,pins = <PAD_GPIO41>;
- sf,pinmux = <PAD_GPIO41_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_DS(3))>;
+ sf,pins = <PAD_GPIO30>;
+ sf,pinmux = <PAD_GPIO30_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
sf,pin-gpio-dout = <GPO_UART2_SOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
uart2-pins-rx {
- sf,pins = <PAD_GPIO42>;
- sf,pinmux = <PAD_GPIO42_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_PU(1))>;
+ sf,pins = <PAD_GPIO31>;
+ sf,pinmux = <PAD_GPIO31_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_UART2_SIN>;
};
uart2-pins-cts {
- sf,pins = <PAD_GPIO43>;
- sf,pinmux = <PAD_GPIO43_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO29>;
+ sf,pinmux = <PAD_GPIO29_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_UART2_CTS_N>;
};
uart2-pins-rts {
- sf,pins = <PAD_GPIO40>;
- sf,pinmux = <PAD_GPIO40_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO27>;
+ sf,pinmux = <PAD_GPIO27_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_UART2_RTS_N>;
sf,pin-gpio-doen = <OEN_LOW>;
uart3-pins-tx {
sf,pins = <PAD_GPIO30>;
sf,pinmux = <PAD_GPIO30_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_DS(3))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
sf,pin-gpio-dout = <GPO_UART3_SOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
uart3-pins-rx {
sf,pins = <PAD_GPIO31>;
sf,pinmux = <PAD_GPIO31_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_PU(1))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_UART3_SIN>;
};
uart4_pins: uart4-pins {
uart4-pins-tx {
- sf,pins = <PAD_GPIO41>;
- sf,pinmux = <PAD_GPIO41_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_DS(3))>;
+ sf,pins = <PAD_GPIO30>;
+ sf,pinmux = <PAD_GPIO30_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
sf,pin-gpio-dout = <GPO_UART4_SOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
uart4-pins-rx {
- sf,pins = <PAD_GPIO42>;
- sf,pinmux = <PAD_GPIO42_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_PU(1))>;
+ sf,pins = <PAD_GPIO31>;
+ sf,pinmux = <PAD_GPIO31_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_UART4_SIN>;
};
uart4-pins-cts {
- sf,pins = <PAD_GPIO43>;
- sf,pinmux = <PAD_GPIO43_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO29>;
+ sf,pinmux = <PAD_GPIO29_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_UART4_CTS_N>;
};
uart4-pins-rts {
- sf,pins = <PAD_GPIO40>;
- sf,pinmux = <PAD_GPIO40_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO27>;
+ sf,pinmux = <PAD_GPIO27_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_UART4_RTS_N>;
sf,pin-gpio-doen = <OEN_LOW>;
uart5_pins: uart5-pins {
uart5-pins-tx {
- sf,pins = <PAD_GPIO41>;
- sf,pinmux = <PAD_GPIO41_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_DS(3))>;
+ sf,pins = <PAD_GPIO30>;
+ sf,pinmux = <PAD_GPIO30_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
sf,pin-gpio-dout = <GPO_UART5_SOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
uart5-pins-rx {
- sf,pins = <PAD_GPIO42>;
- sf,pinmux = <PAD_GPIO42_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_PU(1))>;
+ sf,pins = <PAD_GPIO31>;
+ sf,pinmux = <PAD_GPIO31_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_UART5_SIN>;
};
uart5-pins-cts {
- sf,pins = <PAD_GPIO43>;
- sf,pinmux = <PAD_GPIO43_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO29>;
+ sf,pinmux = <PAD_GPIO29_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_UART5_CTS_N>;
};
uart5-pins-rts {
- sf,pins = <PAD_GPIO40>;
- sf,pinmux = <PAD_GPIO40_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO27>;
+ sf,pinmux = <PAD_GPIO27_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_UART5_RTS_N>;
sf,pin-gpio-doen = <OEN_LOW>;
i2c0-pins-scl {
sf,pins = <PAD_GPIO57>;
sf,pinmux = <PAD_GPIO57_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_LOW>;
sf,pin-gpio-doen = <OEN_I2C0_IC_CLK_OE>;
sf,pin-gpio-din = <GPI_I2C0_IC_CLK_IN_A>;
};
-/*
i2c0-pins-sda {
sf,pins = <PAD_GPIO58>;
sf,pinmux = <PAD_GPIO58_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_LOW>;
sf,pin-gpio-doen = <OEN_I2C0_IC_DATA_OE>;
sf,pin-gpio-din = <GPI_I2C0_IC_DATA_IN_A>;
};
-*/
};
i2c1_pins: i2c1-pins {
i2c1-pins-scl {
- sf,pins = <PAD_GPIO7>;
- sf,pinmux = <PAD_GPIO7_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pins = <PAD_GPIO49>;
+ sf,pinmux = <PAD_GPIO49_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_LOW>;
sf,pin-gpio-doen = <OEN_I2C1_IC_CLK_OE>;
sf,pin-gpio-din = <GPI_I2C1_IC_CLK_IN_A>;
};
i2c1-pins-sda {
- sf,pins = <PAD_GPIO8>;
- sf,pinmux = <PAD_GPIO8_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pins = <PAD_GPIO50>;
+ sf,pinmux = <PAD_GPIO50_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_LOW>;
sf,pin-gpio-doen = <OEN_I2C1_IC_DATA_OE>;
sf,pin-gpio-din = <GPI_I2C1_IC_DATA_IN_A>;
i2c2-pins-scl {
sf,pins = <PAD_GPIO11>;
sf,pinmux = <PAD_GPIO11_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_LOW>;
sf,pin-gpio-doen = <OEN_I2C2_IC_CLK_OE>;
sf,pin-gpio-din = <GPI_I2C2_IC_CLK_IN_A>;
i2c2-pins-sda {
sf,pins = <PAD_GPIO9>;
sf,pinmux = <PAD_GPIO9_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_LOW>;
sf,pin-gpio-doen = <OEN_I2C2_IC_DATA_OE>;
sf,pin-gpio-din = <GPI_I2C2_IC_DATA_IN_A>;
i2c3_pins: i2c3-pins {
i2c3-pins-scl {
- sf,pins = <PAD_GPIO27>;
- sf,pinmux = <PAD_GPIO27_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pins = <PAD_GPIO51>;
+ sf,pinmux = <PAD_GPIO51_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_LOW>;
sf,pin-gpio-doen = <OEN_I2C3_IC_CLK_OE>;
sf,pin-gpio-din = <GPI_I2C3_IC_CLK_IN_A>;
};
i2c3-pins-sda {
- sf,pins = <PAD_GPIO26>;
- sf,pinmux = <PAD_GPIO26_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pins = <PAD_GPIO52>;
+ sf,pinmux = <PAD_GPIO52_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_LOW>;
sf,pin-gpio-doen = <OEN_I2C3_IC_DATA_OE>;
sf,pin-gpio-din = <GPI_I2C3_IC_DATA_IN_A>;
i2c4-pins-scl {
sf,pins = <PAD_GPIO18>;
sf,pinmux = <PAD_GPIO18_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_LOW>;
sf,pin-gpio-doen = <OEN_I2C4_IC_CLK_OE>;
sf,pin-gpio-din = <GPI_I2C4_IC_CLK_IN_A>;
i2c4-pins-sda {
sf,pins = <PAD_GPIO12>;
sf,pinmux = <PAD_GPIO12_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_LOW>;
sf,pin-gpio-doen = <OEN_I2C4_IC_DATA_OE>;
sf,pin-gpio-din = <GPI_I2C4_IC_DATA_IN_A>;
i2c5-pins-scl {
sf,pins = <PAD_GPIO19>;
sf,pinmux = <PAD_GPIO19_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_LOW>;
sf,pin-gpio-doen = <OEN_I2C5_IC_CLK_OE>;
sf,pin-gpio-din = <GPI_I2C5_IC_CLK_IN_A>;
i2c5-pins-sda {
sf,pins = <PAD_GPIO20>;
sf,pinmux = <PAD_GPIO20_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_LOW>;
sf,pin-gpio-doen = <OEN_I2C5_IC_DATA_OE>;
sf,pin-gpio-din = <GPI_I2C5_IC_DATA_IN_A>;
i2c6-pins-scl {
sf,pins = <PAD_GPIO16>;
sf,pinmux = <PAD_GPIO16_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_LOW>;
sf,pin-gpio-doen = <OEN_I2C6_IC_CLK_OE>;
sf,pin-gpio-din = <GPI_I2C6_IC_CLK_IN_A>;
i2c6-pins-sda {
sf,pins = <PAD_GPIO17>;
sf,pinmux = <PAD_GPIO17_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_LOW>;
sf,pin-gpio-doen = <OEN_I2C6_IC_DATA_OE>;
sf,pin-gpio-din = <GPI_I2C6_IC_DATA_IN_A>;
mmc0-pins-rest {
sf,pins = <PAD_GPIO22>;
sf,pinmux = <PAD_GPIO22_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_SDIO0_RST_N>;
sf,pin-gpio-doen = <OEN_LOW>;
};
sdcard0-pins-rest {
sf,pins = <PAD_GPIO24>;
sf,pinmux = <PAD_GPIO24_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_SDIO0_RST_N>;
sf,pin-gpio-doen = <OEN_LOW>;
};
};
- mmc1_pins: mmc1-pins {
- mmc1-pins0 {
- sf,pins = <PAD_GPIO10>;
- sf,pinmux = <PAD_GPIO10_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ emmc1_pins: emmc1-pins {
+ emmc1-pins0-rest {
+ sf,pins = <PAD_GPIO51>;
+ sf,pinmux = <PAD_GPIO51_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_RST_N>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ emmc1-pins1 {
+ sf,pins = <PAD_GPIO38>;
+ sf,pinmux = <PAD_GPIO38_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_SDIO1_CCLK_OUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
- mmc1-pins1 {
- sf,pins = <PAD_GPIO9>;
- sf,pinmux = <PAD_GPIO9_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ emmc1-pins2 {
+ sf,pins = <PAD_GPIO36>;
+ sf,pinmux = <PAD_GPIO36_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_SDIO1_CCMD_OUT>;
sf,pin-gpio-doen = <OEN_SDIO1_CCMD_OUT_EN>;
sf,pin-gpio-din = <GPI_SDIO1_CCMD_IN>;
};
- mmc1-pins2 {
- sf,pins = <PAD_GPIO11>;
- sf,pinmux = <PAD_GPIO11_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ emmc1-pins3 {
+ sf,pins = <PAD_GPIO43>;
+ sf,pinmux = <PAD_GPIO43_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_0>;
sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_0>;
sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_0>;
};
- mmc1-pins3 {
- sf,pins = <PAD_GPIO12>;
- sf,pinmux = <PAD_GPIO12_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ emmc1-pins4 {
+ sf,pins = <PAD_GPIO48>;
+ sf,pinmux = <PAD_GPIO48_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_1>;
sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_1>;
sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_1>;
};
- mmc1-pins4 {
- sf,pins = <PAD_GPIO7>;
- sf,pinmux = <PAD_GPIO7_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ emmc1-pins5 {
+ sf,pins = <PAD_GPIO53>;
+ sf,pinmux = <PAD_GPIO53_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_2>;
sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_2>;
sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_2>;
};
- mmc1-pins5 {
- sf,pins = <PAD_GPIO8>;
- sf,pinmux = <PAD_GPIO8_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ emmc1-pins6 {
+ sf,pins = <PAD_GPIO63>;
+ sf,pinmux = <PAD_GPIO63_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_3>;
sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_3>;
sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_3>;
};
+
+ emmc1-pins7 {
+ sf,pins = <PAD_GPIO52>;
+ sf,pinmux = <PAD_GPIO52_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_4>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_4>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_4>;
+ };
+
+ emmc1-pins8 {
+ sf,pins = <PAD_GPIO39>;
+ sf,pinmux = <PAD_GPIO39_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_5>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_5>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_5>;
+ };
+
+ emmc1-pins9 {
+ sf,pins = <PAD_GPIO46>;
+ sf,pinmux = <PAD_GPIO46_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_6>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_6>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_6>;
+ };
+
+ emmc1-pins10 {
+ sf,pins = <PAD_GPIO47>;
+ sf,pinmux = <PAD_GPIO47_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_7>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_7>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_7>;
+ };
+ };
+
+ sdcard1_pins: sdcard1-pins {
+ sdcard1-pins0 {
+ sf,pins = <PAD_GPIO56>;
+ sf,pinmux = <PAD_GPIO56_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CCLK_OUT>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ sdcard1-pins1 {
+ sf,pins = <PAD_GPIO50>;
+ sf,pinmux = <PAD_GPIO50_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CCMD_OUT>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CCMD_OUT_EN>;
+ sf,pin-gpio-din = <GPI_SDIO1_CCMD_IN>;
+ };
+
+ sdcard1-pins2 {
+ sf,pins = <PAD_GPIO49>;
+ sf,pinmux = <PAD_GPIO49_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_0>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_0>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_0>;
+ };
+
+ sdcard1-pins3 {
+ sf,pins = <PAD_GPIO45>;
+ sf,pinmux = <PAD_GPIO45_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_1>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_1>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_1>;
+ };
+
+ sdcard1-pins4 {
+ sf,pins = <PAD_GPIO62>;
+ sf,pinmux = <PAD_GPIO62_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_2>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_2>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_2>;
+ };
+
+ sdcard1-pins5 {
+ sf,pins = <PAD_GPIO40>;
+ sf,pinmux = <PAD_GPIO40_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_3>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_3>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_3>;
+ };
+ };
+
+ spdif0_pins: spdif0-pins {
+ spdif0-pins {
+ sf,pins = <PAD_GPIO57>;
+ sf,pinmux = <PAD_GPIO57_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SPDIF0_SPDIFO>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
};
pwmdac0_pins: pwmdac0-pins {
-/*
pwmdac0-pins-left {
sf,pins = <PAD_GPIO57>;
sf,pinmux = <PAD_GPIO57_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_PWMDAC0_LEFT_OUTPUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
-*/
pwmdac0-pins-right {
sf,pins = <PAD_GPIO42>;
sf,pinmux = <PAD_GPIO42_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_PWMDAC0_RIGHT_OUTPUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
};
i2s_clk_pins: i2s-clk0 {
- i2s-clk0_bclk {
- sf,pins = <PAD_GPIO38>;
- sf,pinmux = <PAD_GPIO38_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1))>;
- sf,pin-gpio-din = <GPI_I2STX0_BCLK_SLV GPI_I2SRX0_BCLK_SLV>;
- sf,pin-gpio-doen = <OEN_HIGH>;
- };
-
- i2s-clk0_lrclk {
- sf,pins = <PAD_GPIO63>;
- sf,pinmux = <PAD_GPIO63_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1))>;
- sf,pin-gpio-din = <GPI_I2STX0_LRCK_SLV GPI_I2SRX0_LRCK_SLV>;
- sf,pin-gpio-doen = <OEN_HIGH>;
- };
+ i2s-clk0_bclk {
+ sf,pins = <PAD_GPIO38>;
+ sf,pinmux = <PAD_GPIO38_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-din = <GPI_I2STX0_BCLK_SLV GPI_I2SRX0_BCLK_SLV>;
+ sf,pin-gpio-doen = <OEN_HIGH>;
+ };
+ i2s-clk0_lrclk {
+ sf,pins = <PAD_GPIO63>;
+ sf,pinmux = <PAD_GPIO63_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-din = <GPI_I2STX0_LRCK_SLV GPI_I2SRX0_LRCK_SLV>;
+ sf,pin-gpio-doen = <OEN_HIGH>;
+ };
};
i2stx_pins: i2stx-pins {
can1_pins: can1-pins {
can1-pins0 {
- sf,pins = <PAD_GPIO28>;
- sf,pinmux = <PAD_GPIO28_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO29>;
+ sf,pinmux = <PAD_GPIO29_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_CAN1_CTRL_TXD>;
sf,pin-gpio-doen = <OEN_LOW>;
};
};
- pwm_ch0_pins: pwm_ch0-pins {
- pwm_ch0-pins0 {
- sf,pins = <PAD_GPIO51>;
- sf,pinmux = <PAD_GPIO51_FUNC_SEL 0>;
+ pwm_ch0to3_pins: pwm-ch0to3-pins {
+ pwm_ch0-pins {
+ sf,pins = <PAD_GPIO45>;
+ sf,pinmux = <PAD_GPIO45_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_PTC0_PWM_0>;
sf,pin-gpio-doen = <OEN_PTC0_PWM_0_OE_N>;
};
+
+ pwm_ch1-pins {
+ sf,pins = <PAD_GPIO46>;
+ sf,pinmux = <PAD_GPIO46_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_PTC0_PWM_1>;
+ sf,pin-gpio-doen = <OEN_PTC0_PWM_1_OE_N>;
+ };
+
+ pwm_ch2-pins {
+ sf,pins = <PAD_GPIO47>;
+ sf,pinmux = <PAD_GPIO47_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_PTC0_PWM_2>;
+ sf,pin-gpio-doen = <OEN_PTC0_PWM_2_OE_N>;
+ };
+
+ pwm_ch3-pins {
+ sf,pins = <PAD_GPIO48>;
+ sf,pinmux = <PAD_GPIO48_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_PTC0_PWM_3>;
+ sf,pin-gpio-doen = <OEN_PTC0_PWM_3_OE_N>;
+ };
};
ssp0_pins: ssp0-pins {
ssp0-pins_tx {
- sf,pins = <PAD_GPIO52>;
- sf,pinmux = <PAD_GPIO52_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO38>;
+ sf,pinmux = <PAD_GPIO38_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI0_SSPTXD>;
sf,pin-gpio-doen = <OEN_LOW>;
};
ssp0-pins_rx {
- sf,pins = <PAD_GPIO53>;
- sf,pinmux = <PAD_GPIO53_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO39>;
+ sf,pinmux = <PAD_GPIO39_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_SPI0_SSPRXD>;
};
ssp0-pins_clk {
- sf,pins = <PAD_GPIO48>;
- sf,pinmux = <PAD_GPIO48_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO36>;
+ sf,pinmux = <PAD_GPIO36_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI0_SSPCLKOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
ssp0-pins_cs {
- sf,pins = <PAD_GPIO49>;
- sf,pinmux = <PAD_GPIO49_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO37>;
+ sf,pinmux = <PAD_GPIO37_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI0_SSPFSSOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
ssp1_pins: ssp1-pins {
ssp1-pins_tx {
- sf,pins = <PAD_GPIO52>;
- sf,pinmux = <PAD_GPIO52_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO42>;
+ sf,pinmux = <PAD_GPIO42_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI1_SSPTXD>;
sf,pin-gpio-doen = <OEN_LOW>;
};
ssp1-pins_rx {
- sf,pins = <PAD_GPIO53>;
- sf,pinmux = <PAD_GPIO53_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO43>;
+ sf,pinmux = <PAD_GPIO43_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_SPI1_SSPRXD>;
};
ssp1-pins_clk {
- sf,pins = <PAD_GPIO48>;
- sf,pinmux = <PAD_GPIO48_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO40>;
+ sf,pinmux = <PAD_GPIO40_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI1_SSPCLKOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
ssp1-pins_cs {
- sf,pins = <PAD_GPIO49>;
- sf,pinmux = <PAD_GPIO49_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO41>;
+ sf,pinmux = <PAD_GPIO41_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI1_SSPFSSOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
ssp2_pins: ssp2-pins {
ssp2-pins_tx {
- sf,pins = <PAD_GPIO52>;
- sf,pinmux = <PAD_GPIO52_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO46>;
+ sf,pinmux = <PAD_GPIO46_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI2_SSPTXD>;
sf,pin-gpio-doen = <OEN_LOW>;
};
ssp2-pins_rx {
- sf,pins = <PAD_GPIO53>;
- sf,pinmux = <PAD_GPIO53_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO47>;
+ sf,pinmux = <PAD_GPIO47_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_SPI2_SSPRXD>;
};
ssp2-pins_clk {
- sf,pins = <PAD_GPIO48>;
- sf,pinmux = <PAD_GPIO48_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO44>;
+ sf,pinmux = <PAD_GPIO44_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI2_SSPCLKOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
ssp2-pins_cs {
- sf,pins = <PAD_GPIO49>;
- sf,pinmux = <PAD_GPIO49_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO45>;
+ sf,pinmux = <PAD_GPIO45_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI2_SSPFSSOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
ssp3_pins: ssp3-pins {
ssp3-pins_tx {
- sf,pins = <PAD_GPIO52>;
- sf,pinmux = <PAD_GPIO52_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO50>;
+ sf,pinmux = <PAD_GPIO50_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI3_SSPTXD>;
sf,pin-gpio-doen = <OEN_LOW>;
};
ssp3-pins_rx {
- sf,pins = <PAD_GPIO53>;
- sf,pinmux = <PAD_GPIO53_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO51>;
+ sf,pinmux = <PAD_GPIO51_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_SPI3_SSPRXD>;
ssp4_pins: ssp4-pins {
ssp4-pins_tx {
- sf,pins = <PAD_GPIO52>;
- sf,pinmux = <PAD_GPIO52_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO54>;
+ sf,pinmux = <PAD_GPIO54_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI4_SSPTXD>;
sf,pin-gpio-doen = <OEN_LOW>;
};
ssp4-pins_rx {
- sf,pins = <PAD_GPIO53>;
- sf,pinmux = <PAD_GPIO53_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO55>;
+ sf,pinmux = <PAD_GPIO55_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_SPI4_SSPRXD>;
};
ssp4-pins_clk {
- sf,pins = <PAD_GPIO48>;
- sf,pinmux = <PAD_GPIO48_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO52>;
+ sf,pinmux = <PAD_GPIO52_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI4_SSPCLKOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
ssp4-pins_cs {
- sf,pins = <PAD_GPIO49>;
- sf,pinmux = <PAD_GPIO49_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO53>;
+ sf,pinmux = <PAD_GPIO53_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI4_SSPFSSOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
ssp5_pins: ssp5-pins {
ssp5-pins_tx {
- sf,pins = <PAD_GPIO52>;
- sf,pinmux = <PAD_GPIO52_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO58>;
+ sf,pinmux = <PAD_GPIO58_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI5_SSPTXD>;
sf,pin-gpio-doen = <OEN_LOW>;
};
ssp5-pins_rx {
- sf,pins = <PAD_GPIO53>;
- sf,pinmux = <PAD_GPIO53_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO59>;
+ sf,pinmux = <PAD_GPIO59_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_SPI5_SSPRXD>;
};
ssp5-pins_clk {
- sf,pins = <PAD_GPIO48>;
- sf,pinmux = <PAD_GPIO48_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO56>;
+ sf,pinmux = <PAD_GPIO56_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI5_SSPCLKOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
ssp5-pins_cs {
- sf,pins = <PAD_GPIO49>;
- sf,pinmux = <PAD_GPIO49_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO57>;
+ sf,pinmux = <PAD_GPIO57_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI5_SSPFSSOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
ssp6_pins: ssp6-pins {
ssp6-pins_tx {
- sf,pins = <PAD_GPIO52>;
- sf,pinmux = <PAD_GPIO52_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO62>;
+ sf,pinmux = <PAD_GPIO62_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI6_SSPTXD>;
sf,pin-gpio-doen = <OEN_LOW>;
};
ssp6-pins_rx {
- sf,pins = <PAD_GPIO53>;
- sf,pinmux = <PAD_GPIO53_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO63>;
+ sf,pinmux = <PAD_GPIO63_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_SPI6_SSPRXD>;
};
ssp6-pins_clk {
- sf,pins = <PAD_GPIO48>;
- sf,pinmux = <PAD_GPIO48_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO60>;
+ sf,pinmux = <PAD_GPIO60_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI6_SSPCLKOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
ssp6-pins_cs {
- sf,pins = <PAD_GPIO49>;
- sf,pinmux = <PAD_GPIO49_FUNC_SEL 0>;
+ sf,pins = <PAD_GPIO61>;
+ sf,pinmux = <PAD_GPIO61_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI6_SSPFSSOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
sf,pinmux = <PAD_GPIO37_FUNC_SEL 1>;
sf,pin-ioconfig = <IO(GPIO_IE(0))>;
};
-/*
+
rgb-2-pins {
sf,pins = <PAD_GPIO38>;
sf,pinmux = <PAD_GPIO38_FUNC_SEL 1>;
sf,pin-ioconfig = <IO(GPIO_IE(0))>;
};
-*/
+
rgb-3-pins {
sf,pins = <PAD_GPIO39>;
sf,pinmux = <PAD_GPIO39_FUNC_SEL 1>;
sf,pinmux = <PAD_GPIO43_FUNC_SEL 1>;
sf,pin-ioconfig = <IO(GPIO_IE(0))>;
};
-/*
+
rgb-8-pins {
sf,pins = <PAD_GPIO44>;
sf,pinmux = <PAD_GPIO44_FUNC_SEL 1>;
sf,pin-ioconfig = <IO(GPIO_IE(0))>;
};
-*/
+
rgb-9-pins {
sf,pins = <PAD_GPIO45>;
sf,pinmux = <PAD_GPIO45_FUNC_SEL 1>;
sf,pinmux = <PAD_GPIO56_FUNC_SEL 1>;
sf,pin-ioconfig = <IO(GPIO_IE(0))>;
};
-/*
+
rgb-21-pins {
sf,pins = <PAD_GPIO57>;
sf,pinmux = <PAD_GPIO57_FUNC_SEL 1>;
sf,pinmux = <PAD_GPIO58_FUNC_SEL 1>;
sf,pin-ioconfig = <IO(GPIO_IE(0))>;
};
-*/
+
rgb-23-pins {
sf,pins = <PAD_GPIO59>;
sf,pinmux = <PAD_GPIO59_FUNC_SEL 1>;
sf,pinmux = <PAD_GPIO62_FUNC_SEL 1>;
sf,pin-ioconfig = <IO(GPIO_IE(0))>;
};
-/*
+
rgb-27-pins {
sf,pins = <PAD_GPIO63>;
sf,pinmux = <PAD_GPIO63_FUNC_SEL 1>;
sf,pin-ioconfig = <IO(GPIO_IE(0))>;
};
-*/
+
};
+
inno_hdmi_pins: inno_hdmi-pins {
inno_hdmi-scl {
sf,pins = <PAD_GPIO7>;
//sf,pinmux = <PAD_GPIO7_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_HDMI0_DDC_SCL_OUT>;
sf,pin-gpio-doen = <OEN_HDMI0_DDC_SCL_OEN>;
sf,pin-gpio-din = <GPI_HDMI0_DDC_SCL_IN>;
inno_hdmi-sda {
sf,pins = <PAD_GPIO8>;
//sf,pinmux = <PAD_GPIO8_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-dout = <GPO_HDMI0_DDC_SDA_OUT>;
sf,pin-gpio-doen = <OEN_HDMI0_DDC_SDA_OEN>;
sf,pin-gpio-din = <GPI_HDMI0_DDC_SDA_IN>;
inno_hdmi-cec-pins {
sf,pins = <PAD_GPIO14>;
//sf,pinmux = <PAD_GPIO14_FUNC_SEL 0>;
- sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
sf,pin-gpio-doen = <OEN_HDMI0_CEC_SDA_OEN>;
sf,pin-gpio-dout = <GPO_HDMI0_CEC_SDA_OUT>;
sf,pin-gpio-din = <GPI_HDMI0_CEC_SDA_IN>;
sf,pinmux = <PAD_GPIO37_FUNC_SEL 1>;
sf,pin-ioconfig = <IO(GPIO_IE(0))>;
};
-/*
+
mipitx-3-pins {
sf,pins = <PAD_GPIO38>;
sf,pinmux = <PAD_GPIO38_FUNC_SEL 1>;
sf,pin-ioconfig = <IO(GPIO_IE(0))>;
};
-*/
+
mipitx-4-pins {
sf,pins = <PAD_GPIO39>;
sf,pinmux = <PAD_GPIO39_FUNC_SEL 1>;
};
};
};
+
+&gpioa {
+ pwm_ch4to5_pins: pwm-ch4to5-pins {
+ pwm-ch4-pins {
+ sf,pins = <PAD_RGPIO0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <U0_PWM_8CH_PTC_PWM_4>;
+ sf,pin-gpio-doen = <U0_PWM_8CH_PTC_OE_N_4>;
+ };
+
+ pwm-ch5-pins {
+ sf,pins = <PAD_RGPIO1>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <U0_PWM_8CH_PTC_PWM_5>;
+ sf,pin-gpio-doen = <U0_PWM_8CH_PTC_OE_N_5>;
+ };
+ };
+
+ pwm_ch6to7_pins: pwm-ch6to7-pins {
+ pwm-ch6-pins {
+ sf,pins = <PAD_RGPIO0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <U0_PWM_8CH_PTC_PWM_6>;
+ sf,pin-gpio-doen = <U0_PWM_8CH_PTC_OE_N_6>;
+ };
+
+ pwm-ch7-pins {
+ sf,pins = <PAD_RGPIO1>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <U0_PWM_8CH_PTC_PWM_7>;
+ sf,pin-gpio-doen = <U0_PWM_8CH_PTC_OE_N_7>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-evb.dtsi"
+
+/ {
+ model = "StarFive JH7110 EVB";
+ compatible = "starfive,jh7110-evb", "starfive,jh7110";
+};
+
+/* default sd card */
+&sdio0 {
+ clock-frequency = <102400000>;
+ max-frequency = <200000000>;
+ card-detect-delay = <300>;
+ bus-width = <4>;
+ broken-cd;
+ cap-sd-highspeed;
+ post-power-on-delay-ms = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdcard0_pins>;
+ status = "okay";
+};
+
+&usbdrd30 {
+ status = "okay";
+};
+
+
+&pcie1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&spi2 {
+ status = "okay";
+};
+
+&spi3 {
+ status = "okay";
+};
+
+&spi4 {
+ status = "okay";
+};
+
+&spi5 {
+ status = "okay";
+};
+
+&spi6 {
+ status = "okay";
+};
+
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-evb.dtsi"
+
+/ {
+ model = "StarFive JH7110 EVB";
+ compatible = "starfive,jh7110-evb", "starfive,jh7110";
+};
+
+/* default sd card */
+&sdio0 {
+ clock-frequency = <102400000>;
+ max-frequency = <200000000>;
+ card-detect-delay = <300>;
+ bus-width = <4>;
+ broken-cd;
+ cap-sd-highspeed;
+ post-power-on-delay-ms = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdcard0_pins>;
+ status = "okay";
+};
+
+&usbdrd30 {
+ status = "okay";
+};
+
+
+&pcie1 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&hdmi_output {
+ status = "okay";
+};
+
+&tda988x_pin {
+ status = "okay";
+};
+
+&encoder {
+ status = "disabled";
+};
+
+&mipi_dsi {
+ status = "disabled";
+};
+
+&mipi_dphy {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-evb.dtsi"
+
+/ {
+ model = "StarFive JH7110 EVB";
+ compatible = "starfive,jh7110-evb", "starfive,jh7110";
+};
+
+&usbdrd30 {
+ status = "okay";
+};
+
+
+&pcie1 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&sdio0 {
+ clock-frequency = <102400000>;
+ max-frequency = <100000000>;
+ card-detect-delay = <300>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ non-removable;
+ cap-mmc-hw-reset;
+ post-power-on-delay-ms = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ status = "okay";
+};
+
+&sdio1 {
+ clock-frequency = <102400000>;
+ max-frequency = <100000000>;
+ card-detect-delay = <300>;
+ bus-width = <8>;
+ cap-mmc-hw-reset;
+ non-removable;
+ cap-mmc-highspeed;
+ post-power-on-delay-ms = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc1_pins>;
+ status = "okay";
+};
+
+&ptc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_ch6to7_pins>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-evb.dtsi"
+#include "codecs/sf_tdm.dtsi"
+
+/ {
+ model = "StarFive JH7110 EVB";
+ compatible = "starfive,jh7110-evb", "starfive,jh7110";
+};
+
+/* default sd card */
+&sdio0 {
+ clock-frequency = <102400000>;
+ max-frequency = <200000000>;
+ card-detect-delay = <300>;
+ bus-width = <4>;
+ broken-cd;
+ cap-sd-highspeed;
+ post-power-on-delay-ms = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdcard0_pins>;
+ status = "okay";
+};
+
+&usbdrd30 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&ptc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_ch0to3_pins &pwm_ch4to5_pins>;
+ status = "okay";
+};
+
+&tdm {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
*/
/dts-v1/;
-#include "jh7110-common.dtsi"
-#include "codecs/sf_wm8960.dtsi"
-//#include "codecs/sf_pwmdac.dtsi"
+#include "jh7110-evb.dtsi"
/ {
model = "StarFive JH7110 EVB";
compatible = "starfive,jh7110-evb", "starfive,jh7110";
};
+/* default sd card */
+&sdio0 {
+ clock-frequency = <102400000>;
+ max-frequency = <200000000>;
+ card-detect-delay = <300>;
+ bus-width = <4>;
+ broken-cd;
+ cap-sd-highspeed;
+ post-power-on-delay-ms = <200>;
+ status = "okay";
+};
+
+&usbdrd30 {
+ status = "okay";
+};
-&i2c5 {
- pmic: stf7110_evb_reg@50 {
- compatible = "stf,jh7110-evb-regulator";
- reg = <0x50>;
- regulators {
- hdmi_1p8: LDO_REG1 {
- regulator-name = "hdmi_1p8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
- mipitx_1p8: LDO_REG2 {
- regulator-name = "mipitx_1p8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
- mipirx_1p8: LDO_REG3 {
- regulator-name = "mipirx_1p8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
- hdmi_0p9: LDO_REG4 {
- regulator-name = "hdmi_0p9";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- };
- mipitx_0p9: LDO_REG5 {
- regulator-name = "mipitx_0p9";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- };
- mipirx_0p9: LDO_REG6 {
- regulator-name = "mipirx_0p9";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- };
- sdio_vdd: LDO_REG7 {
- regulator-name = "sdio_vdd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
- };
- };
+&pcie1 {
+ status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-common.dtsi"
+
+&i2c5 {
+ pmic: stf7110_evb_reg@50 {
+ compatible = "stf,jh7110-evb-regulator";
+ reg = <0x50>;
+
+ regulators {
+ hdmi_1p8: LDO_REG1 {
+ regulator-name = "hdmi_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ mipitx_1p8: LDO_REG2 {
+ regulator-name = "mipitx_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ mipirx_1p8: LDO_REG3 {
+ regulator-name = "mipirx_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ hdmi_0p9: LDO_REG4 {
+ regulator-name = "hdmi_0p9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ };
+ mipitx_0p9: LDO_REG5 {
+ regulator-name = "mipitx_0p9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ };
+ mipirx_0p9: LDO_REG6 {
+ regulator-name = "mipirx_0p9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ };
+ sdio_vdd: LDO_REG7 {
+ regulator-name = "sdio_vdd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};
*/
/dts-v1/;
-#include "jh7110_clk.dtsi"
+#include "jh7110-clk.dtsi"
#include <dt-bindings/reset/starfive-jh7110.h>
#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
#include <dt-bindings/clock/starfive-jh7110-vout.h>
usbdrd30: usbdrd{
compatible = "starfive,jh7110-cdns3";
- clocks = <&clkgen JH7110_USB0_CLK_APP_125>,
+ clocks = <&clkgen JH7110_USB_125M>,
+ <&clkgen JH7110_USB0_CLK_APP_125>,
<&clkgen JH7110_USB0_CLK_LPM>,
<&clkgen JH7110_USB0_CLK_STB>,
<&clkgen JH7110_USB0_CLK_USB_APB>,
<&clkgen JH7110_USB0_CLK_AXI>,
<&clkgen JH7110_USB0_CLK_UTMI_APB>;
- clock-names = "app","lpm","stb","apb","axi","utmi";
+ clock-names = "125m","app","lpm","stb","apb","axi","utmi";
resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
<&rstgen RSTN_U0_CDN_USB_APB>,
<&rstgen RSTN_U0_CDN_USB_AXI>,
"rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
"rst_isp_top_n", "rst_isp_top_axi";
interrupts = <92 87>;
+ starfive,aon-syscon = <&aon_syscon 0x00>;
status = "disabled";
};
reg = <0x0 0x100a0000 0x0 0x1000>;
clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
<&clkgen JH7110_SPDIF_CLK_CORE>,
- <&clkgen JH7110_MCLK>;
- clock-names = "spdif-apb", "spdif-core", "audioclk";
+ <&clkgen JH7110_APB0>,
+ <&clkgen JH7110_AUDIO_ROOT>,
+ <&clkgen JH7110_MCLK_INNER>;
+ clock-names = "spdif-apb", "spdif-core", "apb0",
+ "audroot", "mclk_inner";
resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
reset-names = "rst_apb";
interrupts = <84>;
reg = <0 0x295B0000 0 0x90>;
};
+ tda988x_pin: tda988x_pin {
+ compatible = "starfive,tda998x_rgb_pin";
+ status = "disabled";
+ };
+
hdmi_output: hdmi-output {
compatible = "verisilicon,hdmi-encoder";
- verisilicon,dss-syscon = <&dssctrl>;
- verisilicon,mux-mask = <0x70 0x380>;
- verisilicon,mux-val = <0x40 0x280>;
+ //verisilicon,dss-syscon = <&dssctrl>;
+ //verisilicon,mux-mask = <0x70 0x380>;
+ //verisilicon,mux-val = <0x40 0x280>;
status = "disabled";
};
dc8200: dc8200@29400000 {
compatible = "verisilicon,dc8200";
+ verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
reg = <0x0 0x29400000 0x0 0x100>,
<0x0 0x29400800 0x0 0x2000>,
<0x0 0x17030000 0x0 0x1000>;
<&clkvout JH7110_U0_DC8200_CLK_CORE>,
<&clkvout JH7110_U0_DC8200_CLK_AHB>,
<&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
- <&clkgen JH7110_DOM_VOUT_TOP_LCD_CLK>;
+ <&clkgen JH7110_DOM_VOUT_TOP_LCD_CLK>,
+ <&hdmitx0_pixelclk>,
+ <&clkvout JH7110_DC8200_PIX0>;
clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
"noc_disp","noc_isp","noc_stg","vout_src",
"top_vout_axi","ahb1","top_vout_ahb",
"top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
"axi_clk","core_clk","vout_ahb",
- "vout_top_axi","vout_top_lcd";
+ "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0";
resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
<&rstgen RSTN_U0_DC8200_AXI>,
mipi_panel: panel@0 {
/*compatible = "";*/
- status = "disabled";
+ status = "okay";
};
};
simple-audio-card,name = "Starfive-Multi-Sound-Card";
#address-cells = <1>;
#size-cells = <0>;
-
- simple-audio-card,dai-link@0 {
- reg = <0>;
- status = "okay";
- format = "dsp_a";
- bitclock-master = <&dailink_master>;
- frame-master = <&dailink_master>;
-
- widgets =
- "Microphone", "Mic Jack",
- "Line", "Line In",
- "Line", "Line Out",
- "Speaker", "Speaker",
- "Headphone", "Headphone Jack";
- routing =
- "Headphone Jack", "HP_L",
- "Headphone Jack", "HP_R",
- "Speaker", "SPK_LP",
- "Speaker", "SPK_LN",
- "LINPUT1", "Mic Jack",
- "LINPUT3", "Mic Jack",
- "RINPUT1", "Mic Jack",
- "RINPUT2", "Mic Jack";
- cpu {
- sound-dai = <&tdm>;
- };
-
- dailink_master:codec {
- sound-dai = <&wm8960>;
- clocks = <&wm8960_mclk>;
- clock-names = "mclk";
- };
- };
};
co_process: e24@0 {
resets = <&rstgen RSTN_U0_HIFI4_CORE>,
<&rstgen RSTN_U0_HIFI4_AXI>;
reset-names = "rst_core","rst_axi";
+ starfive,stg-syscon = <&stg_syscon>;
firmware-name = "hifi4_elf";
#address-cells = <1>;
#size-cells = <1>;
CONFIG_IWLDVM=y
CONFIG_IWLMVM=y
# CONFIG_RTL_CARDS is not set
+CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_SERIO_LIBPS2=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_SENSORS_SFCTEMP=y
CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_SYSFS=y
CONFIG_STARFIVE_WATCHDOG=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_STF7110=y
# CONFIG_MEDIA_CEC_SUPPORT is not set
CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_STF_VIN=y
CONFIG_VIN_SENSOR_SC2235=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_SOUND=y
CONFIG_SND=y
+CONFIG_SND_USB_AUDIO=y
CONFIG_SND_SOC=y
CONFIG_SND_DESIGNWARE_I2S=y
CONFIG_SND_DESIGNWARE_I2S_STARFIVE_JH7110=y
CONFIG_SND_SOC_WM8960=y
+CONFIG_SND_STARFIVE_SPDIF=y
+CONFIG_SND_STARFIVE_SPDIF_PCM=y
CONFIG_SND_STARFIVE_PWMDAC=y
+CONFIG_SND_SOC_SPDIF=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
#define JH7110_SHA_HMAC_FLAGS 0x800
u32 hmac :1;
u32 rsvd_2 :1;
+#define JH7110_SHA_KEY_DONE BIT(13)
u32 key_done :1;
u32 key_flag :1;
u32 hmac_done :1;
-
#define JH7110_SHA_BUSY BIT(16)
u32 busy :1;
u32 shadone :1;
switch (sdev->cry_type) {
case JH7110_SHA_TYPE:
sha_csr.v = jh7110_sec_read(sdev, JH7110_SHA_SHACSR);
- if (sha_csr.key_done)
- sdev->done_flags |= JH7110_SHA_KEY_DONE;
if (sha_csr.hmac_done)
sdev->done_flags |= JH7110_SHA_HMAC_DONE;
if (sha_csr.shadone)
sdev->done_flags |= JH7110_SHA_SHA_DONE;
- jh7110_sec_write(sdev, JH7110_SHA_SHACSR, sha_csr.v | BIT(17));
+ jh7110_sec_write(sdev, JH7110_SHA_SHACSR, sha_csr.v | BIT(15) | BIT(17));
break;
case JH7110_AES_TYPE:
aes_csr.v = jh7110_sec_read(sdev, JH7110_AES_CSR);
#define JH7110_HASH_BUFLEN 8192
-static inline int jh7110_hash_wait_done(struct jh7110_sec_ctx *ctx)
+static inline int jh7110_hash_wait_hmac_done(struct jh7110_sec_ctx *ctx)
{
struct jh7110_sec_dev *sdev = ctx->sdev;
int ret = -1;
- if (sdev->done_flags & (JH7110_SHA_KEY_DONE | JH7110_SHA_HMAC_DONE | JH7110_SHA_SHA_DONE))
+ if (sdev->done_flags & JH7110_SHA_HMAC_DONE)
ret = 0;
+
return ret;
}
u32 status;
return readl_relaxed_poll_timeout(sdev->io_base + JH7110_SHA_SHACSR, status,
- !(status & JH7110_SHA_BUSY), 10, 100000);
+ !(status & JH7110_SHA_BUSY), 10, 100000);
+}
+
+static inline int jh7110_hash_wait_key_done(struct jh7110_sec_ctx *ctx)
+{
+ struct jh7110_sec_dev *sdev = ctx->sdev;
+ u32 status;
+
+ return readl_relaxed_poll_timeout(sdev->io_base + JH7110_SHA_SHACSR, status,
+ (status & JH7110_SHA_KEY_DONE), 10, 100000);
}
static unsigned int jh7110_hash_reverse(unsigned int data)
jh7110_sec_write(sdev, JH7110_SHA_SHACSR, rctx->csr.sha_csr.v);
}
-static void jh7110_sha_hmac_key(struct jh7110_sec_ctx *ctx)
+static int jh7110_sha_hmac_key(struct jh7110_sec_ctx *ctx)
{
struct jh7110_sec_request_ctx *rctx = ctx->rctx;
struct jh7110_sec_dev *sdev = ctx->sdev;
int klen = ctx->keylen, loop;
unsigned int *key_tmp;
- sdev->done_flags = 0;
- sdev->cry_type = JH7110_SHA_TYPE;
-
jh7110_sec_write(sdev, JH7110_SHA_SHAWKLEN, ctx->keylen);
+
+ rctx->csr.sha_csr.hmac = !!(ctx->sha_mode & JH7110_SHA_HMAC_FLAGS);
rctx->csr.sha_csr.key_flag = 1;
+
jh7110_sec_write(sdev, JH7110_SHA_SHACSR, rctx->csr.sha_csr.v);
key_tmp = (unsigned int *)ctx->key;
for (loop = 0; loop < klen / sizeof(unsigned int); loop++)
jh7110_sec_write(sdev, JH7110_SHA_SHAWKR, key_tmp[loop]);
- jh7110_hash_wait_done(ctx);
+ if (jh7110_hash_wait_key_done(ctx)) {
+ dev_err(sdev->dev, " jh7110_hash_wait_key_done error\n");
+ return -ETIMEDOUT;
+ }
+ return 0;
}
static void jh7110_hash_write_back(struct jh7110_sec_ctx *ctx)
total_len = rctx->bufcnt;
mlen = total_len / sizeof(u32);// DIV_ROUND_UP(total_len, sizeof(u32));
buffer = (unsigned int *)ctx->buffer;
+
for (loop = 0; loop < mlen; loop++, buffer++)
jh7110_sec_write(sdev, JH7110_SHA_SHAWDR, *buffer);
{
struct jh7110_sec_request_ctx *rctx = ctx->rctx;
struct jh7110_sec_dev *sdev = ctx->sdev;
- int count, *data, mlen;
int ret;
- mlen = jh7110_get_hash_size(ctx) / sizeof(unsigned int);
-
sdev->cry_type = JH7110_SHA_TYPE;
rctx->csr.sha_csr.v = 0;
return -ETIMEDOUT;
}
- if (ctx->sha_mode & JH7110_SHA_HMAC_FLAGS)
- jh7110_sha_hmac_key(ctx);
-
rctx->csr.sha_csr.v = 0;
- rctx->csr.sha_csr.start = 1;
rctx->csr.sha_csr.mode = ctx->sha_mode & JH7110_SHA_MODE_MASK;
-
- if (ctx->sec_init) {
- rctx->csr.sha_csr.firstb = 1;
- ctx->sec_init = 0;
- } else {
- jh7110_sec_write(sdev, JH7110_SHA_SHAWLEN3, 0X00000000);
- jh7110_sec_write(sdev, JH7110_SHA_SHAWLEN2, 0X00000000);
- jh7110_sec_write(sdev, JH7110_SHA_SHAWLEN1,
- jh7110_hash_reverse(ctx->sha_len_total >> 32));
- jh7110_sec_write(sdev, JH7110_SHA_SHAWLEN0,
- jh7110_hash_reverse(ctx->sha_len_total & 0xffffffff));
- jh7110_hash_write_back(ctx);
- }
-
- rctx->csr.sha_csr.hmac = !!(ctx->sha_mode & JH7110_SHA_HMAC_FLAGS);
- if (!ctx->sdev->use_dma)
+ if (ctx->sdev->use_dma)
rctx->csr.sha_csr.ie = 1;
- jh7110_sec_write(sdev, JH7110_SHA_SHACSR, rctx->csr.sha_csr.v);
+ if (ctx->sha_mode & JH7110_SHA_HMAC_FLAGS)
+ ret = jh7110_sha_hmac_key(ctx);
- if (jh7110_hash_wait_busy(ctx)) {
- dev_err(sdev->dev, "jh7110_hash_wait_busy error\n");
- return -ETIMEDOUT;
+ if (ret)
+ return ret;
+
+ if (ctx->sec_init && !rctx->csr.sha_csr.hmac) {
+ rctx->csr.sha_csr.start = 1;
+ rctx->csr.sha_csr.firstb = 1;
+ ctx->sec_init = 0;
+ jh7110_sec_write(sdev, JH7110_SHA_SHACSR, rctx->csr.sha_csr.v);
}
if (ctx->sdev->use_dma) {
if (ret)
return ret;
+ jh7110_hash_start(ctx, flags);
+
if (jh7110_hash_wait_busy(ctx)) {
dev_err(sdev->dev, "jh7110_hash_wait_busy error\n");
return -ETIMEDOUT;
}
- jh7110_hash_start(ctx, flags);
-
- if (ctx->sha_mode & JH7110_SHA_HMAC_FLAGS) {
- rctx->csr.sha_csr.final = 1;
- jh7110_sec_write(sdev, JH7110_SHA_SHACSR, rctx->csr.sha_csr.v);
- }
-
- if (jh7110_hash_wait_busy(ctx))
- dev_dbg(sdev->dev, "this is debug %s %s %d\n", __FILE__, __func__, __LINE__);
-
- if (!flags) {
- data = (unsigned int *)rctx->sha_digest_mid;
- for (count = 0; count < mlen; count++)
- data[count] = jh7110_sec_read(ctx->sdev, JH7110_SHA_SHARDR);
- }
-
+ if (ctx->sha_mode & JH7110_SHA_HMAC_FLAGS)
+ if (jh7110_hash_wait_hmac_done(ctx)) {
+ dev_err(sdev->dev, "jh7110_hash_wait_hmac_done error\n");
+ return -ETIMEDOUT;
+ }
return 0;
}
mlen = jh7110_get_hash_size(ctx) / sizeof(u32);
- if (mlen == 28)
- jh7110_sec_read(ctx->sdev, JH7110_SHA_SHARDR);
-
- if (mlen == 48) {
- for (count = 0; count < 4; count++)
- jh7110_sec_read(ctx->sdev, JH7110_SHA_SHARDR);
- }
data = (u32 *)req->result;
for (count = 0; count < mlen; count++)
data[count] = jh7110_sec_read(ctx->sdev, JH7110_SHA_SHARDR);
{
crypto_unregister_ahashes(algs_sha0_sha512_sm3, ARRAY_SIZE(algs_sha0_sha512_sm3));
}
-
struct mutex aes_lock;
struct mutex rsa_lock;
-#define JH7110_SHA_KEY_DONE BIT(0)
#define JH7110_SHA_HMAC_DONE BIT(1)
#define JH7110_SHA_SHA_DONE BIT(2)
#define JH7110_AES_DONE BIT(3)
obj-$(CONFIG_DRM_I2C_SIL164) += sil164.o
tda998x-y := tda998x_drv.o
-obj-$(CONFIG_DRM_I2C_NXP_TDA998X) += tda998x.o
+obj-$(CONFIG_DRM_I2C_NXP_TDA998X) += tda998x.o tda998x_pin.o
obj-$(CONFIG_DRM_I2C_NXP_TDA9950) += tda9950.o
--- /dev/null
+#include <linux/module.h>\r
+#include <linux/of_platform.h>\r
+#include <linux/iommu.h>\r
+#include <drm/drm_drv.h>\r
+#include <drm/drm_of.h>\r
+\r
+#define DRIVER_NAME "starfive"\r
+#define DRIVER_DESC "StarFive Soc DRM"\r
+#define DRIVER_DATE "20220624"\r
+#define DRIVER_MAJOR 1\r
+#define DRIVER_MINOR 0\r
+#define DRIVER_VERSION "v1.0.0"\r
+\r
+static struct drm_driver starfive_drm_driver = {\r
+ .name = DRIVER_NAME,\r
+ .desc = DRIVER_DESC,\r
+ .date = DRIVER_DATE,\r
+ .major = DRIVER_MAJOR,\r
+ .minor = DRIVER_MINOR,\r
+};\r
+\r
+static int starfive_drm_platform_probe(struct platform_device *pdev)\r
+{\r
+ dev_info(&pdev->dev, "%s, ok\n", __func__);\r
+\r
+ return 0;\r
+}\r
+\r
+static const struct of_device_id tda998x_rgb_dt_ids[] = {\r
+ { .compatible = "starfive,tda998x_rgb_pin", },\r
+ { /* sentinel */ },\r
+};\r
+MODULE_DEVICE_TABLE(of, starfive_drm_dt_ids);\r
+\r
+static struct platform_driver starfive_drm_platform_driver = {\r
+ .probe = starfive_drm_platform_probe,\r
+ .driver = {\r
+ .name = "tda998x_rgb_dt_ids",\r
+ .of_match_table = tda998x_rgb_dt_ids,\r
+ },\r
+};\r
+\r
+module_platform_driver(starfive_drm_platform_driver);\r
+\r
+MODULE_AUTHOR("David Li <david.li@starfivetech.com>");\r
+MODULE_DESCRIPTION("starfive DRM Driver");\r
+MODULE_LICENSE("GPL v2");\r
#include <linux/component.h>
#include<linux/reset.h>
+#include <drm/bridge/dw_hdmi.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_of.h>
struct inno_hdmi_i2c *i2c;
struct i2c_adapter *ddc;
- unsigned int tmds_rate;
+ unsigned long tmds_rate;
struct hdmi_data_info hdmi_data;
struct drm_display_mode previous_mode;
struct regulator *hdmi_1p8;
struct regulator *hdmi_0p9;
+ const struct pre_pll_config *pre_cfg;
+ const struct post_pll_config *post_cfg;
};
enum {
CSC_RGB_0_255_TO_RGB_16_235_8BIT,
};
+static const struct pre_pll_config pre_pll_cfg_table[] = {
+ { 25200000, 25200000, 1, 100, 2, 3, 3, 12, 3, 3, 4, 0, 0},
+ { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
+ { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
+ { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
+ { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B},
+ { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0},
+ { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B},
+ { 59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0},
+ { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B},
+ { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817},
+ { 74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0},
+ {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B},
+ {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817},
+ {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0},
+ {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B},
+ {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817},
+ {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0},
+ {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B},
+ {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0},
+ {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817},
+ {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0},
+ {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B},
+ {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0},
+ { /* sentinel */ }
+};
+
+static const struct post_pll_config post_pll_cfg_table[] = {
+ {25200000, 1, 80, 7, 0,1},
+ {27000000, 1, 40, 3, 0,1},
+ {33750000, 1, 40, 8, 3,1},
+ //{33750000, 1, 80, 8, 2},
+ {74250000, 1, 20, 1, 3,1},
+ //{74250000, 18, 80, 8, 2},
+ {148500000, 1, 20, 1, 3,3},
+ {297000000, 2, 20, 0, 3,3},
+ {594000000, 4, 20, 0, 0,0},//postpll_postdiv_en = 0
+ { /* sentinel */ }
+};
+/*
+static const struct post_pll_config post_pll_cfg_table[] = {
+ {33750000, 1, 40, 8, 1},
+ {33750000, 1, 80, 8, 2},
+ {74250000, 1, 40, 8, 1},
+ {74250000, 18, 80, 8, 2},
+ {148500000, 2, 40, 4, 3},
+ {297000000, 4, 40, 2, 3},
+ {594000000, 8, 40, 1, 3},
+};
+*/
static const char coeff_csc[][24] = {
/*
* YUV2RGB:601 SD mode(Y[16:235], UV[16:240], RGB[0:255]):
static void inno_hdmi_power_up(struct inno_hdmi *hdmi)
{
- int val;
+ u8 val;
val = readl_relaxed(hdmi->regs + (0x1b0) * 0x04);
val |= 0x4;
val &= ~(0x1);
writel_relaxed(val, hdmi->regs + (0x1aa) * 0x04);
- /*wait for pre-PLL and post-PLL lock*/
- //while(!(hdmi_read(word_align(0x1a9)) & 0x1));
- //while(!(hdmi_read(word_align(0x1af)) & 0x1));
while (!(readl_relaxed(hdmi->regs + (0x1a9) * 0x04) & 0x1))
;
while (!(readl_relaxed(hdmi->regs + (0x1af) * 0x04) & 0x1))
writel_relaxed(0x63, hdmi->regs + (0x00) * 0x04);
}
-typedef struct register_value {
- u16 reg;
- u8 value;
-} reg_value_t;
-
-#if 0
-static void inno_hdmi_config_640x480p60(struct inno_hdmi *hdmi)
+static void inno_hdmi_config_pll(struct inno_hdmi *hdmi)
{
+ u8 reg_1ad_value = hdmi->post_cfg->post_div_en ?
+ hdmi->post_cfg->postdiv : 0x0d;
const reg_value_t cfg_pll_data[] = {
- /* config pll: 640x480p, 60hz*/
{0x1a0, 0x01},
- //{0x1aa, 0x0f},
- {0x1a1, 0x01},
- {0x1a2, 0xf0},
- {0x1a3, 0x64},
- {0x1a4, 0x2f},
- //{0x1a4, 0x2a},
- {0x1a5, 0x6c},
- {0x1a6, 0x64},
- {0x1ab, 0x01},
- {0x1ac, 0x50},
- //{0x1ad, 0x07},
- {0x1ad, 0x0d},
+ {0x1aa, 0x0f},
+ {0x1a1, hdmi->pre_cfg->prediv},
+ {0x1a2, 0xf0 | hdmi->pre_cfg->fbdiv>>8},
+ {0x1a3, hdmi->pre_cfg->fbdiv},
+ {0x1a4, ((hdmi->pre_cfg->tmds_div_a << 4) | (hdmi->pre_cfg->tmds_div_b << 2) | (hdmi->pre_cfg->tmds_div_c))},
+ {0x1a5, (hdmi->pre_cfg->pclk_div_b << 5) | hdmi->pre_cfg->pclk_div_a},
+ {0x1a6, (hdmi->pre_cfg->pclk_div_c << 5) | hdmi->pre_cfg->pclk_div_d},
+ {0x1ab, hdmi->post_cfg->prediv},
+ {0x1ac, hdmi->post_cfg->fbdiv & 0xff},
+ {0x1ad, reg_1ad_value},
{0x1aa, 0x0e},
{0x1a0, 0x00},
};
int i;
-
- for (i = 0; i < sizeof(cfg_pll_data) / sizeof(reg_value_t); i++) {
- //hdmi_write(cfg_pll_data[i].value, word_align(cfg_pll_data[i].reg));
+ for (i = 0; i < sizeof(cfg_pll_data) / sizeof(reg_value_t); i++)
+ {
+ /*
+ if(0x1ad == cfg_pll_data[i].reg)
+ {
+ if(0 == hdmi->post_cfg->post_div_en)
+ {
+ writel_relaxed(0x0d, hdmi->regs + (cfg_pll_data[i].reg) * 0x04);
+ continue;
+ }
+ }*/
+ dev_info(hdmi->dev, "%s %d reg[%02x],val[%02x]\n",__func__, __LINE__,cfg_pll_data[i].reg,cfg_pll_data[i].value);
writel_relaxed(cfg_pll_data[i].value, hdmi->regs + (cfg_pll_data[i].reg) * 0x04);
}
return;
}
-#endif
static void inno_hdmi_config_1920x1080p60(struct inno_hdmi *hdmi)
{
static void inno_hdmi_tx_phy_param_config(struct inno_hdmi *hdmi)
{
-
- //640x480p60
- //vic = VIC_640x480p60;
- //inno_hdmi_config_640x480p60(hdmi);
- //640x480p60
- //1920x1080p60
inno_hdmi_config_1920x1080p60(hdmi);
- //1920x1080p60
inno_hdmi_tx_ctrl(hdmi);
return;
{
const reg_value_t pwon_data[] = {
{0x00, 0x61},
- //{0xce, 0x00},//data sync
- //{0xce, 0x01}
};
int i;
for (i = 0; i < sizeof(pwon_data)/sizeof(reg_value_t); i++) {
- //hdmi_write(pwon_data[i].value, word_align(pwon_data[i].reg));
writel_relaxed(pwon_data[i].value, hdmi->regs + (pwon_data[i].reg) * 0x04);
}
return;
void inno_hdmi_tmds_driver_on(struct inno_hdmi *hdmi)
{
writel_relaxed(0x8f, hdmi->regs + (0x1b2) * 0x04);
- printk("HDMI tmds encode driver on\r\n");
}
return 0;
}
+ static const
+ struct pre_pll_config *inno_hdmi_phy_get_pre_pll_cfg(struct inno_hdmi *hdmi,
+ unsigned long rate)
+ {
+ const struct pre_pll_config *cfg = pre_pll_cfg_table;
+ //unsigned long tmdsclock = 148500000;
+ rate = (rate / 1000) * 1000;
+
+ for (; cfg->pixclock != 0; cfg++)
+ if (cfg->pixclock == rate)
+ break;
+
+ if (cfg->pixclock == 0)
+ return ERR_PTR(-EINVAL);
+
+ return cfg;
+ }
+
+#define PRE_PLL_POWER_DOWN BIT(0)
+
+ /* phy tuning values for an undocumented set of registers */
+ static const struct phy_config inno_phy_cfg[] = {
+ { 165000000, {
+ 0x07, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x08, 0x08, 0x08,
+ 0x00, 0xac, 0xcc, 0xcc, 0xcc,
+ },
+ }, {
+ 340000000, {
+ 0x0b, 0x0d, 0x0d, 0x0d, 0x07, 0x15, 0x08, 0x08, 0x08,
+ 0x3f, 0xac, 0xcc, 0xcd, 0xdd,
+ },
+ }, {
+ 594000000, {
+ 0x10, 0x1a, 0x1a, 0x1a, 0x07, 0x15, 0x08, 0x08, 0x08,
+ 0x00, 0xac, 0xcc, 0xcc, 0xcc,
+ },
+ }, { /* sentinel */ },
+ };
+
+ static int inno_hdmi_phy_clk_set_rate(struct inno_hdmi *hdmi,unsigned long rate)
+ {
+ unsigned long tmdsclock;
+ hdmi->post_cfg = post_pll_cfg_table;
+
+ tmdsclock = hdmi->tmds_rate;
+ dev_info(hdmi->dev, "%s rate %lu tmdsclk %lu\n",__func__, rate, tmdsclock);
+
+ hdmi->pre_cfg = inno_hdmi_phy_get_pre_pll_cfg(hdmi, tmdsclock);
+ if (IS_ERR(hdmi->pre_cfg))
+ return PTR_ERR(hdmi->pre_cfg);
+
+ for (; hdmi->post_cfg->tmdsclock != 0; hdmi->post_cfg++)
+ if (tmdsclock <= hdmi->post_cfg->tmdsclock && hdmi->post_cfg->version)
+ break;
+
+ dev_info(hdmi->dev, "%s hdmi->pre_cfg->pixclock = %lu\n",__func__, hdmi->pre_cfg->pixclock);
+ dev_info(hdmi->dev, "%s hdmi->pre_cfg->tmdsclock = %lu\n",__func__, hdmi->pre_cfg->tmdsclock);
+ dev_info(hdmi->dev, "%s hdmi->pre_cfg->prediv = %d\n",__func__, hdmi->pre_cfg->prediv);
+ dev_info(hdmi->dev, "%s hdmi->pre_cfg->fbdiv = %d\n",__func__, hdmi->pre_cfg->fbdiv);
+ dev_info(hdmi->dev, "%s hdmi->pre_cfg->tmds_div_a = %d\n",__func__, hdmi->pre_cfg->tmds_div_a);
+ dev_info(hdmi->dev, "%s hdmi->pre_cfg->tmds_div_b = %d\n",__func__, hdmi->pre_cfg->tmds_div_b);
+ dev_info(hdmi->dev, "%s hdmi->pre_cfg->tmds_div_c = %d\n",__func__, hdmi->pre_cfg->tmds_div_c);
+ dev_info(hdmi->dev, "%s hdmi->pre_cfg->pclk_div_a = %d\n",__func__, hdmi->pre_cfg->pclk_div_a);
+ dev_info(hdmi->dev, "%s hdmi->pre_cfg->pclk_div_b = %d\n",__func__, hdmi->pre_cfg->pclk_div_b);
+ dev_info(hdmi->dev, "%s hdmi->pre_cfg->pclk_div_c = %d\n",__func__, hdmi->pre_cfg->pclk_div_c);
+ dev_info(hdmi->dev, "%s hdmi->pre_cfg->pclk_div_d = %d\n",__func__, hdmi->pre_cfg->pclk_div_d);
+ dev_info(hdmi->dev, "%s hdmi->pre_cfg->vco_div_5_en = %d\n",__func__, hdmi->pre_cfg->vco_div_5_en);
+ dev_info(hdmi->dev, "%s hdmi->pre_cfg->fracdiv = %d\n",__func__, hdmi->pre_cfg->fracdiv);
+
+
+ dev_info(hdmi->dev, "*******************************************************\n");
+
+ dev_info(hdmi->dev, "%s hdmi->post_cfg->tmdsclock = %lu\n",__func__, hdmi->post_cfg->tmdsclock);
+ dev_info(hdmi->dev, "%s hdmi->post_cfg->prediv = %d\n",__func__, hdmi->post_cfg->prediv);
+ dev_info(hdmi->dev, "%s hdmi->post_cfg->fbdiv = %d\n",__func__, hdmi->post_cfg->fbdiv);
+ dev_info(hdmi->dev, "%s hdmi->post_cfg->postdiv = %d\n",__func__, hdmi->post_cfg->postdiv);
+ dev_info(hdmi->dev, "%s hdmi->post_cfg->post_div_en = %d\n",__func__, hdmi->post_cfg->post_div_en);
+ dev_info(hdmi->dev, "%s hdmi->post_cfg->version = %d\n",__func__, hdmi->post_cfg->version);
+
+ inno_hdmi_config_pll(hdmi);
+ //1920x1080p60
+ //inno_hdmi_tx_ctrl(hdmi);
+
+#if 0 //pre pll + post pll configire
+
+ /*pre-pll power down*/
+ hdmi_modb(hdmi, 0x1a0, INNO_PRE_PLL_POWER_DOWN, INNO_PRE_PLL_POWER_DOWN);
+
+ /* Configure pre-pll */
+ hdmi_modb(hdmi, 0x1a0, INNO_PCLK_VCO_DIV_5_MASK, INNO_PCLK_VCO_DIV_5(hdmi->pre_cfg->vco_div_5_en));
+ hdmi_writeb(hdmi, 0x1a1, INNO_PRE_PLL_PRE_DIV(hdmi->pre_cfg->prediv));
+
+ u32 val;
+ val = INNO_SPREAD_SPECTRUM_MOD_DISABLE;
+ if (!hdmi->pre_cfg->fracdiv)
+ val |= INNO_PRE_PLL_FRAC_DIV_DISABLE;
+ hdmi_writeb(hdmi, 0x1a2, INNO_PRE_PLL_FB_DIV_11_8(hdmi->pre_cfg->fbdiv | val));
+
+ hdmi_writeb(hdmi, 0x1a3, INNO_PRE_PLL_FB_DIV_7_0(hdmi->pre_cfg->fbdiv));
+
+ hdmi_writeb(hdmi, 0x1a5, INNO_PRE_PLL_PCLK_DIV_A(hdmi->pre_cfg->pclk_div_a) |
+ INNO_PRE_PLL_PCLK_DIV_B(hdmi->pre_cfg->pclk_div_b));
+
+ hdmi_writeb(hdmi, 0x1a6, INNO_PRE_PLL_PCLK_DIV_C(hdmi->pre_cfg->pclk_div_c) |
+ INNO_PRE_PLL_PCLK_DIV_D(hdmi->pre_cfg->pclk_div_d));
+
+ hdmi_writeb(hdmi, 0x1a4, INNO_PRE_PLL_TMDSCLK_DIV_C(hdmi->pre_cfg->tmds_div_c) |
+ INNO_PRE_PLL_TMDSCLK_DIV_A(hdmi->pre_cfg->tmds_div_a) |
+ INNO_PRE_PLL_TMDSCLK_DIV_B(hdmi->pre_cfg->tmds_div_b));
+
+ hdmi_writeb(hdmi, 0x1d3, INNO_PRE_PLL_FRAC_DIV_7_0(hdmi->pre_cfg->fracdiv));
+ hdmi_writeb(hdmi, 0x1d2, INNO_PRE_PLL_FRAC_DIV_15_8(hdmi->pre_cfg->fracdiv));
+ hdmi_writeb(hdmi, 0x1d1, INNO_PRE_PLL_FRAC_DIV_23_16(hdmi->pre_cfg->fracdiv));
+
+ /*pre-pll power down*/
+ hdmi_modb(hdmi, 0x1a0, INNO_PRE_PLL_POWER_DOWN, 0);
+
+ const struct phy_config *phy_cfg = inno_phy_cfg;
+
+ for (; phy_cfg->tmdsclock != 0; phy_cfg++)
+ if (tmdsclock <= phy_cfg->tmdsclock)
+ break;
+
+ hdmi_modb(hdmi, 0x1aa, INNO_POST_PLL_POWER_DOWN, INNO_POST_PLL_POWER_DOWN);
+
+ hdmi_writeb(hdmi, 0x1ac, INNO_POST_PLL_FB_DIV_7_0(hdmi->post_cfg->fbdiv));
+
+ if (hdmi->post_cfg->postdiv == 1) {
+ hdmi_modb(hdmi, 0x1aa, INNO_POST_PLL_REFCLK_SEL_TMDS, INNO_POST_PLL_REFCLK_SEL_TMDS);
+ hdmi_modb(hdmi, 0x1aa, BIT(4), INNO_POST_PLL_FB_DIV_8(hdmi->post_cfg->fbdiv));
+ hdmi_modb(hdmi, 0x1ab, INNO_POST_PLL_Pre_DIV_MASK, INNO_POST_PLL_PRE_DIV(hdmi->post_cfg->prediv));
+ } else {
+ v = (hdmi->post_cfg->postdiv / 2) - 1;
+ v &= INNO_POST_PLL_POST_DIV_MASK;
+ hdmi_modb(hdmi, 0x1ad, INNO_POST_PLL_POST_DIV_MASK, v);
+ hdmi_modb(hdmi, 0x1aa, BIT(4), INNO_POST_PLL_FB_DIV_8(hdmi->post_cfg->fbdiv));
+ hdmi_modb(hdmi, 0x1ab, INNO_POST_PLL_Pre_DIV_MASK, INNO_POST_PLL_PRE_DIV(hdmi->post_cfg->prediv));
+ hdmi_modb(hdmi, 0x1aa, INNO_POST_PLL_REFCLK_SEL_TMDS, INNO_POST_PLL_REFCLK_SEL_TMDS);
+ hdmi_modb(hdmi, 0x1aa, INNO_POST_PLL_POST_DIV_ENABLE, INNO_POST_PLL_POST_DIV_ENABLE);
+ }
+
+ for (v = 0; v < 14; v++){
+ hdmi_writeb(hdmi, 0x1b5 + v, phy_cfg->regs[v]);
+ }
+
+ if (phy_cfg->tmdsclock > 340000000) {
+ /* Set termination resistor to 100ohm */
+ v = clk_get_rate(hdmi->sys_clk) / 100000;
+
+ hdmi_writeb(hdmi, 0x1c5, INNO_TERM_RESISTOR_CALIB_SPEED_14_8(v)
+ | INNO_BYPASS_TERM_RESISTOR_CALIB);
+
+ hdmi_writeb(hdmi, 0x1c6, INNO_TERM_RESISTOR_CALIB_SPEED_7_0(v));
+ hdmi_writeb(hdmi, 0x1c7, INNO_TERM_RESISTOR_100);
+ hdmi_modb(hdmi, 0x1c5, INNO_BYPASS_TERM_RESISTOR_CALIB, 0);
+ } else {
+ hdmi_writeb(hdmi, 0x1c5, INNO_BYPASS_TERM_RESISTOR_CALIB);
+
+ /* clk termination resistor is 50ohm (parallel resistors) */
+ if (phy_cfg->tmdsclock > 165000000){
+ hdmi_modb(hdmi, 0x1c8,
+ INNO_ESD_DETECT_MASK,
+ INNO_TERM_RESISTOR_200);
+ }
+ /* data termination resistor for D2, D1 and D0 is 150ohm */
+ for (v = 0; v < 3; v++){
+ hdmi_modb(hdmi, 0x1c9 + v,
+ INNO_ESD_DETECT_MASK,
+ INNO_TERM_RESISTOR_200);
+ }
+ }
+
+ hdmi_modb(hdmi, 0x1aa, INNO_POST_PLL_POWER_DOWN, 0);
+
+
+#endif
+ return 0;
+ }
+
static int inno_hdmi_setup(struct inno_hdmi *hdmi,
struct drm_display_mode *mode)
{
+ u8 val;
+ int value;
+ hdmi->hdmi_data.vic = drm_match_cea_mode(mode);
+
+ val = readl_relaxed(hdmi->regs + (0x1b0) * 0x04);
+ val |= 0x4;
+ writel_relaxed(val, hdmi->regs + (0x1b0) * 0x04);
+ writel_relaxed(0xf, hdmi->regs + (0x1cc) * 0x04);
+
+ /*turn on pre-PLL*/
+ val = readl_relaxed(hdmi->regs + (0x1a0) * 0x04);
+ val &= ~(0x1);
+ writel_relaxed(val, hdmi->regs + (0x1a0) * 0x04);
+ /*turn on post-PLL*/
+ val = readl_relaxed(hdmi->regs + (0x1aa) * 0x04);
+ val &= ~(0x1);
+ writel_relaxed(val, hdmi->regs + (0x1aa) * 0x04);
+
+ hdmi->tmds_rate = mode->clock * 1000;
+ inno_hdmi_phy_clk_set_rate(hdmi,hdmi->tmds_rate);
+
+ while (!(readl_relaxed(hdmi->regs + (0x1a9) * 0x04) & 0x1))
+ ;
+ while (!(readl_relaxed(hdmi->regs + (0x1af) * 0x04) & 0x1))
+ ;
+
+ /*turn on LDO*/
+ writel_relaxed(0x7, hdmi->regs + (0x1b4) * 0x04);
+ /*turn on serializer*/
+ writel_relaxed(0x70, hdmi->regs + (0x1be) * 0x04);
+ inno_hdmi_tx_phy_power_down(hdmi);
+ /* Set HDMI Mode */
+ hdmi_writeb(hdmi, 0x100,0x3);
+ //hdmi_writeb(hdmi, 0x8,0x00);
+
+ /* Set detail external video timing polarity and interlace mode */
+ value = v_EXTERANL_VIDEO(0);
+ value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
+ v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0);
+ value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
+ v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0);
+ value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
+ v_INETLACE(1) : v_INETLACE(0);
+ hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value);
+
hdmi->hdmi_data.vic = drm_match_cea_mode(mode);
hdmi->hdmi_data.enc_in_format = HDMI_COLORSPACE_RGB;
else
hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
- /* Mute video and audio output */
- hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
- v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1));
+ /* Mute audio output */
+ hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE ,
+ v_AUDIO_MUTE(1));
- /* Set HDMI Mode */
- hdmi_writeb(hdmi, HDMI_HDCP_CTRL,
- v_HDMI_DVI(hdmi->hdmi_data.sink_is_hdmi));
- inno_hdmi_config_video_timing(hdmi, mode);
+ if(0 == hdmi->hdmi_data.vic)
+ {
+ inno_hdmi_config_video_timing(hdmi, mode);
- inno_hdmi_config_video_csc(hdmi);
+ inno_hdmi_config_video_csc(hdmi);
+ }
if (hdmi->hdmi_data.sink_is_hdmi) {
inno_hdmi_config_video_avi(hdmi, mode);
inno_hdmi_config_video_vsi(hdmi, mode);
}
- /*
- * When IP controller have configured to an accurate video
- * timing, then the TMDS clock source would be switched to
- * DCLK_LCDC, so we need to init the TMDS rate to mode pixel
- * clock rate, and reconfigure the DDC clock.
- */
- hdmi->tmds_rate = mode->clock * 1000;
- inno_hdmi_i2c_init(hdmi);
+ inno_hdmi_tx_phy_power_on(hdmi);
+ inno_hdmi_tmds_driver_on(hdmi);
- /* Unmute video and audio output */
- hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
- v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0));
+ writel_relaxed(0x0, hdmi->regs + (0xce) * 0x04);
+ writel_relaxed(0x1, hdmi->regs + (0xce) * 0x04);
return 0;
}
static void inno_hdmi_encoder_enable(struct drm_encoder *encoder)
{
struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
- inno_hdmi_init(hdmi);
+ //inno_hdmi_init(hdmi);
inno_hdmi_set_pwr_mode(hdmi, NORMAL);
}
{
struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
+ hdmi_modb(hdmi, 0x1b2, 0xf, 0);
+ hdmi_modb(hdmi, 0x1be, 0xf, 0);
+ hdmi_modb(hdmi, 0x1b4, 0xf, 0);
+ hdmi_modb(hdmi, 0x1a0, 1, 1);
+ hdmi_modb(hdmi, 0x1aa, 1, 1);
+ hdmi_modb(hdmi, 0x1cc, 0x0f, 0);
+ hdmi_modb(hdmi, 0x1b0, 1<<2, 0);
+
inno_hdmi_set_pwr_mode(hdmi, LOWER_PWR);
}
return ret;
}
+static const struct dw_hdmi_mpll_config starfive_mpll_cfg[] = {
+ {
+ 25200000, {
+ { 0x00b3, 0x0000},
+ { 0x2153, 0x0000},
+ { 0x40f3, 0x0000}
+ },
+ }, {
+ 27000000, {
+ { 0x00b3, 0x0000},
+ { 0x2153, 0x0000},
+ { 0x40f3, 0x0000}
+ },
+ }, {
+ 36000000, {
+ { 0x00b3, 0x0000},
+ { 0x2153, 0x0000},
+ { 0x40f3, 0x0000}
+ },
+ }, {
+ 40000000, {
+ { 0x00b3, 0x0000},
+ { 0x2153, 0x0000},
+ { 0x40f3, 0x0000}
+ },
+ }, {
+ 54000000, {
+ { 0x0072, 0x0001},
+ { 0x2142, 0x0001},
+ { 0x40a2, 0x0001},
+ },
+ }, {
+ 65000000, {
+ { 0x0072, 0x0001},
+ { 0x2142, 0x0001},
+ { 0x40a2, 0x0001},
+ },
+ }, {
+ 66000000, {
+ { 0x013e, 0x0003},
+ { 0x217e, 0x0002},
+ { 0x4061, 0x0002}
+ },
+ }, {
+ 74250000, {
+ { 0x0072, 0x0001},
+ { 0x2145, 0x0002},
+ { 0x4061, 0x0002}
+ },
+ }, {
+ 83500000, {
+ { 0x0072, 0x0001},
+ },
+ }, {
+ 108000000, {
+ { 0x0051, 0x0002},
+ { 0x2145, 0x0002},
+ { 0x4061, 0x0002}
+ },
+ }, {
+ 106500000, {
+ { 0x0051, 0x0002},
+ { 0x2145, 0x0002},
+ { 0x4061, 0x0002}
+ },
+ }, {
+ 146250000, {
+ { 0x0051, 0x0002},
+ { 0x2145, 0x0002},
+ { 0x4061, 0x0002}
+ },
+ }, {
+ 148500000, {
+ { 0x0051, 0x0003},
+ { 0x214c, 0x0003},
+ { 0x4064, 0x0003}
+ },
+ }, {
+ ~0UL, {
+ { 0x00a0, 0x000a },
+ { 0x2001, 0x000f },
+ { 0x4002, 0x000f },
+ },
+ }
+};
+
static enum drm_mode_status
inno_hdmi_connector_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
- return MODE_OK;
+#if 0
+ const struct dw_hdmi_mpll_config *mpll_cfg = starfive_mpll_cfg;
+ int pclk = mode->clock * 1000;
+ bool valid = false;
+ int i;
+
+ for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
+ if (pclk == mpll_cfg[i].mpixelclock) {
+ valid = true;
+ break;
+ }
+ }
+
+ return (valid) ? MODE_OK : MODE_BAD;
+#endif
+ u32 vic = drm_match_cea_mode(mode);
+
+ if (vic >= 1)
+ return MODE_OK;
+ else
+ return MODE_BAD;
+
+ //return MODE_OK;
}
static int
hdmi->i2c = i2c;
- DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
+ DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver success\n", adap->name);
return adap;
}
}
udelay(100);
-//20220531 clk rst interface support
-#if 1
ret = inno_hdmi_get_clk_rst(dev, hdmi);
- //if (ret) {
- // dev_err(dev, "failed to get clock or reset\n");
- // return ret;
- //}
ret = inno_hdmi_en_clk_deas_rst(dev, hdmi);
- //if (ret) {
- // dev_err(dev, "failed to enable clock or deassert reset\n");
- // return ret;
- //}
-#endif
-//20220531 clk rst interface support
-
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
ret = irq;
goto err_disable_clk;
}
- //inno_hdmi_set_pinmux();//20220601 disable for testing dts pinctrl setting
#ifdef CONFIG_DRM_I2C_NXP_TDA998X
inno_hdmi_init(hdmi);
#endif
- //inno_hdmi_get_edid(hdmi,51200000, data);//20220525
inno_hdmi_reset(hdmi);
hdmi->ddc = inno_hdmi_i2c_adapter(hdmi);
clk_disable_unprepare(hdmi->mclk);
clk_disable_unprepare(hdmi->bclk);
- //pmic turn off
- #if 1
regulator_disable(hdmi->hdmi_1p8);
udelay(100);
regulator_disable(hdmi->hdmi_0p9);
- #endif
- //pmic turn off
-
-// clk_disable_unprepare(hdmi->pclk);
}
static const struct component_ops inno_hdmi_ops = {
} vic_code_t;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
+
+ /* REG: 0x1a0 */
+#define INNO_PCLK_VCO_DIV_5_MASK BIT(1)
+#define INNO_PCLK_VCO_DIV_5(x) UPDATE(x, 1, 1)
+#define INNO_PRE_PLL_POWER_DOWN BIT(0)
+
+ /* REG: 0x1a1 */
+#define INNO_PRE_PLL_PRE_DIV_MASK GENMASK(5, 0)
+#define INNO_PRE_PLL_PRE_DIV(x) UPDATE(x, 5, 0)
+
+
+ /* REG: 0xa2 */
+ /* unset means center spread */
+#define INNO_SPREAD_SPECTRUM_MOD_DOWN BIT(7)
+#define INNO_SPREAD_SPECTRUM_MOD_DISABLE BIT(6)
+#define INNO_PRE_PLL_FRAC_DIV_DISABLE UPDATE(3, 5, 4)
+#define INNO_PRE_PLL_FB_DIV_11_8_MASK GENMASK(3, 0)
+#define INNO_PRE_PLL_FB_DIV_11_8(x) UPDATE((x) >> 8, 3, 0)
+
+ /* REG: 0xa3 */
+#define INNO_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
+
+ /* REG: 0xa4*/
+#define INNO_PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(1, 0)
+#define INNO_PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 1, 0)
+#define INNO_PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(3, 2)
+#define INNO_PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 3, 2)
+#define INNO_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(5, 4)
+#define INNO_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 5, 4)
+ /* REG: 0xa5 */
+#define INNO_PRE_PLL_PCLK_DIV_B_SHIFT 5
+#define INNO_PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5)
+#define INNO_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)
+#define INNO_PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0)
+#define INNO_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0)
+
+ /* REG: 0xa6 */
+#define INNO_PRE_PLL_PCLK_DIV_C_SHIFT 5
+#define INNO_PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5)
+#define INNO_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5)
+#define INNO_PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0)
+#define INNO_PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0)
+
+ /* REG: 0xd1 */
+#define INNO_PRE_PLL_FRAC_DIV_23_16(x) UPDATE((x) >> 16, 7, 0)
+ /* REG: 0xd2 */
+#define INNO_PRE_PLL_FRAC_DIV_15_8(x) UPDATE((x) >> 8, 7, 0)
+ /* REG: 0xd3 */
+#define INNO_PRE_PLL_FRAC_DIV_7_0(x) UPDATE(x, 7, 0)
+
+ /* REG: 0x1aa */
+#define INNO_POST_PLL_POST_DIV_ENABLE GENMASK(3, 2)
+#define INNO_POST_PLL_REFCLK_SEL_TMDS BIT(1)
+#define INNO_POST_PLL_POWER_DOWN BIT(0)
+#define INNO_POST_PLL_FB_DIV_8(x) UPDATE(((x) >> 8) <<4 , 4, 4)
+
+ /* REG:0x1ab */
+#define INNO_POST_PLL_Pre_DIV_MASK GENMASK(5, 0)
+#define INNO_POST_PLL_PRE_DIV(x) UPDATE(x, 5, 0)
+ /* REG: 0x1ac */
+#define INNO_POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
+ /* REG: 0x1ad */
+#define INNO_POST_PLL_POST_DIV_MASK GENMASK(2, 0)
+#define INNO_POST_PLL_POST_DIV_2 0x0
+#define INNO_POST_PLL_POST_DIV_4 0x1
+#define INNO_POST_PLL_POST_DIV_8 0x3
+ /* REG: 0x1af */
+#define INNO_POST_PLL_LOCK_STATUS BIT(0)
+ /* REG: 0x1b0 */
+#define INNO_BANDGAP_ENABLE BIT(2)
+ /* REG: 0x1b2 */
+#define INNO_TMDS_CLK_DRIVER_EN BIT(3)
+#define INNO_TMDS_D2_DRIVER_EN BIT(2)
+#define INNO_TMDS_D1_DRIVER_EN BIT(1)
+#define INNO_TMDS_D0_DRIVER_EN BIT(0)
+#define INNO_TMDS_DRIVER_ENABLE (INNO_TMDS_CLK_DRIVER_EN | \
+ INNO_TMDS_D2_DRIVER_EN | \
+ INNO_TMDS_D1_DRIVER_EN | \
+ INNO_TMDS_D0_DRIVER_EN)
+ /* REG:0x1c5 */
+#define INNO_BYPASS_TERM_RESISTOR_CALIB BIT(7)
+#define INNO_TERM_RESISTOR_CALIB_SPEED_14_8(x) UPDATE((x) >> 8, 6, 0)
+ /* REG:0x1c6 */
+#define INNO_TERM_RESISTOR_CALIB_SPEED_7_0(x) UPDATE(x, 7, 0)
+ /* REG:0x1c7 */
+#define INNO_TERM_RESISTOR_100 UPDATE(0, 2, 1)
+#define INNO_TERM_RESISTOR_125 UPDATE(1, 2, 1)
+#define INNO_TERM_RESISTOR_150 UPDATE(2, 2, 1)
+#define INNO_TERM_RESISTOR_200 UPDATE(3, 2, 1)
+ /* REG 0x1c8 - 0x1cb */
+#define INNO_ESD_DETECT_MASK GENMASK(5, 0)
+#define INNO_ESD_DETECT_340MV (0x0 << 6)
+#define INNO_ESD_DETECT_280MV (0x1 << 6)
+#define INNO_ESD_DETECT_260MV (0x2 << 6)
+#define INNO_ESD_DETECT_240MV (0x3 << 6)
+ /* resistors can be used in parallel */
+#define INNO_TMDS_TERM_RESIST_MASK GENMASK(5, 0)
+#define INNO_TMDS_TERM_RESIST_125 BIT(5)
+#define INNO_TMDS_TERM_RESIST_250 BIT(4)
+#define INNO_TMDS_TERM_RESIST_500 BIT(3)
+#define INNO_TMDS_TERM_RESIST_1000 BIT(2)
+#define INNO_TMDS_TERM_RESIST_2000 BIT(1)
+#define INNO_TMDS_TERM_RESIST_4000 BIT(0)
+
+struct pre_pll_config {
+ unsigned long pixclock;
+ unsigned long tmdsclock;
+ u8 prediv;
+ u16 fbdiv;
+ u8 tmds_div_a;
+ u8 tmds_div_b;
+ u8 tmds_div_c;
+ u8 pclk_div_a;
+ u8 pclk_div_b;
+ u8 pclk_div_c;
+ u8 pclk_div_d;
+ u8 vco_div_5_en;
+ u32 fracdiv;
+};
+
+struct post_pll_config {
+ unsigned long tmdsclock;
+ u8 prediv;
+ u16 fbdiv;
+ u8 postdiv;
+ u8 post_div_en;
+ u8 version;
+};
+
+struct phy_config {
+ unsigned long tmdsclock;
+ u8 regs[14];
+};
+
+typedef struct register_value {
+ u16 reg;
+ u8 value;
+} reg_value_t;
+
#endif /* __INNO_HDMI_H__ */
#include <drm/drm_vblank.h>
#endif
+//syscon panel
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+//syscon panel
+
static inline void update_format(u32 format, u64 mod, struct dc_hw_fb *fb)
{
u8 f = FORMAT_A8R8G8B8;
}
return ret;
}
-//noc bus clk get
-
-//noc bus clk enable
static int vs_dc_clock_enable(struct device *dev, struct vs_dc *dc)
{
int ret;
static int vs_dc_dc8200_get_clock(struct device *dev, struct vs_dc *dc)
{
int ret;
- dc->dc8200_pix0 = devm_clk_get(dev, "pix_clk");
- if (IS_ERR(dc->dc8200_pix0)) {
- dev_err(dev, "---dc8200_pix0 get error\n");
- return PTR_ERR(dc->dc8200_pix0);
+ dc->dc8200_clk_pix0 = devm_clk_get(dev, "pix_clk");
+ if (IS_ERR(dc->dc8200_clk_pix0)) {
+ dev_err(dev, "---dc8200_clk_pix0 get error\n");
+ return PTR_ERR(dc->dc8200_clk_pix0);
}
- dc->dc8200_pix1 = devm_clk_get(dev, "vout_pix1");
- if (IS_ERR(dc->dc8200_pix1)) {
- dev_err(dev, "---dc8200_pix1 get error\n");
- return PTR_ERR(dc->dc8200_pix1);
+ dc->dc8200_clk_pix1 = devm_clk_get(dev, "vout_pix1");
+ if (IS_ERR(dc->dc8200_clk_pix1)) {
+ dev_err(dev, "---dc8200_clk_pix1 get error\n");
+ return PTR_ERR(dc->dc8200_clk_pix1);
}
dc->dc8200_axi = devm_clk_get(dev, "axi_clk");
{
int ret;
/*clk_prepare_enable(dc->sys_clk);*/
- ret = clk_prepare_enable(dc->dc8200_pix0);
+ ret = clk_prepare_enable(dc->dc8200_clk_pix0);
if (ret) {
- dev_err(dev, "failed to prepare/enable dc8200_pix0\n");
+ dev_err(dev, "failed to prepare/enable dc8200_clk_pix0\n");
return ret;
}
- ret = clk_prepare_enable(dc->dc8200_pix1);
+ ret = clk_prepare_enable(dc->dc8200_clk_pix1);
if (ret) {
- dev_err(dev, "failed to prepare/enable dc8200_pix1\n");
+ dev_err(dev, "failed to prepare/enable dc8200_clk_pix1\n");
return ret;
}
ret = clk_prepare_enable(dc->dc8200_axi);
static void vs_dc_dc8200_clock_disable(struct vs_dc *dc)
{
- clk_disable_unprepare(dc->dc8200_pix0);
- clk_disable_unprepare(dc->dc8200_pix1);
+ clk_disable_unprepare(dc->dc8200_clk_pix0);
+ clk_disable_unprepare(dc->dc8200_clk_pix1);
clk_disable_unprepare(dc->dc8200_axi);
clk_disable_unprepare(dc->dc8200_core);
clk_disable_unprepare(dc->dc8200_ahb);
static int dc_vout_clk_rst_init(struct device *dev, struct vs_dc *dc)
{
int ret;
- #if 1 //noc bus
ret = vs_dc_get_clock(dev, dc);
if (ret) {
dev_err(dev, "failed to get clock\n");
dev_err(dev, "failed to deassert reset\n");
return ret;
}
- #endif
- #if 1 //vout top
ret = vs_dc_vouttop_get_clock(dev, dc);
if (ret) {
dev_err(dev, "failed to get clock\n");
dev_err(dev, "failed to deassert reset\n");
return ret;
}
- #endif
- #if 1 //dc8200
ret = vs_dc_dc8200_get_clock(dev, dc);
if (ret) {
dev_err(dev, "failed to get clock\n");
dev_err(dev, "failed to deassert reset\n");
return ret;
}
- #endif
return ret;
}
-int sys_vout_mux_config(void)
+
+static int syscon_panel_parse_dt(struct device *dev)
{
- #ifdef CONFIG_DRM_I2C_NXP_TDA998X//tda998x-rgb2hdmi
- SET_U0_LCD_DATA_MAPPING_DPI_DP_SEL(0);//DC8200_INTERFACE_DPI
- SET_U0_LCD_DATA_MAPPING_DP_RGB_FMT(0);//0-RGB888
- SET_U0_DISPLAY_PANEL_MUX_PANEL_SEL(0);//panel 0
- #else
- if(1){
- SET_U0_HDMI_DATA_MAPPING_DPI_DP_SEL(0);
- SET_U0_HDMI_DATA_MAPPING_DPI_BIT_DEPTH(0);
- SET_U0_HDMI_DATA_MAPPING_DP_BIT_DEPTH(0);
- SET_U0_HDMI_DATA_MAPPING_DP_YUV_MODE(0);
- SET_U2_DISPLAY_PANEL_MUX_PANEL_SEL(0);
-
- }
- #endif
- return 0;
+ struct vs_dc *dc = dev_get_drvdata(dev);
+ int ret = 0;
+
+ dc->dss_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "verisilicon,dss-syscon");
+
+ if (IS_ERR(dc->dss_regmap)) {
+ if (PTR_ERR(dc->dss_regmap) != -ENODEV) {
+ dev_err(dev, "failed to get dss-syscon\n");
+ ret = PTR_ERR(dc->dss_regmap);
+ goto err;
+ }
+ dc->dss_regmap = NULL;
+ goto err;
+ }
+
+err:
+ return ret;
}
-int sys_dispctrl_clk(void)
+int sys_dispctrl_clk_standard(struct vs_dc *dc, struct device *dev)
{
- #ifdef CONFIG_DRM_I2C_NXP_TDA998X//tda998x-rgb2hdmi
- _SWITCH_CLOCK_CLK_U0_DC8200_CLK_PIX1_SOURCE_CLK_HDMITX0_PIXELCLK_;
- _SWITCH_CLOCK_CLK_U0_DC8200_CLK_PIX0_SOURCE_CLK_HDMITX0_PIXELCLK_;
- //_ENABLE_CLOCK_CLK_DOM_VOUT_TOP_LCD_CLK_;//disabled standard
- #else
- _SWITCH_CLOCK_CLK_U0_DC8200_CLK_PIX0_SOURCE_CLK_HDMITX0_PIXELCLK_;
- //_SWITCH_CLOCK_CLK_U0_DC8200_CLK_PIX0_SOURCE_CLK_DC8200_PIX0_;
- #endif
+#ifdef CONFIG_DRM_I2C_NXP_TDA998X
+ dc->dc8200_clk_pix1 = devm_clk_get(dev, "vout_pix1");
+ if (IS_ERR(dc->dc8200_clk_pix1)) {
+ dev_err(dev, "---dc8200_clk_pix1 get error\n");
+ return PTR_ERR(dc->dc8200_clk_pix1);
+ }
+
+ dc->hdmitx0_pixelclk = devm_clk_get(dev, "hdmitx0_pixelclk");
+ if (IS_ERR(dc->hdmitx0_pixelclk)) {
+ dev_err(dev, "---hdmitx0_pixelclk get error\n");
+ return PTR_ERR(dc->hdmitx0_pixelclk);
+ }
+
+ dc->dc8200_clk_pix0 = devm_clk_get(dev, "pix_clk");
+ if (IS_ERR(dc->dc8200_clk_pix0)) {
+ dev_err(dev, "---dc8200_clk_pix0 get error\n");
+ return PTR_ERR(dc->dc8200_clk_pix0);
+ }
+
+ clk_set_parent( dc->dc8200_clk_pix1, dc->hdmitx0_pixelclk );
+ clk_set_parent( dc->dc8200_clk_pix0, dc->hdmitx0_pixelclk );
+
+#else
+ //_SWITCH_CLOCK_CLK_U0_DC8200_CLK_PIX0_SOURCE_CLK_HDMITX0_PIXELCLK_;
+ dc->dc8200_clk_pix0 = devm_clk_get(dev, "pix_clk"); //dc8200_clk_pix0
+ if (IS_ERR(dc->dc8200_clk_pix0)) {
+ dev_err(dev, "---dc8200_clk_pix0 get error\n");
+ return PTR_ERR(dc->dc8200_clk_pix0);
+ }
+
+ dc->hdmitx0_pixelclk = devm_clk_get(dev, "hdmitx0_pixelclk");//hdmitx0_pixelclk
+ if (IS_ERR(dc->hdmitx0_pixelclk)) {
+ dev_err(dev, "---hdmitx0_pixelclk get error\n");
+ return PTR_ERR(dc->hdmitx0_pixelclk);
+ }
+ clk_set_parent( dc->dc8200_clk_pix0, dc->hdmitx0_pixelclk );//parent,child
+
+#endif
return 0;
}
int ret;
dev_info(dev, "====> %s, %d.\n", __func__, __LINE__);
- /*---------------------mux config------------*/
- SET_U0_DSITX_DATA_MAPPING_DPI_DP_SEL(0);
- //SET_U0_DSITX_DATA_MAPPING_DP_MODE(vout_sys->vout_dsitx.dp_color_mode);
- SET_U1_DISPLAY_PANEL_MUX_PANEL_SEL(0);
- //_ENABLE_CLOCK_CLK_DOM_VOUT_TOP_LCD_CLK_;
+
ret = clk_prepare_enable(dc->vout_top_lcd);
if (ret) {
dev_err(dev, "failed to prepare/enable vout_top_lcd\n");
return 0;
}
-int sys_dispctrl_init(void)
-{
- sys_vout_mux_config();
- sys_dispctrl_clk();
-
- mdelay(1);
- return 0;
-}
-
static void dc_deinit(struct device *dev)
{
struct vs_dc *dc = dev_get_drvdata(dev);
dc->first_frame = true;
- //power_set(dev, 1);
+ ret = syscon_panel_parse_dt(dev);
+ if (ret){
+ dev_err(dev,"syscon_panel_parse_dt failed\n");
+ return ret;
+ }
starfive_power_domain_set(POWER_DOMAIN_VOUT, 1);
//ret = plda_clk_rst_init(dev);
ret = dc_vout_clk_rst_init(dev, dc);
- ret = sys_dispctrl_init();
- if (ret < 0) {
- dev_err(dev, "failed to init vout clk reset: %d\n", ret);
- return ret;
- }
+ #ifdef CONFIG_DRM_I2C_NXP_TDA998X//tda998x-rgb2hdmi
+ regmap_update_bits(dc->dss_regmap, 0x4, BIT(20), 1<<20);
+ #endif
+
+ ret = sys_dispctrl_clk_standard(dc, dev);
+
#ifdef CONFIG_STARFIVE_DSI
dev_info(dev, "dc mipi channel\n");
+ regmap_update_bits(dc->dss_regmap, 0x8, BIT(3), 1<<3);
dc->vout_src = devm_clk_get(dev, "vout_src");
if (IS_ERR(dc->vout_src)){
dev_err(dev,"failed to get dc->vout_src\n");
dev_err(dev,"failed to get dc->vout_top_lcd\n");
return PTR_ERR(dc->vout_top_lcd);
}
+ #if 1 //parent for dc8200_clk_pix0 !!
+ dc->dc8200_pix0 = devm_clk_get(dev, "dc8200_pix0"); //dc8200_pix0
+ if (IS_ERR(dc->dc8200_pix0)) {
+ dev_err(dev, "---dc8200_pix0 get error\n");
+ return PTR_ERR(dc->dc8200_pix0);
+ }
+ #endif
+ //_SWITCH_CLOCK_CLK_U0_DC8200_CLK_PIX0_SOURCE_CLK_DC8200_PIX0_;
+ clk_set_parent( dc->dc8200_clk_pix0, dc->dc8200_pix0 );//child,parent
ret = drv_config_dc_4_dsi(dc,dev);
if (ret < 0) {
dev_err(dev, "failed to drv_config_dc_4_dsi: %d\n", ret);
#ifdef CONFIG_DRM_I2C_NXP_TDA998X
_ENABLE_CLOCK_CLK_DOM_VOUT_TOP_LCD_CLK_;
- /*
+ #if 0 //to do fix
dev_info(dev, "dc rgb2hdmi channel\n");
dc->vout_top_lcd = devm_clk_get(dev, "vout_top_lcd");
if (IS_ERR(dc->vout_top_lcd)){
dev_err(dev,"failed to get dc->vout_top_lcd\n");
return PTR_ERR(dc->vout_top_lcd);
}
+
+ clk_set_parent( dc->vout_top_lcd, dc->dc8200_clk_pix1);
+
ret = clk_prepare_enable(dc->vout_top_lcd);
if (ret) {
dev_err(dev, "failed to prepare/enable vout_top_lcd\n");
return ret;
}
- */
+ #endif
#endif
printk("====> %s, %d.\n", __func__, __LINE__);
struct vs_crtc_state *crtc_state = to_vs_crtc_state(crtc->state);
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
struct dc_hw_display display;
+#ifdef CONFIG_STARFIVE_DSI//7110 mipi
+ #if 0
uint32_t vout_clock;
uint32_t div;
uint32_t div_new;
const uint32_t wanted_pxclk = mode->clock * 1000;
+ #endif
+#endif
display.bus_format = crtc_state->output_fmt;
display.h_active = mode->hdisplay;
display.enable = true;
-#if 1
- ;//printk("====> %s, %d--pix_clk.\n", __func__, __LINE__);
-#else
- //used for div clock
- if (dc->pix_clk_rate != mode->clock) {
- printk("====> %s, %d--pix_clk.mode->clock = %d\n", __func__, __LINE__,mode->clock);
- u32 div = _GET_CLOCK_DIVIDE_STATUS_CLK_DC8200_PIX0_;
- printk("====> %s, %d--pix_clk.div = %d\n", __func__, __LINE__,div);
-
- //148500
- div = 1228800/mode->clock;
- //148500
- printk("====> %s, %d--pix_clk.div = %d\n", __func__, __LINE__,div);
-
- _DIVIDE_CLOCK_CLK_DC8200_PIX0_(div);
- _SWITCH_CLOCK_CLK_U0_DC8200_CLK_PIX0_SOURCE_CLK_DC8200_PIX0_;
- _SWITCH_CLOCK_CLK_U0_DC8200_CLK_PIX1_SOURCE_CLK_DC8200_PIX0_;
-
- _SWITCH_CLOCK_CLK_DOM_VOUT_TOP_LCD_CLK_SOURCE_CLK_U0_DC8200_CLK_PIX0_OUT_;
-
- //clk_set_rate(dc->pix_clk, mode->clock * 1000);
- dc->pix_clk_rate = mode->clock;
- }
-#endif
-
-#ifdef CONFIG_STARFIVE_DSI//7110 mipi
- /*-----------------div freq clk sys_dispctrl_clk()----------*/
- //const uint32_t wanted_pxclk = 20144262;//dpi->pixelclock;
- //wanted_pxclk = mode->clock * 1000;
- dev_info(dev, "wanted_pxclk = %d\n",wanted_pxclk);
- //uint32_t vout_clock = 614400000;
- vout_clock = clk_get_rate(dc->vout_src);
- dev_info(dev, "vout_clock = %d\n", vout_clock);
- div = _GET_CLOCK_DIVIDE_STATUS_CLK_DC8200_PIX0_;
- div_new = vout_clock / wanted_pxclk;
- if (div != div_new) {
- div = div_new;
- _DIVIDE_CLOCK_CLK_DC8200_PIX0_(div);
- _SWITCH_CLOCK_CLK_U0_DC8200_CLK_PIX0_SOURCE_CLK_DC8200_PIX0_;
- }
- /*-----------------div freq clk sys_dispctrl_clk()----------*/
+#ifdef CONFIG_STARFIVE_DSI//
+ clk_set_rate(dc->dc8200_pix0, 20144263);//round up, 20144262+1
#endif
if (crtc_state->encoder_type == DRM_MODE_ENCODER_DSI)
fb->width = drm_rect_width(src) >> 16;
fb->height = drm_rect_height(src) >> 16;
fb->tile_mode = to_vs_tile_mode(drm_fb->modifier);
- printk("update_fb tile_mode = %d\n", to_vs_tile_mode(drm_fb->modifier));
//fb->tile_mode = 0x04;
fb->rotation = to_vs_rotation(state->rotation);
fb->yuv_color_space = to_vs_yuv_color_space(state->color_encoding);
const struct vs_dc_funcs *funcs;
-//noc bus clk
struct clk *cpu_axi;
struct clk *axicfg0_axi;
struct clk *disp_axi;
struct clk *stg_axi;
-//noc bus clk
-//noc bus rst
+
struct reset_control *cpu_axi_n;
struct reset_control *axicfg0_axi_n;
struct reset_control *apb_bus_n;
struct reset_control *disp_axi_n;
struct reset_control *stg_axi_n;
-//noc bus rst
-//vout top clk
struct clk *vout_src;
struct clk *vout_axi;
struct clk *ahb1;
struct clk *vout_ahb;
struct clk *hdmitx0_mclk;
struct clk *bclk_mst;
-//vout top clk
-//vout top rst
+
struct reset_control *rstn_vout_src;
-//vout top rst
-//dc8200 clk
- struct clk *dc8200_pix0;
- struct clk *dc8200_pix1;
+ struct clk *dc8200_clk_pix0;
+ struct clk *dc8200_clk_pix1;
struct clk *dc8200_axi;
struct clk *dc8200_core;
struct clk *dc8200_ahb;
-//dc8200 clk
-//dc8200 rst
+
struct reset_control *rstn_dc8200_axi;
struct reset_control *rstn_dc8200_core;
struct reset_control *rstn_dc8200_ahb;
-//dc8200 rst
-//7110 mp
-struct clk *vout_top_axi;
-struct clk *vout_top_lcd;
-//7110 mp
+ struct clk *vout_top_axi;
+ struct clk *vout_top_lcd;
+
+ struct clk *hdmitx0_pixelclk;
+ struct clk *dc8200_pix0;
+
+ struct regmap *dss_regmap;
};
extern struct platform_driver dc_platform_driver;
-//extern struct platform_driver simple_encoder_driver;
extern struct platform_driver starfive_dsi_platform_driver;
extern int init_seeed_panel(void);
extern void exit_seeed_panel(void);
#else
static u64 dma_mask = DMA_40BIT_MASK;
#endif
- printk("vs_drm_bind dma_mask = %08x\n", dma_mask);
- printk("vs_drm_bind LINUX_VERSION_CODE = %08x\n", LINUX_VERSION_CODE);
- printk("vs_drm_bind KERNEL_VERSION(2, 6, 24) = %08x\n", KERNEL_VERSION(2, 6, 24));
/* Remove existing drivers that may own the framebuffer memory. */
ret = drm_aperture_remove_framebuffers(false, &vs_drm_driver);
{
int ret;
- printk("%s:%d\n", __func__, __LINE__);
ret = platform_register_drivers(drm_sub_drivers, NUM_DRM_DRIVERS);
if (ret)
return ret;
return container_of(enc, struct simple_encoder, encoder);
}
+#if 0
static int encoder_parse_dt(struct device *dev)
{
struct simple_encoder *simple = dev_get_drvdata(dev);
err:
return ret;
}
+#endif
#define DOM_VOUT_SYSCON_8 0x8U
#define U0_LCD_DATA_MAPPING_DPI_DP_SEL_SHIFT 0x2U
void encoder_atomic_enable(struct drm_encoder *encoder,
struct drm_atomic_state *state)
{
- struct simple_encoder *simple = to_simple_encoder(encoder);
- struct dss_data *data = simple->dss_regdatas;
- int crtc_id;
-
- if (!simple->dss_regmap)
- return;
-
- crtc_id = drm_of_encoder_active_endpoint_id(
- simple->dev->of_node, encoder);
-
- regmap_update_bits(simple->dss_regmap, 0, data[crtc_id].mask,
- data[crtc_id].value);
-
- regmap_update_bits(simple->dss_regmap, DOM_VOUT_SYSCON_8, U0_LCD_DATA_MAPPING_DPI_DP_SEL_MASK, 0);
- regmap_update_bits(simple->dss_regmap, DOM_VOUT_SYSCON_4, U0_DISPLAY_PANEL_MUX_PANEL_SEL_MASK, 0);
+ return;
}
int encoder_atomic_check(struct drm_encoder *encoder,
struct simple_encoder *simple = dev_get_drvdata(dev);
struct drm_encoder *encoder;
struct drm_bridge *bridge;
- struct drm_panel *tmp_panel;
+
int ret;
encoder = &simple->encoder;
encoder->possible_crtcs =
drm_of_find_possible_crtcs(drm_dev, dev->of_node);
+ encoder->possible_crtcs = 3;
/* output port is port1*/
#ifdef CONFIG_STARFIVE_DSI
+ struct drm_panel *tmp_panel;
+
ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0,&tmp_panel, &bridge);
if (ret){
printk("==no panel, %d\n",ret);
{
struct device *dev = &pdev->dev;
struct simple_encoder *simple;
- int ret;
simple = devm_kzalloc(dev, sizeof(*simple), GFP_KERNEL);
if (!simple)
simple->dev = dev;
dev_set_drvdata(dev, simple);
-
+#if 0
ret = encoder_parse_dt(dev);
if (ret)
return ret;
-
+#endif
return component_add(dev, &encoder_component_ops);
}
+/dev/video0: Output the camera data directly.
+/dev/video1: Output the data of the camera converted by isp.
-/dev/video0 sensor配置为ov5640的设备节点
-/dev/video1 sensor配置为ov4689(i2c0)的设备节点
-/dev/video2 sensor配置为sc2235/ov4689(i2c2)的设备节点
-
-确认conf/sdk_210209_defconfig
-CONFIG_VIN_SENSOR_OV5640=y
+ensure linux/arch/riscv/configs/starfive_jh7110_defconfig:
+CONFIG_VIDEO_STF_VIN=y
CONFIG_VIN_SENSOR_SC2235=y
CONFIG_VIN_SENSOR_OV4689=y
-
-只支持DPHY的lane0/lane5做clk通道，lane1/2/3/4做数据通道。
-
-sensor port 设为okay, 硬件需要接入对应的sensor，否则驱动不能使用。
-
-1. ov5640 config dts:
- parallel_from_ov5640 port status 设置为okay, sc2235 port status 设为failed.
- port@2 {
- reg = <2>; // dvp sensor
-
- /* Parallel bus endpoint */
- parallel_from_ov5640: endpoint {
- remote-endpoint = <&ov5640_to_parallel>;
- bus-type = <5>; /* Parallel */
- bus-width = <8>;
- data-shift = <2>; /* lines 9:2 are used */
- hsync-active = <1>;
- vsync-active = <0>;
- pclk-sample = <1>;
- sensor-type = <0>; //0:SENSOR_VIN 1:SENSOR_ISP0 2:SENSOR_ISP1
- status = "okay";
- };
- };
-
-2. SC2235 config dts:
- stf_isp_hw_ops.c:
- stf_isp_set_format函数里面注释掉：
- // isp_settings = isp_1920_1080_settings;
-
- parallel_from_sc2235 port status 设置为okay, ov5640/ov4689(i2c2) port status设为failed.
- port@3 {
- reg = <2>; // dvp sensor
-
- /* Parallel bus endpoint */
- parallel_from_sc2235: endpoint {
- remote-endpoint = <&sc2235_to_parallel>;
- bus-type = <5>; /* Parallel */
- bus-width = <8>;
- data-shift = <2>; /* lines 9:2 are used */
- hsync-active = <1>;
- vsync-active = <1>;
- pclk-sample = <1>;
- sensor-type = <2>; //0:SENSOR_VIN 1:SENSOR_ISP0 2:SENSOR_ISP1
- status = "okay";
- };
- };
-
-3. i2c0 ov4689 config dts:
- csi2rx0_from_ov4689 port status 设置为okay.
- port@4 {
- reg = <3>; // csi2rx0 sensor
-
- /* CSI2 bus endpoint */
- csi2rx0_from_ov4689: endpoint {
- remote-endpoint = <&ov4689_to_csi2rx0>;
- bus-type = <4>; /* MIPI CSI-2 D-PHY */
- clock-lanes = <0>;
- data-lanes = <1 2>;
- sensor-type = <1>; //0:SENSOR_VIN 1:SENSOR_ISP0 2:SENSOR_ISP1
- csi-dt = <0x2b>;
- status = "okay";
- };
- };
-
-4. i2c2 ov4689 config dts:
-
- stf_isp_hw_ops.c:
- stf_isp_set_format函数里面346行不要注释掉：
- isp_settings = isp_1920_1080_settings;
-
- csi2rx1_from_ov4689 port status 设置为okay, sc2235 port status 设为failed.
- port@5 {
- reg = <4>; // csi2rx1 sensor
-
- /* CSI2 bus endpoint */
- csi2rx1_from_ov4689: endpoint {
- remote-endpoint = <&ov4689_to_csi2rx1>;
- bus-type = <4>; /* MIPI CSI-2 D-PHY */
- clock-lanes = <5>;
- data-lanes = <4 3>;
- lane-polarities = <1 1 1>;
- sensor-type = <2>; //0:SENSOR_VIN 1:SENSOR_ISP0 2:SENSOR_ISP1
- csi-dt = <0x2b>;
- status = "okay";
- };
- };
-
+Only support the lane0/lane5 of dphy as clock lane, lane1/lane2/lane3/lane4
+as data lane.
struct v4l2_ctrl *vflip;
};
-struct sensor_pinctrl_info {
- struct pinctrl *pinctrl;
- struct pinctrl_state *reset_state_low;
- struct pinctrl_state *reset_state_high;
- bool use_pinctrl;
-};
-
struct sc2235_dev {
struct i2c_client *i2c_client;
struct v4l2_subdev sd;
bool pending_mode_change;
bool streaming;
-
- struct sensor_pinctrl_info sc2235_pctrl;
};
-int sc2235_sensor_pinctrl_init(
- struct sensor_pinctrl_info *sensor_pctrl, struct device *dev)
-{
- sensor_pctrl->pinctrl = devm_pinctrl_get(dev);
- if (IS_ERR_OR_NULL(sensor_pctrl->pinctrl)) {
- pr_err("Getting pinctrl handle failed\n");
- return -EINVAL;
- }
-
- sensor_pctrl->reset_state_low
- = pinctrl_lookup_state(sensor_pctrl->pinctrl, "reset_low");
- if (IS_ERR_OR_NULL(sensor_pctrl->reset_state_low)) {
- pr_err("Failed to get the reset_low pinctrl handle\n");
- return -EINVAL;
- }
-
- sensor_pctrl->reset_state_high
- = pinctrl_lookup_state(sensor_pctrl->pinctrl, "reset_high");
- if (IS_ERR_OR_NULL(sensor_pctrl->reset_state_high)) {
- pr_err("Failed to get the reset_high pinctrl handle\n");
- return -EINVAL;
- }
-
- sensor_pctrl->use_pinctrl = true;
-
- return 0;
-}
-
static inline struct sc2235_dev *to_sc2235_dev(struct v4l2_subdev *sd)
{
return container_of(sd, struct sc2235_dev, sd);
ctrls.handler)->sd;
}
-/* sc2235 initial register 7fps*/
-static struct reg_value sc2235_init_tbl_1080p_7fps[] = {
- {0x0103, 0x01, 0, 0},
- {0x0100, 0x00, 0, 0},
- {0x3039, 0x75, 0, 0},
- {0x320c, 0x08, 0, 0},
- {0x320d, 0x98, 0, 0},
- {0x3222, 0x29, 0, 0},
- {0x3235, 0x04, 0, 0},
- {0x3236, 0x63, 0, 0},
- {0x3237, 0x08, 0, 0},
- {0x3238, 0x68, 0, 0},
- {0x3301, 0x04, 0, 0},
- {0x3303, 0x20, 0, 0},
- {0x3306, 0x1a, 0, 0},
- {0x3309, 0xa0, 0, 0},
- {0x330b, 0x54, 0, 0},
- {0x330e, 0x30, 0, 0},
- {0x3313, 0x05, 0, 0},
- {0x331e, 0x0d, 0, 0},
- {0x331f, 0x8d, 0, 0},
- {0x3320, 0x0f, 0, 0},
- {0x3321, 0x8f, 0, 0},
- {0x3340, 0x06, 0, 0},
- {0x3341, 0x50, 0, 0},
- {0x3342, 0x04, 0, 0},
- {0x3343, 0x20, 0, 0},
- {0x3348, 0x07, 0, 0},
- {0x3349, 0x80, 0, 0},
- {0x334a, 0x04, 0, 0},
- {0x334b, 0x20, 0, 0},
- {0x335e, 0x01, 0, 0},
- {0x335f, 0x03, 0, 0},
- {0x3364, 0x05, 0, 0},
- {0x3366, 0x7c, 0, 0},
- {0x3367, 0x08, 0, 0},
- {0x3368, 0x02, 0, 0},
- {0x3369, 0x00, 0, 0},
- {0x336a, 0x00, 0, 0},
- {0x336b, 0x00, 0, 0},
- {0x337c, 0x04, 0, 0},
- {0x337d, 0x06, 0, 0},
- {0x337f, 0x03, 0, 0},
- {0x3380, 0x04, 0, 0},
- {0x3381, 0x0a, 0, 0},
- {0x33a0, 0x05, 0, 0},
- {0x33b5, 0x10, 0, 0},
- {0x3621, 0x28, 0, 0},
- {0x3622, 0x06, 0, 0},
- {0x3625, 0x02, 0, 0},
- {0x3630, 0x48, 0, 0},
- {0x3631, 0x84, 0, 0},
- {0x3632, 0x88, 0, 0},
- {0x3633, 0x42, 0, 0},
- {0x3634, 0x42, 0, 0},
- {0x3636, 0x24, 0, 0},
- {0x3635, 0xc1, 0, 0},
- {0x3637, 0x14, 0, 0},
- {0x3638, 0x1f, 0, 0},
- {0x363b, 0x09, 0, 0},
- {0x3639, 0x09, 0, 0},
- {0x363c, 0x07, 0, 0},
- {0x366e, 0x08, 0, 0},
- {0x3670, 0x08, 0, 0},
- {0x366f, 0x2f, 0, 0},
- {0x3677, 0x1f, 0, 0},
- {0x3678, 0x42, 0, 0},
- {0x3679, 0x43, 0, 0},
- {0x367e, 0x07, 0, 0},
- {0x367f, 0x0f, 0, 0},
- {0x3802, 0x01, 0, 0},
- {0x3901, 0x02, 0, 0},
- {0x3908, 0x11, 0, 0},
- {0x391b, 0x4d, 0, 0},
- {0x391e, 0x00, 0, 0},
- {0x3e01, 0x46, 0, 0},
- {0x3e03, 0x0b, 0, 0},
- {0x3f00, 0x07, 0, 0},
- {0x3f04, 0x08, 0, 0},
- {0x3f05, 0x74, 0, 0},
- {0x4500, 0x59, 0, 0},
- {0x5780, 0xff, 0, 0},
- {0x5781, 0x04, 0, 0},
- {0x5785, 0x18, 0, 0},
- //{0x0100, 0x01, 0, 0},
- {0x330b, 0x5d, 0, 0},
- {0x3301, 0x0a, 0, 0},
- {0x3631, 0x88, 0, 0},
- {0x366f, 0x2f, 0, 0},
-};
-
/* sc2235 initial register 30fps*/
static struct reg_value sc2235_init_regs_tbl_1080[] = {
{0x0103, 0x01, 0, 50},
static int sc2235_set_power_on(struct sc2235_dev *sensor)
{
struct i2c_client *client = sensor->i2c_client;
- struct sensor_pinctrl_info *sensor_pctrl = &sensor->sc2235_pctrl;
int ret;
ret = clk_prepare_enable(sensor->xclk);
goto xclk_off;
}
- if (sensor_pctrl->use_pinctrl) {
- ret = pinctrl_select_state(
- sensor_pctrl->pinctrl,
- sensor_pctrl->reset_state_high);
- if (ret)
- pr_err("cannot set reset pin to high\n");
- } else {
- sc2235_reset(sensor);
- sc2235_power(sensor, true);
- }
+ sc2235_reset(sensor);
+ sc2235_power(sensor, true);
return 0;
static void sc2235_set_power_off(struct sc2235_dev *sensor)
{
- struct sensor_pinctrl_info *sensor_pctrl = &sensor->sc2235_pctrl;
- int ret;
-
- if (sensor_pctrl->use_pinctrl) {
- ret = pinctrl_select_state(
- sensor_pctrl->pinctrl,
- sensor_pctrl->reset_state_low);
- if (ret)
- pr_err("cannot set reset pin to low\n");
- } else {
- sc2235_power(sensor, false);
- }
+ sc2235_power(sensor, false);
regulator_bulk_disable(SC2235_NUM_SUPPLIES, sensor->supplies);
clk_disable_unprepare(sensor->xclk);
struct v4l2_subdev_state *state,
struct v4l2_subdev_frame_interval_enum *fie)
{
- struct sc2235_dev *sensor = to_sc2235_dev(sd);
struct v4l2_fract tpf;
- int ret;
if (fie->pad != 0)
return -EINVAL;
tpf.numerator = 1;
tpf.denominator = sc2235_framerates[fie->index];
- ret = sc2235_try_frame_interval(sensor, &tpf,
- fie->width, fie->height);
- if (ret < 0)
- return -EINVAL;
-
fie->interval = tpf;
return 0;
}
return -EINVAL;
}
- ret = sc2235_sensor_pinctrl_init(&sensor->sc2235_pctrl, dev);
- if (ret) {
- pr_err("Can't get pinctrl, use gpio to ctrl\n");
- sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
- sensor->sc2235_pctrl.use_pinctrl = false;
- }
+ sensor->pwdn_gpio = devm_gpiod_get_optional(dev, "powerdown",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(sensor->pwdn_gpio))
+ return PTR_ERR(sensor->pwdn_gpio);
+
+ sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(sensor->reset_gpio))
+ return PTR_ERR(sensor->reset_gpio);
v4l2_i2c_subdev_init(&sensor->sd, client, &sc2235_subdev_ops);
static int stf_csi_power_on(struct stf_csi_dev *csi_dev, u8 on)
{
- void __iomem *aon_syscon;
+ struct stfcamss *stfcamss = csi_dev->stfcamss;
int ret;
if (on) {
st_err(ST_CSI, "Cannot enable mipirx_0p9 regulator\n");
goto err_0p9;
}
- }
- else
- {
+ } else {
regulator_disable(csi_dev->mipirx_1p8);
regulator_disable(csi_dev->mipirx_0p9);
}
- aon_syscon = ioremap(0x17010000, 0x4);
- reg_write(aon_syscon, 0x00, 0x80000000);
+ regmap_write(stfcamss->stf_aon_syscon, stfcamss->aon_gp_reg, 0x80000000);
return 0;
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/uaccess.h>
+#include <linux/mfd/syscon.h>
#include <linux/videodev2.h>
struct stfcamss *stfcamss;
struct stf_vin_dev *vin;
struct device *dev = &pdev->dev;
+ struct of_phandle_args args;
int ret = 0, num_subdevs;
dev_info(dev, "stfcamss probe enter!\n");
return ret;
}
+ ret = of_parse_phandle_with_fixed_args(dev->of_node,
+ "starfive,aon-syscon", 1, 0, &args);
+ if (ret < 0) {
+ dev_err(dev, "Failed to parse starfive,aon-syscon\n");
+ return -EINVAL;
+ }
+
+ stfcamss->stf_aon_syscon = syscon_node_to_regmap(args.np);
+ of_node_put(args.np);
+ if (IS_ERR(stfcamss->stf_aon_syscon))
+ return PTR_ERR(stfcamss->stf_aon_syscon);
+
+ stfcamss->aon_gp_reg = args.args[0];
+
ret = stfcamss_get_mem_res(pdev, vin);
if (ret) {
st_err(ST_CAMSS, "Could not map registers\n");
int nclks;
struct reset_control_bulk_data *sys_rst;
int nrsts;
+ struct regmap *stf_aon_syscon;
+ uint32_t aon_gp_reg;
#ifdef CONFIG_DEBUG_FS
struct dentry *debugfs_entry;
struct dentry *vin_debugfs;
#include <linux/reset.h>
#include <linux/usb/otg.h>
-#define USB_STRAP_HOST (2 << 0x10)
-#define USB_STRAP_DEVICE (4 << 0X10)
-#define USB_STRAP_MASK 0x70000U
-
-#define USB_SUSPENDM_HOST (1 << 0x13)
-#define USB_SUSPENDM_DEVICE (0 << 0x13)
-#define USB_SUSPENDM_MASK 0x80000U
-
-#define USB_SUSPENDM_BYPS_SHIFT 0x14U
-#define USB_SUSPENDM_BYPS_MASK 0x100000U
-
-#define USB_REFCLK_MODE_SHIFT 0x17U
-#define USB_REFCLK_MODE_MASK 0x800000U
-
-#define USB_PLL_EN_SHIFT 0x16U
-#define USB_PLL_EN_MASK 0x400000U
-
-#define USB_PDRSTN_SPLIT_SHIFT 0x11
-#define USB_PDRSTN_SPLIT_MASK 0x20000U
-
-#define PCIE_CKREF_SRC_SHIFT 0x12U
-#define PCIE_CKREF_SRC_MASK 0xC0000U
-#define PCIE_CLK_SEL_SHIFT 0x14U
-#define PCIE_CLK_SEL_MASK 0x300000U
-#define PCIE_PHY_MODE_SHIFT 0x14U
-#define PCIE_PHY_MODE_MASK 0x300000U
-#define PCIE_USB3_BUS_WIDTH_SHIFT 0x2U
-#define PCIE_USB3_BUS_WIDTH_MASK 0xCU
-#define PCIE_USB3_RATE_SHIFT 0x5U
-#define PCIE_USB3_RATE_MASK 0x60U
-#define PCIE_USB3_RX_STANDBY_SHIFT 0x7U
-#define PCIE_USB3_RX_STANDBY_MASK 0x80U
-#define PCIE_USB3_PHY_ENABLE_SHIFT 0x4U
-#define PCIE_USB3_PHY_ENABLE_MASK 0x10U
+#define USB_STRAP_HOST (2 << 0x10)
+#define USB_STRAP_DEVICE (4 << 0X10)
+#define USB_STRAP_MASK 0x70000
+
+#define USB_SUSPENDM_HOST (1 << 0x13)
+#define USB_SUSPENDM_DEVICE (0 << 0x13)
+#define USB_SUSPENDM_MASK 0x80000
+
+#define USB_SUSPENDM_BYPS_SHIFT 0x14
+#define USB_SUSPENDM_BYPS_MASK 0x100000
+#define USB_REFCLK_MODE_SHIFT 0x17
+#define USB_REFCLK_MODE_MASK 0x800000
+#define USB_PLL_EN_SHIFT 0x16
+#define USB_PLL_EN_MASK 0x400000
+#define USB_PDRSTN_SPLIT_SHIFT 0x11
+#define USB_PDRSTN_SPLIT_MASK 0x20000
+
+#define PCIE_CKREF_SRC_SHIFT 0x12
+#define PCIE_CKREF_SRC_MASK 0xC0000
+#define PCIE_CLK_SEL_SHIFT 0x14
+#define PCIE_CLK_SEL_MASK 0x300000
+#define PCIE_PHY_MODE_SHIFT 0x14
+#define PCIE_PHY_MODE_MASK 0x300000
+#define PCIE_USB3_BUS_WIDTH_SHIFT 0x2
+#define PCIE_USB3_BUS_WIDTH_MASK 0xC
+#define PCIE_USB3_RATE_SHIFT 0x5
+#define PCIE_USB3_RATE_MASK 0x60
+#define PCIE_USB3_RX_STANDBY_SHIFT 0x7
+#define PCIE_USB3_RX_STANDBY_MASK 0x80
+#define PCIE_USB3_PHY_ENABLE_SHIFT 0x4
+#define PCIE_USB3_PHY_ENABLE_MASK 0x10
+
+#define USB_125M_CLK_RATE 125000000
struct cdns_starfive {
struct device *dev;
struct reset_control *resets;
struct clk_bulk_data *clks;
int num_clks;
+ struct clk *usb_125m_clk;
u32 sys_offset;
u32 stg_offset_4;
u32 stg_offset_196;
{
enum usb_dr_mode mode;
- /*usb 2.0 utmi phy init*/
+ /* Init usb 2.0 utmi phy */
regmap_update_bits(data->stg_syscon, data->stg_offset_4,
USB_SUSPENDM_BYPS_MASK, BIT(USB_SUSPENDM_BYPS_SHIFT));
regmap_update_bits(data->stg_syscon, data->stg_offset_4,
if (data->usb2_only) {
- /* disconnect usb 3.0 phy mode */
+ /* Disconnect usb 3.0 phy mode */
regmap_update_bits(data->sys_syscon, data->sys_offset,
USB_PDRSTN_SPLIT_MASK, BIT(USB_PDRSTN_SPLIT_SHIFT));
} else {
- /*usb 3.0 pipe phy config*/
+ /* Config usb 3.0 pipe phy */
regmap_update_bits(data->stg_syscon, data->stg_offset_196,
PCIE_CKREF_SRC_MASK, (0<<PCIE_CKREF_SRC_SHIFT));
regmap_update_bits(data->stg_syscon, data->stg_offset_196,
regmap_update_bits(data->stg_syscon, data->stg_offset_500,
PCIE_USB3_PHY_ENABLE_MASK, BIT(PCIE_USB3_PHY_ENABLE_SHIFT));
- /* connect usb 3.0 phy mode */
+ /* Connect usb 3.0 phy mode */
regmap_update_bits(data->sys_syscon, data->sys_offset,
USB_PDRSTN_SPLIT_MASK, (0 << USB_PDRSTN_SPLIT_SHIFT));
}
{
int ret;
+ data->usb_125m_clk = devm_clk_get(data->dev, "125m");
+ if (IS_ERR(data->usb_125m_clk)) {
+ dev_err(data->dev, "Failed to get usb 125m clock\n");
+ ret = PTR_ERR(data->usb_125m_clk);
+ goto exit;
+ }
+
data->num_clks = devm_clk_bulk_get_all(data->dev, &data->clks);
if (data->num_clks < 0) {
dev_err(data->dev, "Failed to get usb clocks\n");
ret = -ENODEV;
goto exit;
}
+
+ /* Needs to set the USB_125M clock explicitly,
+ * since it's divided from pll0 clock, and the pll0 clock
+ * changes per the cpu frequency.
+ */
+ ret = clk_set_rate(data->usb_125m_clk, USB_125M_CLK_RATE);
+ if (ret) {
+ dev_err(data->dev, "Failed to set usb 125m clock\n");
+ goto exit;
+ }
ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
if (ret) {
dev_err(data->dev, "Failed to enable clocks\n");
ret = of_platform_populate(node, NULL, NULL, dev);
if (ret) {
- dev_err(dev, "failed to create children: %d\n", ret);
+ dev_err(dev, "Failed to create children: %d\n", ret);
goto exit;
}
MODULE_ALIAS("platform:cdns3-starfive");
MODULE_AUTHOR("YanHong Wang <yanhong.wang@starfivetech.com>");
+MODULE_AUTHOR("Mason Huo <mason.huo@starfivetech.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Cadence USB3 StarFive SoC platform");
}
}
-static int dw_i2s_startup(struct snd_pcm_substream *substream,
- struct snd_soc_dai *cpu_dai)
-{
- struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
- union dw_i2s_snd_dma_data *dma_data = NULL;
-
- if (!(dev->capability & DWC_I2S_RECORD) &&
- (substream->stream == SNDRV_PCM_STREAM_CAPTURE))
- return -EINVAL;
-
- if (!(dev->capability & DWC_I2S_PLAY) &&
- (substream->stream == SNDRV_PCM_STREAM_PLAYBACK))
- return -EINVAL;
-
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
- dma_data = &dev->play_dma_data;
- else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
- dma_data = &dev->capture_dma_data;
-
- snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);
- return 0;
-}
-
static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
{
u32 ch_reg;
struct i2s_clk_config_data *config = &dev->config;
int ret;
unsigned int bclk_rate;
+ union dw_i2s_snd_dma_data *dma_data = NULL;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
return -EINVAL;
}
+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+ dma_data = &dev->capture_dma_data;
+ }
+ snd_soc_dai_set_dma_data(dai, substream, (void *)dma_data);
+
dw_i2s_config(dev, substream->stream);
i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
return 0;
}
-static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
- struct snd_soc_dai *dai)
-{
- snd_soc_dai_set_dma_data(dai, substream, NULL);
-}
-
static int dw_i2s_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
}
static const struct snd_soc_dai_ops dw_i2s_dai_ops = {
- .startup = dw_i2s_startup,
- .shutdown = dw_i2s_shutdown,
.hw_params = dw_i2s_hw_params,
.prepare = dw_i2s_prepare,
.trigger = dw_i2s_trigger,
-/**
- ******************************************************************************
- * @file sf_spdif.c
- * @author StarFive Technology
- * @version V1.0
- * @date 05/27/2021
- * @brief
- ******************************************************************************
- * @copy
- *
- * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 20120 Shanghai StarFive Technology Co., Ltd. </center></h2>
- */
+//SPDX-License-Identifier: GPL-2.0
+/*
+ * SPDIF driver for the StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
#include <linux/init.h>
#include <linux/kernel.h>
regmap_read(dev->regmap, SPDIF_STAT_REG, &stat);
regmap_update_bits(dev->regmap, SPDIF_CTRL,
SPDIF_MASK_ENABLE, 0);
- regmap_update_bits(dev->regmap, SPDIF_INT_REG,
+ regmap_update_bits(dev->regmap, SPDIF_INT_REG,
SPDIF_INT_REG_BIT, 0);
if ((stat & SPDIF_EMPTY_FLAG) || (stat & SPDIF_AEMPTY_FLAG)) {
sf_spdif_pcm_push_tx(dev);
irq_valid = true;
- }
-
+ }
+
if ((stat & SPDIF_FULL_FLAG) || (stat & SPDIF_AFULL_FLAG)) {
sf_spdif_pcm_pop_rx(dev);
irq_valid = true;
- }
+ }
- if (stat & SPDIF_PARITY_FLAG) {
+ if (stat & SPDIF_PARITY_FLAG)
irq_valid = true;
- }
-
- if (stat & SPDIF_UNDERR_FLAG) {
+
+ if (stat & SPDIF_UNDERR_FLAG)
irq_valid = true;
- }
-
- if (stat & SPDIF_OVRERR_FLAG) {
+
+ if (stat & SPDIF_OVRERR_FLAG)
irq_valid = true;
- }
-
- if (stat & SPDIF_SYNCERR_FLAG) {
+
+ if (stat & SPDIF_SYNCERR_FLAG)
irq_valid = true;
- }
-
- if (stat & SPDIF_LOCK_FLAG) {
+
+ if (stat & SPDIF_LOCK_FLAG)
irq_valid = true;
- }
-
- if (stat & SPDIF_BEGIN_FLAG) {
+
+ if (stat & SPDIF_BEGIN_FLAG)
irq_valid = true;
- }
- if (stat & SPDIF_RIGHT_LEFT) {
+ if (stat & SPDIF_RIGHT_LEFT)
irq_valid = true;
- }
regmap_update_bits(dev->regmap, SPDIF_CTRL,
SPDIF_MASK_ENABLE, SPDIF_MASK_ENABLE);
/* tx mode */
regmap_update_bits(spdif->regmap, SPDIF_CTRL,
SPDIF_TR_MODE, SPDIF_TR_MODE);
-
+
regmap_update_bits(spdif->regmap, SPDIF_CTRL,
SPDIF_MASK_FIFO, SPDIF_EMPTY_MASK | SPDIF_AEMPTY_MASK);
} else {
/* rx mode */
regmap_update_bits(spdif->regmap, SPDIF_CTRL,
SPDIF_TR_MODE, 0);
-
+
regmap_update_bits(spdif->regmap, SPDIF_CTRL,
SPDIF_MASK_FIFO, SPDIF_FULL_MASK | SPDIF_AFULL_MASK);
}
/* clock recovery form the SPDIF data stream 0:clk_enable */
regmap_update_bits(spdif->regmap, SPDIF_CTRL,
SPDIF_CLK_ENABLE, 0);
-
+
regmap_update_bits(spdif->regmap, SPDIF_CTRL,
SPDIF_ENABLE, SPDIF_ENABLE);
break;
/* clock recovery form the SPDIF data stream 1:power save mode */
regmap_update_bits(spdif->regmap, SPDIF_CTRL,
SPDIF_CLK_ENABLE, SPDIF_CLK_ENABLE);
-
+
regmap_update_bits(spdif->regmap, SPDIF_CTRL,
SPDIF_ENABLE, 0);
break;
default:
- printk(KERN_ERR "%s L.%d cmd:%d\n", __func__, __LINE__, cmd);
+ dev_err(dai->dev, "%s L.%d cmd:%d\n", __func__, __LINE__, cmd);
return -EINVAL;
}
unsigned int rate;
unsigned int format;
unsigned int tsamplerate;
+ unsigned int mclk;
+ int ret;
channels = params_channels(params);
rate = params_rate(params);
format = params_format(params);
-
+
switch (channels) {
case 2:
break;
case SNDRV_PCM_FORMAT_S32_LE:
break;
default:
- dev_err(spdif->dev, "invalid format\n");
+ dev_err(dai->dev, "invalid format\n");
return -EINVAL;
}
switch (rate) {
case 8000:
+ mclk = 4096000;
+ break;
case 11025:
+ mclk = 5644800;
+ break;
case 16000:
+ mclk = 8192000;
+ break;
case 22050:
+ mclk = 11289600;
break;
default:
- printk(KERN_ERR "channel:%d sample rate:%d\n", channels, rate);
+ dev_err(dai->dev, "channel:%d sample rate:%d\n", channels, rate);
return -EINVAL;
}
- /* 4096000/128=32000 */
- tsamplerate = (32000 + rate/2)/rate - 1;
-
- if (rate < 3) {
- return -EINVAL;
+ ret = clk_set_rate(spdif->mclk_inner, mclk);
+ if (ret) {
+ dev_err(dai->dev, "failed to set rate for spdif mclk_inner ret=%d\n", ret);
+ return ret;
}
-
+
+ /* (FCLK)4096000/128=32000 */
+ tsamplerate = (32000 + rate/2)/rate - 1;
+
+ if (tsamplerate < 3)
+ tsamplerate = 3;
+
/* transmission sample rate */
regmap_update_bits(spdif->regmap, SPDIF_CTRL, 0xFF, tsamplerate);
static int sf_spdif_clks_get(struct platform_device *pdev,
struct sf_spdif_dev *spdif)
{
-
static struct clk_bulk_data clks[] = {
- { .id = "spdif-apb" }, //clock-names in dts file
- { .id = "spdif-core" },
- { .id = "audioclk" },
+ { .id = "spdif-apb" }, /* clock-names in dts file */
+ { .id = "spdif-core" },
+ { .id = "apb0" },
+ { .id = "audroot" },
+ { .id = "mclk_inner"},
};
int ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(clks), clks);
+
spdif->spdif_apb = clks[0].clk;
spdif->spdif_core = clks[1].clk;
- spdif->audioclk = clks[2].clk;
+ spdif->apb0_clk = clks[2].clk;
+ spdif->audio_root = clks[3].clk;
+ spdif->mclk_inner = clks[4].clk;
return ret;
}
ret = clk_prepare_enable(spdif->spdif_apb);
if (ret) {
dev_err(&pdev->dev, "failed to prepare enable spdif_apb\n");
- goto err_clk_spdif;
+ goto disable_apb_clk;
}
ret = clk_prepare_enable(spdif->spdif_core);
if (ret) {
dev_err(&pdev->dev, "failed to prepare enable spdif_core\n");
- goto err_clk_spdif;
+ goto disable_core_clk;
+ }
+
+ ret = clk_prepare_enable(spdif->apb0_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to prepare enable apb0_clk\n");
+ goto disable_apb0_clk;
+ }
+
+ ret = clk_prepare_enable(spdif->audio_root);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to prepare enable spdif->audio_root\n");
+ goto disable_audroot_clk;
}
- ret = clk_prepare_enable(spdif->audioclk);
+ ret = clk_set_rate(spdif->audio_root, 204800000);
if (ret) {
- dev_err(&pdev->dev, "failed to prepare enable audioclk\n");
- goto err_clk_spdif;
+ dev_err(&pdev->dev, "failed to set rate for spdif audroot ret=%d\n", ret);
+ goto disable_audroot_clk;
}
+ ret = clk_prepare_enable(spdif->mclk_inner);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to prepare enable spdif->mclk_inner\n");
+ goto disable_mclk_clk;
+ }
+
+ ret = clk_set_rate(spdif->mclk_inner, 8192000);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to set rate for spdif mclk_inner ret=%d\n", ret);
+ goto disable_mclk_clk;
+ }
+
+ dev_dbg(&pdev->dev, "spdif->spdif_apb = %lu\n", clk_get_rate(spdif->spdif_apb));
+ dev_dbg(&pdev->dev, "spdif->spdif_core = %lu\n", clk_get_rate(spdif->spdif_core));
+ dev_dbg(&pdev->dev, "spdif->apb0_clk = %lu\n", clk_get_rate(spdif->apb0_clk));
+
ret = reset_control_deassert(spdif->rst_apb);
if (ret) {
- printk(KERN_INFO "failed to deassert apb\n");
- goto err_clk_spdif;
+ dev_err(&pdev->dev, "failed to deassert apb\n");
+ goto disable_mclk_clk;
}
- printk(KERN_INFO "Initialize spdif...success\n");
+ return 0;
-err_clk_spdif:
- return ret;
+disable_mclk_clk:
+ clk_disable_unprepare(spdif->mclk_inner);
+disable_audroot_clk:
+ clk_disable_unprepare(spdif->audio_root);
+disable_apb0_clk:
+ clk_disable_unprepare(spdif->apb0_clk);
+disable_core_clk:
+ clk_disable_unprepare(spdif->spdif_core);
+disable_apb_clk:
+ clk_disable_unprepare(spdif->spdif_apb);
+
+ return ret;
}
static int sf_spdif_dai_probe(struct snd_soc_dai *dai)
{
struct sf_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
- #if 0
- spdif->play_dma_data.addr = (dma_addr_t)spdif->spdif_base + SPDIF_FIFO_ADDR;
- spdif->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
- spdif->play_dma_data.fifo_size = 16;
- spdif->play_dma_data.maxburst = 16;
- spdif->capture_dma_data.addr = (dma_addr_t)spdif->spdif_base + SPDIF_FIFO_ADDR;
- spdif->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
- spdif->capture_dma_data.fifo_size = 16;
- spdif->capture_dma_data.maxburst = 16;
- snd_soc_dai_init_dma_data(dai, &spdif->play_dma_data, &spdif->capture_dma_data);
- snd_soc_dai_set_drvdata(dai, spdif);
- #endif
-
/* reset */
regmap_update_bits(spdif->regmap, SPDIF_CTRL,
SPDIF_ENABLE | SPDIF_SFR_ENABLE | SPDIF_FIFO_ENABLE, 0);
/* clear irq */
regmap_update_bits(spdif->regmap, SPDIF_INT_REG,
- SPDIF_INT_REG_BIT, 0);
+ SPDIF_INT_REG_BIT, 0);
/* power save mode */
regmap_update_bits(spdif->regmap, SPDIF_CTRL,
SPDIF_SETPREAMBB, SPDIF_SETPREAMBB);
regmap_update_bits(spdif->regmap, SPDIF_INT_REG,
- 0x1FFF<<SPDIF_PREAMBLEDEL, 0x3<<SPDIF_PREAMBLEDEL);
+ BIT8TO20MASK<<SPDIF_PREAMBLEDEL, 0x3<<SPDIF_PREAMBLEDEL);
regmap_update_bits(spdif->regmap, SPDIF_FIFO_CTRL,
- 0xFFFFFFFF, 0x20|(0x20<<SPDIF_AFULL_THRESHOLD));
+ ALLBITMASK, 0x20|(0x20<<SPDIF_AFULL_THRESHOLD));
regmap_update_bits(spdif->regmap, SPDIF_CTRL,
SPDIF_PARITYGEN, SPDIF_PARITYGEN);
};
#define SF_PCM_RATE_44100_192000 (SNDRV_PCM_RATE_44100 | \
- SNDRV_PCM_RATE_48000 | \
- SNDRV_PCM_RATE_96000 | \
- SNDRV_PCM_RATE_192000)
-
+ SNDRV_PCM_RATE_48000 | \
+ SNDRV_PCM_RATE_96000 | \
+ SNDRV_PCM_RATE_192000)
+
#define SF_PCM_RATE_8000_22050 (SNDRV_PCM_RATE_8000 | \
- SNDRV_PCM_RATE_11025 | \
- SNDRV_PCM_RATE_16000 | \
- SNDRV_PCM_RATE_22050)
+ SNDRV_PCM_RATE_11025 | \
+ SNDRV_PCM_RATE_16000 | \
+ SNDRV_PCM_RATE_22050)
static struct snd_soc_dai_driver sf_spdif_dai = {
.name = "spdif",
.channels_min = 2,
.channels_max = 2,
.rates = SF_PCM_RATE_8000_22050,
- .formats = SNDRV_PCM_FMTBIT_S16_LE \
- |SNDRV_PCM_FMTBIT_S24_LE \
- |SNDRV_PCM_FMTBIT_S32_LE,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SF_PCM_RATE_8000_22050,
- .formats = SNDRV_PCM_FMTBIT_S16_LE \
- |SNDRV_PCM_FMTBIT_S24_LE \
- |SNDRV_PCM_FMTBIT_S32_LE,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &sf_spdif_dai_ops,
.symmetric_rate = 1,
ret = sf_spdif_clks_get(pdev, spdif);
if (ret) {
- dev_err(&pdev->dev, "failed to get audio clock\n");
- return ret;
+ dev_err(&pdev->dev, "failed to get audio clock\n");
+ return ret;
}
ret = sf_spdif_resets_get(pdev, spdif);
if (ret) {
- dev_err(&pdev->dev, "failed to get audio reset controls\n");
- return ret;
+ dev_err(&pdev->dev, "failed to get audio reset controls\n");
+ return ret;
}
ret = sf_spdif_clk_init(pdev, spdif);
if (ret) {
- dev_err(&pdev->dev, "failed to enable audio clock\n");
- return ret;
+ dev_err(&pdev->dev, "failed to enable audio clock\n");
+ return ret;
}
-
+
spdif->dev = &pdev->dev;
spdif->fifo_th = 16;
-
+
irq = platform_get_irq(pdev, 0);
if (irq >= 0) {
ret = devm_request_irq(&pdev->dev, irq, spdif_irq_handler, 0,
&sf_spdif_dai, 1);
if (ret)
goto err_clk_disable;
-
+
if (irq >= 0) {
ret = sf_spdif_pcm_register(pdev);
spdif->use_pio = true;
};
module_platform_driver(sf_spdif_driver);
-MODULE_AUTHOR("curry.zhang <michael.yan@starfive.com>");
+MODULE_AUTHOR("curry.zhang <curry.zhang@starfive.com>");
MODULE_DESCRIPTION("starfive SPDIF driver");
MODULE_LICENSE("GPL v2");
-/**
- ******************************************************************************
- * @file sf_spdif.h
- * @author StarFive Technology
- * @version V1.0
- * @date 05/27/2021
- * @brief
- ******************************************************************************
- * @copy
- *
- * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 20120 Shanghai StarFive Technology Co., Ltd. </center></h2>
- */
+//SPDX-License-Identifier: GPL-2.0
+/*
+ * SPDIF driver for the StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
#ifndef __SND_SOC_STARFIVE_SPDIF_H
#define __SND_SOC_STARFIVE_SPDIF_H
#include <linux/dmaengine.h>
#include <linux/types.h>
-#define SPDIF_CTRL (0x0)
-#define SPDIF_INT_REG (0x4)
-#define SPDIF_FIFO_CTRL (0x8)
-#define SPDIF_STAT_REG (0xC)
-
-#define SPDIF_FIFO_ADDR (0x100)
-#define DMAC_SPDIF_POLLING_LEN (256)
-
-///ctrl: sampled on the rising clock edge
-#define SPDIF_TSAMPLERATE 0///[SRATEW-1:0]
-#define SPDIF_SFR_ENABLE (1<<8) ///0:SFR reg reset to defualt value; auto set back to '1' after reset
-#define SPDIF_ENABLE (1<<9) ///0:reset of SPDIF block, SRF bits are unchanged; 1:enables SPDIF module
-#define SPDIF_FIFO_ENABLE (1<<10) ///0:FIFO pointers are reset to zero,threshold levels for FIFO are unchaned; auto set back to '1'
-#define SPDIF_CLK_ENABLE (1<<11) ///1:blocked and the modules are in power save mode; 0:block feeds the modules
-#define SPDIF_TR_MODE (1<<12) ///0:rx; 1:tx
-#define SPDIF_PARITCHECK (1<<13) ///0:party bit rx in a sub-frame is repeated on the parity; 1:check on a parity error
-#define SPDIF_PARITYGEN (1<<14) ///0:parity bit from FIFO is transmitted in sub-frame;1:parity bit generated inside the core and added to a transmitted sub-frame
-#define SPDIF_VALIDITYCHECK (1<<15) ///0:validity bit in frame isn't checked and all frame are written; 1:validity bit rx is checked
-#define SPDIF_CHANNEL_MODE (1<<16) ///0:two-channel; 1:single-channel
-#define SPDIF_DUPLICATE (1<<17) ///only tx -single-channel mode; 0:secondary channel; 1: left(primary) channel
-#define SPDIF_SETPREAMBB (1<<18) ///only tx; 0:first preamble B after reset tx valid sub-frame; 1:first preamble B is tx after preambleddel(INT_REG)
-#define SPDIF_USE_FIFO_IF (1<<19) ///0:FIFO disabled ,APB accese FIFO; 1:FIFO enable, APB access to FIFO disable;
-///#define RESERVED (1<<20)
+#define SPDIF_CTRL 0x0
+#define SPDIF_INT_REG 0x4
+#define SPDIF_FIFO_CTRL 0x8
+#define SPDIF_STAT_REG 0xC
+
+#define SPDIF_FIFO_ADDR 0x100
+#define DMAC_SPDIF_POLLING_LEN 256
+
+/* ctrl: sampled on the rising clock edge */
+#define SPDIF_TSAMPLERATE 0 /* [SRATEW-1:0] */
+#define SPDIF_SFR_ENABLE (1<<8) /* 0:SFR reg reset to defualt value; auto set back to '1' after reset */
+#define SPDIF_ENABLE (1<<9) /* 0:reset of SPDIF block, SRF bits are unchanged; 1:enables SPDIF module */
+#define SPDIF_FIFO_ENABLE (1<<10) /* 0:FIFO pointers are reset to zero,threshold levels for FIFO are unchaned; auto set back to '1' */
+#define SPDIF_CLK_ENABLE (1<<11) /* 1:blocked and the modules are in power save mode; 0:block feeds the modules */
+#define SPDIF_TR_MODE (1<<12) /* 0:rx; 1:tx */
+#define SPDIF_PARITCHECK (1<<13) /* 0:party bit rx in a sub-frame is repeated on the parity; 1:check on a parity error */
+#define SPDIF_PARITYGEN (1<<14) /* 0:parity bit from FIFO is transmitted in sub-frame;1:parity bit generated inside the core and added to a transmitted sub-frame */
+#define SPDIF_VALIDITYCHECK (1<<15) /* 0:validity bit in frame isn't checked and all frame are written; 1:validity bit rx is checked */
+#define SPDIF_CHANNEL_MODE (1<<16) /* 0:two-channel; 1:single-channel */
+#define SPDIF_DUPLICATE (1<<17) /* only tx -single-channel mode; 0:secondary channel; 1: left(primary) channel */
+#define SPDIF_SETPREAMBB (1<<18) /* only tx; 0:first preamble B after reset tx valid sub-frame; 1:first preamble B is tx after preambleddel(INT_REG) */
+#define SPDIF_USE_FIFO_IF (1<<19) /* 0:FIFO disabled ,APB accese FIFO; 1:FIFO enable, APB access to FIFO disable; */
#define SPDIF_PARITY_MASK (1<<21)
#define SPDIF_UNDERR_MASK (1<<22)
#define SPDIF_OVRERR_MASK (1<<23)
#define SPDIF_BEGIN_MASK (1<<30)
#define SPDIF_INTEREQ_MAKS (1<<31)
-#define SPDIF_MASK_ENABLE (SPDIF_PARITY_MASK | SPDIF_UNDERR_MASK | SPDIF_OVRERR_MASK | SPDIF_EMPTY_MASK | \
- SPDIF_AEMPTY_MASK | SPDIF_FULL_MASK | SPDIF_AFULL_MASK | SPDIF_SYNCERR_MASK | \
- SPDIF_LOCK_MASK | SPDIF_BEGIN_MASK | SPDIF_INTEREQ_MAKS)
-
-#define SPDIF_MASK_FIFO (SPDIF_EMPTY_MASK | SPDIF_AEMPTY_MASK | SPDIF_FULL_MASK | SPDIF_AFULL_MASK)
-
-////INT_REG
-#define SPDIF_RSAMPLERATE 0 ///[SRATEW-1:0]
-#define SPDIF_PREAMBLEDEL 8 ///[PDELAYW+7:8] first B delay
-#define SPDIF_PARITYO (1<<21) ///0:clear parity error
-#define SPDIF_TDATA_UNDERR (1<<22) ///tx data underrun error;0:clear
-#define SPDIF_RDATA_OVRERR (1<<23) ///rx data overrun error; 0:clear
-#define SPDIF_FIFO_EMPTY (1<<24) ///empty; 0:clear
-#define SPDIF_FIOF_AEMPTY (1<<25) ///almost empty; 0:clear
-#define SPDIF_FIFO_FULL (1<<26) ///FIFO full; 0:clear
-#define SPDIF_FIFO_AFULL (1<<27) ///FIFO almost full; 0:clear
-#define SPDIF_SYNCERR (1<<28) ///sync error; 0:clear
-#define SPDIF_LOCK (1<<29) ///sync; 0:clear
-#define SPDIF_BLOCK_BEGIN (1<<30) ///new start block rx data
-
-#define SPDIF_INT_REG_BIT (SPDIF_PARITYO | SPDIF_TDATA_UNDERR | SPDIF_RDATA_OVRERR | SPDIF_FIFO_EMPTY | \
- SPDIF_FIOF_AEMPTY | SPDIF_FIFO_FULL | SPDIF_FIFO_AFULL | SPDIF_SYNCERR | \
- SPDIF_LOCK | SPDIF_BLOCK_BEGIN)
+#define SPDIF_MASK_ENABLE (SPDIF_PARITY_MASK | SPDIF_UNDERR_MASK | \
+ SPDIF_OVRERR_MASK | SPDIF_EMPTY_MASK | \
+ SPDIF_AEMPTY_MASK | SPDIF_FULL_MASK | \
+ SPDIF_AFULL_MASK | SPDIF_SYNCERR_MASK | \
+ SPDIF_LOCK_MASK | SPDIF_BEGIN_MASK | \
+ SPDIF_INTEREQ_MAKS)
+
+#define SPDIF_MASK_FIFO (SPDIF_EMPTY_MASK | SPDIF_AEMPTY_MASK | \
+ SPDIF_FULL_MASK | SPDIF_AFULL_MASK)
+
+/* INT_REG */
+#define SPDIF_RSAMPLERATE 0 /* [SRATEW-1:0] */
+#define SPDIF_PREAMBLEDEL 8 /* [PDELAYW+7:8] first B delay */
+#define SPDIF_PARITYO (1<<21) /* 0:clear parity error */
+#define SPDIF_TDATA_UNDERR (1<<22) /* tx data underrun error;0:clear */
+#define SPDIF_RDATA_OVRERR (1<<23) /* rx data overrun error; 0:clear */
+#define SPDIF_FIFO_EMPTY (1<<24) /* empty; 0:clear */
+#define SPDIF_FIOF_AEMPTY (1<<25) /* almost empty; 0:clear */
+#define SPDIF_FIFO_FULL (1<<26) /* FIFO full; 0:clear */
+#define SPDIF_FIFO_AFULL (1<<27) /* FIFO almost full; 0:clear */
+#define SPDIF_SYNCERR (1<<28) /* sync error; 0:clear */
+#define SPDIF_LOCK (1<<29) /* sync; 0:clear */
+#define SPDIF_BLOCK_BEGIN (1<<30) /* new start block rx data */
+
+#define SPDIF_INT_REG_BIT (SPDIF_PARITYO | SPDIF_TDATA_UNDERR | \
+ SPDIF_RDATA_OVRERR | SPDIF_FIFO_EMPTY | \
+ SPDIF_FIOF_AEMPTY | SPDIF_FIFO_FULL | \
+ SPDIF_FIFO_AFULL | SPDIF_SYNCERR | \
+ SPDIF_LOCK | SPDIF_BLOCK_BEGIN)
-#define SPDIF_ERROR_INT_STATUS (SPDIF_PARITYO | SPDIF_TDATA_UNDERR | SPDIF_RDATA_OVRERR)
-#define SPDIF_FIFO_INT_STATUS (SPDIF_FIFO_EMPTY | SPDIF_FIOF_AEMPTY | SPDIF_FIFO_FULL | SPDIF_FIFO_AFULL)
+#define SPDIF_ERROR_INT_STATUS (SPDIF_PARITYO | \
+ SPDIF_TDATA_UNDERR | SPDIF_RDATA_OVRERR)
+#define SPDIF_FIFO_INT_STATUS (SPDIF_FIFO_EMPTY | SPDIF_FIOF_AEMPTY | \
+ SPDIF_FIFO_FULL | SPDIF_FIFO_AFULL)
#define SPDIF_INT_PARITY_ERROR (-1)
#define SPDIF_INT_TDATA_UNDERR (-2)
#define SPDIF_INT_RDATA_OVRERR (-3)
#define SPDIF_INT_FIFO_EMPTY 1
#define SPDIF_INT_FIFO_AEMPTY 2
-#define SPDIF_INT_FIFO_FULL 3
+#define SPDIF_INT_FIFO_FULL 3
#define SPDIF_INT_FIFO_AFULL 4
-#define SPDIF_INT_SYNCERR (-4)
-#define SPDIF_INT_LOCK 5 ///reciever has become synchronized with input data stream
-#define SPDIF_INT_BLOCK_BEGIN 6 ///start a new block in recieve data, written into FIFO
+#define SPDIF_INT_SYNCERR (-4)
+#define SPDIF_INT_LOCK 5 /* reciever has become synchronized with input data stream */
+#define SPDIF_INT_BLOCK_BEGIN 6 /* start a new block in recieve data, written into FIFO */
-///FIFO_CTRL
-#define SPDIF_AEMPTY_THRESHOLD 0///[depth-1:0]
-#define SPDIF_AFULL_THRESHOLD 16///[depth+15:16]
+/* FIFO_CTRL */
+#define SPDIF_AEMPTY_THRESHOLD 0 /* [depth-1:0] */
+#define SPDIF_AFULL_THRESHOLD 16 /* [depth+15:16] */
-///STAT_REG
+/* STAT_REG */
#define SPDIF_FIFO_LEVEL (1<<0)
-#define SPDIF_PARITY_FLAG (1<<21) ///1:error; 0:repeated
-#define SPDIF_UNDERR_FLAG (1<<22) ///1:error
-#define SPDIF_OVRERR_FLAG (1<<23) ///1:error
-#define SPDIF_EMPTY_FLAG (1<<24) ///1:fifo empty
-#define SPDIF_AEMPTY_FLAG (1<<25) ///1:fifo almost empty
-#define SPDIF_FULL_FLAG (1<<26) ///1:fifo full
-#define SPDIF_AFULL_FLAG (1<<27) ///1:fifo almost full
-#define SPDIF_SYNCERR_FLAG (1<<28) ///1:rx sync error
-#define SPDIF_LOCK_FLAG (1<<29) ///1:RX sync
-#define SPDIF_BEGIN_FLAG (1<<30) ///1:start a new block
-#define SPDIF_RIGHT_LEFT (1<<31) ///1:left channel received and tx into FIFO; 0:right channel received and tx into FIFO
-
-#define SPDIF_STAT (SPDIF_PARITY_FLAG | SPDIF_UNDERR_FLAG | SPDIF_OVRERR_FLAG | SPDIF_EMPTY_FLAG | \
- SPDIF_AEMPTY_FLAG | SPDIF_FULL_FLAG | SPDIF_AFULL_FLAG | SPDIF_SYNCERR_FLAG | \
- SPDIF_LOCK_FLAG | SPDIF_BEGIN_FLAG | SPDIF_RIGHT_LEFT)
+#define SPDIF_PARITY_FLAG (1<<21) /* 1:error; 0:repeated */
+#define SPDIF_UNDERR_FLAG (1<<22) /* 1:error */
+#define SPDIF_OVRERR_FLAG (1<<23) /* 1:error */
+#define SPDIF_EMPTY_FLAG (1<<24) /* 1:fifo empty */
+#define SPDIF_AEMPTY_FLAG (1<<25) /* 1:fifo almost empty */
+#define SPDIF_FULL_FLAG (1<<26) /* 1:fifo full */
+#define SPDIF_AFULL_FLAG (1<<27) /* 1:fifo almost full */
+#define SPDIF_SYNCERR_FLAG (1<<28) /* 1:rx sync error */
+#define SPDIF_LOCK_FLAG (1<<29) /* 1:RX sync */
+#define SPDIF_BEGIN_FLAG (1<<30) /* 1:start a new block */
+#define SPDIF_RIGHT_LEFT (1<<31) /* 1:left channel received and tx into FIFO; 0:right channel received and tx into FIFO */
+
+#define BIT8TO20MASK 0x1FFF
+#define ALLBITMASK 0xFFFFFFFF
+
+#define SPDIF_STAT (SPDIF_PARITY_FLAG | SPDIF_UNDERR_FLAG | \
+ SPDIF_OVRERR_FLAG | SPDIF_EMPTY_FLAG | \
+ SPDIF_AEMPTY_FLAG | SPDIF_FULL_FLAG | \
+ SPDIF_AFULL_FLAG | SPDIF_SYNCERR_FLAG | \
+ SPDIF_LOCK_FLAG | SPDIF_BEGIN_FLAG | \
+ SPDIF_RIGHT_LEFT)
struct sf_spdif_dev {
void __iomem *spdif_base;
struct regmap *regmap;
bool *period_elapsed, snd_pcm_format_t format);
snd_pcm_format_t format;
- //unsigned int sample_bits;
unsigned int tx_ptr;
unsigned int rx_ptr;
struct clk* spdif_apb;
struct clk* spdif_core;
- struct clk* audioclk;
+ struct clk* apb0_clk;
+ struct clk* audio_root;
+ struct clk* mclk_inner;
struct reset_control *rst_apb;
struct snd_dmaengine_dai_dma_data dma_data;
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct sf_spdif_dev *dev = runtime->private_data;
- int ret;
switch (params_channels(hw_params)) {
case 2:
projects / platform / kernel / linux-starfive.git / commitdiff