+2007-07-13 David Edelsohn <edelsohn@gnu.org>
+
+ * config/rs6000/spe.md (SPE_ACC_REGNO): Delete definition.
+ (SPEFSCR_REGNO): Delete definition.
+ * config/rs6000/rs6000.c: LINK_REGISTER_REGNUM -> LR_REGNO.
+ COUNT_REGISTER_REGNUM -> CTR_REGNO.
+ * config/rs6000/rs6000.h: Do not define *_REGNO.
+ LINK_REGISTER_REGNUM -> LR_REGNO.
+ COUNT_REGISTER_REGNUM -> CTR_REGNO.
+ * config/rs6000/predicates.md: LINK_REGISTER_REGNUM -> LR_REGNO.
+ COUNT_REGISTER_REGNUM -> CTR_REGNO.
+ * config/rs6000/linux-unwind.h: Define R_LR, R_CR2, R_VR0,
+ R_VRSAVE, R_VSCR. Use them.
+ * config/rs6000/darwin-fallback.c: Define R_LR, R_CTR, R_CR2,
+ R_XER, R_VR0, R_VRSAVE, R_VSCR, R_SPEFSCR. Use them.
+ * config/rs6000/rs6000.md: Define REGNO constants. Use them.
+ * config/rs6000/aix.h: Define R_LR. Use it.
+
2007-07-13 Caroline Tice <ctice@apple.com>
* toplev.c (process_options): Turn flag_var_tracking_uninit off when
code that does the save/restore is generated by the linker, so
we have no good way to determine at compile time what to do. */
+#define R_LR 65
+
#ifdef __64BIT__
#define MD_FROB_UPDATE_CONTEXT(CTX, FS) \
do { \
{ \
unsigned int *insn \
= (unsigned int *) \
- _Unwind_GetGR ((CTX), LINK_REGISTER_REGNUM); \
+ _Unwind_GetGR ((CTX), R_LR); \
if (*insn == 0xE8410028) \
_Unwind_SetGRPtr ((CTX), 2, (CTX)->cfa + 40); \
} \
{ \
unsigned int *insn \
= (unsigned int *) \
- _Unwind_GetGR ((CTX), LINK_REGISTER_REGNUM); \
+ _Unwind_GetGR ((CTX), R_LR); \
if (*insn == 0x80410014) \
_Unwind_SetGRPtr ((CTX), 2, (CTX)->cfa + 20); \
} \
#include <sys/types.h>
#include <signal.h>
+#define R_LR 65
+#define R_CTR 66
+#define R_CR2 70
+#define R_XER 76
+#define R_VR0 77
+#define R_VRSAVE 109
+#define R_VSCR 110
+#define R_SPEFSCR 112
+
typedef unsigned long reg_unit;
/* Place in GPRS the parameters to the first 'sc' instruction that would
new_cfa = m64->gpr[1][1];
- set_offset (CR2_REGNO, &m64->cr);
+ set_offset (R_CR2, &m64->cr);
for (i = 0; i < 32; i++)
set_offset (i, m64->gpr[i] + 1);
- set_offset (XER_REGNO, m64->xer + 1);
- set_offset (LINK_REGISTER_REGNUM, m64->lr + 1);
- set_offset (COUNT_REGISTER_REGNUM, m64->ctr + 1);
+ set_offset (R_XER, m64->xer + 1);
+ set_offset (R_LR, m64->lr + 1);
+ set_offset (R_CTR, m64->ctr + 1);
if (is_vector)
- set_offset (VRSAVE_REGNO, &m64->vrsave);
+ set_offset (R_VRSAVE, &m64->vrsave);
/* Sometimes, srr0 points to the instruction that caused the exception,
and sometimes to the next instruction to be executed; we want
new_cfa = m->gpr[1];
- set_offset (CR2_REGNO, &m->cr);
+ set_offset (R_CR2, &m->cr);
for (i = 0; i < 32; i++)
set_offset (i, m->gpr + i);
- set_offset (XER_REGNO, &m->xer);
- set_offset (LINK_REGISTER_REGNUM, &m->lr);
- set_offset (COUNT_REGISTER_REGNUM, &m->ctr);
+ set_offset (R_XER, &m->xer);
+ set_offset (R_LR, &m->lr);
+ set_offset (R_CTR, &m->ctr);
if (is_vector)
- set_offset (VRSAVE_REGNO, &m->vrsave);
+ set_offset (R_VRSAVE, &m->vrsave);
/* Sometimes, srr0 points to the instruction that caused the exception,
and sometimes to the next instruction to be executed; we want
for (i = 0; i < 32; i++)
set_offset (32 + i, float_vector_state->fpregs + i);
- set_offset (SPEFSCR_REGNO, &float_vector_state->fpscr);
+ set_offset (R_SPEFSCR, &float_vector_state->fpscr);
if (is_vector)
{
for (i = 0; i < 32; i++)
- set_offset (FIRST_ALTIVEC_REGNO + i, float_vector_state->save_vr + i);
- set_offset (VSCR_REGNO, float_vector_state->save_vscr);
+ set_offset (R_VR0 + i, float_vector_state->save_vr + i);
+ set_offset (R_VSCR, float_vector_state->save_vscr);
}
return true;
/* DWARF2 EH unwinding support for PowerPC and PowerPC64 Linux.
- Copyright (C) 2004, 2005, 2006 Free Software Foundation, Inc.
+ Copyright (C) 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
This file is part of GCC.
these structs elsewhere; Many fields are missing, particularly
from the end of the structures. */
+#define R_LR 65
+#define R_CR2 70
+#define R_VR0 77
+#define R_VRSAVE 109
+#define R_VSCR 110
+
struct gcc_vregs
{
__attribute__ ((vector_size (16))) int vr[32];
fs->regs.reg[i].loc.offset = (long) ®s->gpr[i] - new_cfa;
}
- fs->regs.reg[CR2_REGNO].how = REG_SAVED_OFFSET;
- fs->regs.reg[CR2_REGNO].loc.offset = (long) ®s->ccr - new_cfa;
+ fs->regs.reg[R_CR2].how = REG_SAVED_OFFSET;
+ fs->regs.reg[R_CR2].loc.offset = (long) ®s->ccr - new_cfa;
- fs->regs.reg[LINK_REGISTER_REGNUM].how = REG_SAVED_OFFSET;
- fs->regs.reg[LINK_REGISTER_REGNUM].loc.offset = (long) ®s->link - new_cfa;
+ fs->regs.reg[R_LR].how = REG_SAVED_OFFSET;
+ fs->regs.reg[R_LR].loc.offset = (long) ®s->link - new_cfa;
fs->regs.reg[ARG_POINTER_REGNUM].how = REG_SAVED_OFFSET;
fs->regs.reg[ARG_POINTER_REGNUM].loc.offset = (long) ®s->nip - new_cfa;
{
for (i = 0; i < 32; i++)
{
- fs->regs.reg[i + FIRST_ALTIVEC_REGNO].how = REG_SAVED_OFFSET;
- fs->regs.reg[i + FIRST_ALTIVEC_REGNO].loc.offset
+ fs->regs.reg[i + R_VR0].how = REG_SAVED_OFFSET;
+ fs->regs.reg[i + R_VR0].loc.offset
= (long) &vregs[i] - new_cfa;
}
- fs->regs.reg[VSCR_REGNO].how = REG_SAVED_OFFSET;
- fs->regs.reg[VSCR_REGNO].loc.offset = (long) &vregs->vscr - new_cfa;
+ fs->regs.reg[R_VSCR].how = REG_SAVED_OFFSET;
+ fs->regs.reg[R_VSCR].loc.offset = (long) &vregs->vscr - new_cfa;
}
- fs->regs.reg[VRSAVE_REGNO].how = REG_SAVED_OFFSET;
- fs->regs.reg[VRSAVE_REGNO].loc.offset = (long) &vregs->vsave - new_cfa;
+ fs->regs.reg[R_VRSAVE].how = REG_SAVED_OFFSET;
+ fs->regs.reg[R_VRSAVE].loc.offset = (long) &vregs->vsave - new_cfa;
}
/* If we have SPE register high-parts... we check at compile-time to
code that does the save/restore is generated by the linker, so
we have no good way to determine at compile time what to do. */
unsigned int *insn
- = (unsigned int *) _Unwind_GetGR (context, LINK_REGISTER_REGNUM);
+ = (unsigned int *) _Unwind_GetGR (context, R_LR);
if (*insn == 0xE8410028)
_Unwind_SetGRPtr (context, 2, context->cfa + 40);
}
;; Return 1 if op is COUNT register.
(define_predicate "count_register_operand"
(and (match_code "reg")
- (match_test "REGNO (op) == COUNT_REGISTER_REGNUM
+ (match_test "REGNO (op) == CTR_REGNO
|| REGNO (op) > LAST_VIRTUAL_REGISTER")))
;; Return 1 if op is an Altivec register.
;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
(define_predicate "call_operand"
(if_then_else (match_code "reg")
- (match_test "REGNO (op) == LINK_REGISTER_REGNUM
- || REGNO (op) == COUNT_REGISTER_REGNUM
+ (match_test "REGNO (op) == LR_REGNO
+ || REGNO (op) == CTR_REGNO
|| REGNO (op) >= FIRST_PSEUDO_REGISTER")
(match_code "symbol_ref")))
first = emit_insn (gen_load_toc_v4_PIC_1b (gsym));
emit_move_insn (tmp1,
- gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
+ gen_rtx_REG (Pmode, LR_REGNO));
emit_move_insn (tmp2, mem);
emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
last = emit_move_insn (got, tmp3);
case 'T':
/* Print the symbolic name of a branch target register. */
- if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
- && REGNO (x) != COUNT_REGISTER_REGNUM))
+ if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
+ && REGNO (x) != CTR_REGNO))
output_operand_lossage ("invalid %%T value");
- else if (REGNO (x) == LINK_REGISTER_REGNUM)
+ else if (REGNO (x) == LR_REGNO)
fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
else
fputs ("ctr", file);
|| rs6000_ra_ever_killed ())
{
info_ptr->lr_save_p = 1;
- df_set_regs_ever_live (LINK_REGISTER_REGNUM, true);
+ df_set_regs_ever_live (LR_REGNO, true);
}
/* Determine if we need to save the condition code registers. */
}
cfun->machine->ra_need_lr = 1;
- return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
+ return get_hard_reg_initial_val (Pmode, LR_REGNO);
}
/* Say whether a function is a candidate for sibcall handling or not.
push_topmost_sequence ();
top = get_insns ();
pop_topmost_sequence ();
- reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
+ reg = gen_rtx_REG (Pmode, LR_REGNO);
for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
{
if (!SIBLING_CALL_P (insn))
return 1;
}
- else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM))
+ else if (find_regno_note (insn, REG_INC, LR_REGNO))
return 1;
else if (set_of (reg, insn) != NULL_RTX
&& !prologue_epilogue_contains (insn))
}
emit_insn (gen_load_toc_v4_PIC_1 (lab));
emit_move_insn (tmp1,
- gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
+ gen_rtx_REG (Pmode, LR_REGNO));
emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
}
else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
{
emit_insn (gen_load_toc_v4_pic_si ());
- emit_move_insn (dest, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
+ emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
}
else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
{
emit_insn (gen_load_toc_v4_PIC_1 (symF));
emit_move_insn (dest,
- gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
+ gen_rtx_REG (Pmode, LR_REGNO));
emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
}
else
tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
emit_insn (gen_load_toc_v4_PIC_1b (tocsym));
emit_move_insn (dest,
- gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
+ gen_rtx_REG (Pmode, LR_REGNO));
emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
}
emit_insn (gen_addsi3 (dest, temp0, dest));
emit_move_insn (tmp, operands[0]);
}
else
- emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
+ emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
}
static GTY(()) int set = -1;
if (info->lr_save_p)
{
insn = emit_move_insn (reg0,
- gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
+ gen_rtx_REG (Pmode, LR_REGNO));
RTX_FRAME_RELATED_P (insn) = 1;
}
j = 0;
RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
gen_rtx_REG (SImode,
- LINK_REGISTER_REGNUM));
+ LR_REGNO));
RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
gen_rtx_SYMBOL_REF (Pmode,
"*save_world"));
rtx addr, reg, mem;
insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
- gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
+ gen_rtx_REG (Pmode, LR_REGNO));
RTX_FRAME_RELATED_P (insn) = 1;
addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
gen_rtx_REG (Pmode,
- LINK_REGISTER_REGNUM));
+ LR_REGNO));
sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
alloc_rname = ggc_strdup (rname);
&& EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
if (save_LR_around_toc_setup)
{
- rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
+ rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
insn = emit_move_insn (frame_ptr_rtx, lr);
RTX_FRAME_RELATED_P (insn) = 1;
if (DEFAULT_ABI == ABI_DARWIN
&& flag_pic && current_function_uses_pic_offset_table)
{
- rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
+ rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
rtx src = machopic_function_base_sym ();
/* Save and restore LR locally around this call (in R0). */
RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
gen_rtx_REG (Pmode,
- LINK_REGISTER_REGNUM));
+ LR_REGNO));
RTVEC_ELT (p, j++)
= gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
/* The instruction pattern requires a clobber here;
/* Set LR here to try to overlap restores below. */
if (info->lr_save_p)
- emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
+ emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
gen_rtx_REG (Pmode, 0));
/* Load exception handler data registers, if needed. */
RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
gen_rtx_REG (Pmode,
- LINK_REGISTER_REGNUM));
+ LR_REGNO));
/* If we have to restore more than two FP registers, branch to the
restore function. It will return to our caller. */
gen_rtx_USE (VOIDmode, const0_rtx),
gen_rtx_USE (VOIDmode,
gen_rtx_REG (SImode,
- LINK_REGISTER_REGNUM)),
+ LR_REGNO)),
gen_rtx_RETURN (VOIDmode))));
SIBLING_CALL_P (insn) = 1;
emit_barrier ();
else if (DEFAULT_ABI == ABI_DARWIN)
{
const char *mcount_name = RS6000_MCOUNT;
- int caller_addr_regno = LINK_REGISTER_REGNUM;
+ int caller_addr_regno = LR_REGNO;
/* Be conservative and always set this, at least for now. */
current_function_uses_pic_offset_table = 1;
return regno;
if (regno == MQ_REGNO)
return 100;
- if (regno == LINK_REGISTER_REGNUM)
+ if (regno == LR_REGNO)
return 108;
- if (regno == COUNT_REGISTER_REGNUM)
+ if (regno == CTR_REGNO)
return 109;
if (CR_REGNO_P (regno))
return regno - CR0_REGNO + 86;
, 0, 0, 0 \
}
-#define MQ_REGNO 64
-#define CR0_REGNO 68
-#define CR1_REGNO 69
-#define CR2_REGNO 70
-#define CR3_REGNO 71
-#define CR4_REGNO 72
-#define MAX_CR_REGNO 75
-#define XER_REGNO 76
-#define FIRST_ALTIVEC_REGNO 77
-#define LAST_ALTIVEC_REGNO 108
#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
-#define VRSAVE_REGNO 109
-#define VSCR_REGNO 110
-#define SPE_ACC_REGNO 111
-#define SPEFSCR_REGNO 112
#define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
#define FIRST_SAVED_FP_REGNO (14+32)
#define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
/* True if register is a condition register. */
-#define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
+#define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
/* True if register is a condition register, but not cr0. */
-#define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
+#define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
/* True if register is an integer register. */
#define INT_REGNO_P(N) \
/* Place to put static chain when calling a function that requires it. */
#define STATIC_CHAIN_REGNUM 11
-/* Link register number. */
-#define LINK_REGISTER_REGNUM 65
-
-/* Count register number. */
-#define COUNT_REGISTER_REGNUM 66
\f
/* Define the classes of registers for register constraints in the
machine description. Also define ranges of constants.
: (REGNO) == CR0_REGNO ? CR0_REGS \
: CR_REGNO_P (REGNO) ? CR_REGS \
: (REGNO) == MQ_REGNO ? MQ_REGS \
- : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
- : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
+ : (REGNO) == LR_REGNO ? LINK_REGS \
+ : (REGNO) == CTR_REGNO ? CTR_REGS \
: (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
: (REGNO) == XER_REGNO ? XER_REGS \
: (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
needed. */
#define EPILOGUE_USES(REGNO) \
- ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
+ ((reload_completed && (REGNO) == LR_REGNO) \
|| (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
|| (current_function_calls_eh_return \
&& TARGET_AIX \
dwarf2 unwind information. This also enables the table driven
mechanism. */
-#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
-#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
+#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
+#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
/* Describe how we implement __builtin_eh_return. */
#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
;;
+;; REGNOS
+;;
+
+(define_constants
+ [(MQ_REGNO 64)
+ (LR_REGNO 65)
+ (CTR_REGNO 66)
+ (CR0_REGNO 68)
+ (CR1_REGNO 69)
+ (CR2_REGNO 70)
+ (CR3_REGNO 71)
+ (CR4_REGNO 72)
+ (CR5_REGNO 73)
+ (CR6_REGNO 74)
+ (CR7_REGNO 75)
+ (MAX_CR_REGNO 75)
+ (XER_REGNO 76)
+ (FIRST_ALTIVEC_REGNO 77)
+ (LAST_ALTIVEC_REGNO 108)
+ (VRSAVE_REGNO 109)
+ (VSCR_REGNO 110)
+ (SPE_ACC_REGNO 111)
+ (SPEFSCR_REGNO 112)
+ (SFP_REGNO 113)
+ ])
+
+;;
;; UNSPEC usage
;;
(lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
(sign_extend:DI (reg:SI 4)))
(const_int 32))))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __mulh"
[(set_attr "type" "imul")])
[(set (reg:DI 3)
(mult:DI (sign_extend:DI (reg:SI 3))
(sign_extend:DI (reg:SI 4))))
- (clobber (reg:SI 65))
+ (clobber (reg:SI LR_REGNO))
(clobber (reg:SI 0))]
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __mull"
(div:SI (reg:SI 3) (reg:SI 4)))
(set (reg:SI 4)
(mod:SI (reg:SI 3) (reg:SI 4)))
- (clobber (reg:SI 65))
+ (clobber (reg:SI LR_REGNO))
(clobber (reg:SI 0))]
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __divss"
(udiv:SI (reg:SI 3) (reg:SI 4)))
(set (reg:SI 4)
(umod:SI (reg:SI 3) (reg:SI 4)))
- (clobber (reg:SI 65))
+ (clobber (reg:SI LR_REGNO))
(clobber (reg:SI 0))
(clobber (match_scratch:CC 0 "=x"))
- (clobber (reg:CC 69))]
+ (clobber (reg:CC CR1_REGNO))]
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __divus"
[(set_attr "type" "idiv")])
(define_insn "quoss_call"
[(set (reg:SI 3)
(div:SI (reg:SI 3) (reg:SI 4)))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __quoss"
[(set_attr "type" "idiv")])
(define_insn "quous_call"
[(set (reg:SI 3)
(udiv:SI (reg:SI 3) (reg:SI 4)))
- (clobber (reg:SI 65))
+ (clobber (reg:SI LR_REGNO))
(clobber (reg:SI 0))
(clobber (match_scratch:CC 0 "=x"))
- (clobber (reg:CC 69))]
+ (clobber (reg:CC CR1_REGNO))]
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __quous"
[(set_attr "type" "idiv")])
[(set_attr "type" "load")])
(define_insn "load_toc_v4_pic_si"
- [(set (reg:SI 65)
+ [(set (reg:SI LR_REGNO)
(unspec:SI [(const_int 0)] UNSPEC_TOC))]
"DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
"bl _GLOBAL_OFFSET_TABLE_@local-4"
(set_attr "length" "4")])
(define_insn "load_toc_v4_PIC_1"
- [(set (reg:SI 65)
+ [(set (reg:SI LR_REGNO)
(match_operand:SI 0 "immediate_operand" "s"))
(use (unspec [(match_dup 0)] UNSPEC_TOC))]
"TARGET_ELF && DEFAULT_ABI != ABI_AIX
(set_attr "length" "4")])
(define_insn "load_toc_v4_PIC_1b"
- [(set (reg:SI 65)
+ [(set (reg:SI LR_REGNO)
(unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
UNSPEC_TOCPTR))]
"TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
emit_insn (gen_load_macho_picbase (tmplabrtx));
- emit_move_insn (picreg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
+ emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
}
else
(use (reg:SI 11))
(set (reg:SI 2)
(mem:SI (plus:SI (reg:SI 1) (const_int 20))))
- (clobber (reg:SI 65))])]
+ (clobber (reg:SI LR_REGNO))])]
"TARGET_32BIT"
"
{ operands[2] = gen_reg_rtx (SImode); }")
(use (reg:DI 11))
(set (reg:DI 2)
(mem:DI (plus:DI (reg:DI 1) (const_int 40))))
- (clobber (reg:SI 65))])]
+ (clobber (reg:SI LR_REGNO))])]
"TARGET_64BIT"
"
{ operands[2] = gen_reg_rtx (DImode); }")
(use (reg:SI 11))
(set (reg:SI 2)
(mem:SI (plus:SI (reg:SI 1) (const_int 20))))
- (clobber (reg:SI 65))])]
+ (clobber (reg:SI LR_REGNO))])]
"TARGET_32BIT"
"
{ operands[3] = gen_reg_rtx (SImode); }")
(use (reg:DI 11))
(set (reg:DI 2)
(mem:DI (plus:DI (reg:DI 1) (const_int 40))))
- (clobber (reg:SI 65))])]
+ (clobber (reg:SI LR_REGNO))])]
"TARGET_64BIT"
"
{ operands[3] = gen_reg_rtx (DImode); }")
[(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
- (clobber (reg:SI 65))])]
+ (clobber (reg:SI LR_REGNO))])]
""
"
{
operands[1]),
gen_rtx_USE (VOIDmode, operands[2]),
gen_rtx_CLOBBER (VOIDmode,
- gen_rtx_REG (Pmode,
- LINK_REGISTER_REGNUM)));
+ gen_rtx_REG (Pmode, LR_REGNO)));
call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
DONE;
(call (mem:SI (match_operand 1 "address_operand" ""))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
- (clobber (reg:SI 65))])]
+ (clobber (reg:SI LR_REGNO))])]
""
"
{
operands[2])),
gen_rtx_USE (VOIDmode, operands[3]),
gen_rtx_CLOBBER (VOIDmode,
- gen_rtx_REG (Pmode,
- LINK_REGISTER_REGNUM)));
+ gen_rtx_REG (Pmode, LR_REGNO)));
call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
DONE;
[(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
(match_operand 1 "" "g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"(INTVAL (operands[2]) & CALL_LONG) == 0"
"*
{
[(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
(match_operand 1 "" "g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
"*
{
(call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
(match_operand 2 "" "g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"(INTVAL (operands[3]) & CALL_LONG) == 0"
"*
{
(call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
(match_operand 2 "" "g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
"*
{
(use (reg:SI 11))
(set (reg:SI 2)
(mem:SI (plus:SI (reg:SI 1) (const_int 20))))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
"b%T0l\;{l|lwz} 2,20(1)"
[(set_attr "type" "jmpreg")
[(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
(match_operand 1 "" "g"))
(use (match_operand:SI 2 "immediate_operand" "O"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_32BIT
&& DEFAULT_ABI == ABI_AIX
&& (INTVAL (operands[2]) & CALL_LONG) == 0"
(use (reg:DI 11))
(set (reg:DI 2)
(mem:DI (plus:DI (reg:DI 1) (const_int 40))))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
"b%T0l\;ld 2,40(1)"
[(set_attr "type" "jmpreg")
[(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
(match_operand 1 "" "g"))
(use (match_operand:SI 2 "immediate_operand" "O"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_64BIT
&& DEFAULT_ABI == ABI_AIX
&& (INTVAL (operands[2]) & CALL_LONG) == 0"
(use (reg:SI 11))
(set (reg:SI 2)
(mem:SI (plus:SI (reg:SI 1) (const_int 20))))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
"b%T1l\;{l|lwz} 2,20(1)"
[(set_attr "type" "jmpreg")
(call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
(match_operand 2 "" "g")))
(use (match_operand:SI 3 "immediate_operand" "O"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_32BIT
&& DEFAULT_ABI == ABI_AIX
&& (INTVAL (operands[3]) & CALL_LONG) == 0"
(use (reg:DI 11))
(set (reg:DI 2)
(mem:DI (plus:DI (reg:DI 1) (const_int 40))))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
"b%T1l\;ld 2,40(1)"
[(set_attr "type" "jmpreg")
(call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
(match_operand 2 "" "g")))
(use (match_operand:SI 3 "immediate_operand" "O"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_64BIT
&& DEFAULT_ABI == ABI_AIX
&& (INTVAL (operands[3]) & CALL_LONG) == 0"
[(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
(match_operand 1 "" "g,g,g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"DEFAULT_ABI == ABI_V4
|| DEFAULT_ABI == ABI_DARWIN"
{
[(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
(match_operand 1 "" "g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"(DEFAULT_ABI == ABI_DARWIN
|| (DEFAULT_ABI == ABI_V4
&& (INTVAL (operands[2]) & CALL_LONG) == 0))"
(call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
(match_operand 2 "" "g,g,g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"DEFAULT_ABI == ABI_V4
|| DEFAULT_ABI == ABI_DARWIN"
{
(call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
(match_operand 2 "" "g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"(DEFAULT_ABI == ABI_DARWIN
|| (DEFAULT_ABI == ABI_V4
&& (INTVAL (operands[3]) & CALL_LONG) == 0))"
[(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)])]
""
"
[(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
(match_operand 1 "" "g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,n"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"(INTVAL (operands[2]) & CALL_LONG) == 0"
"*
[(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
(match_operand 1 "" "g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,n"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
"*
(call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
(match_operand 2 "" "g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,n"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"(INTVAL (operands[3]) & CALL_LONG) == 0"
"*
(call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
(match_operand 2 "" "g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,n"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
"*
[(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
(match_operand 1 "" "g"))
(use (match_operand:SI 2 "immediate_operand" "O"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"TARGET_32BIT
&& DEFAULT_ABI == ABI_AIX
[(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
(match_operand 1 "" "g"))
(use (match_operand:SI 2 "immediate_operand" "O"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"TARGET_64BIT
&& DEFAULT_ABI == ABI_AIX
(call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
(match_operand 2 "" "g")))
(use (match_operand:SI 3 "immediate_operand" "O"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"TARGET_32BIT
&& DEFAULT_ABI == ABI_AIX
(call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
(match_operand 2 "" "g")))
(use (match_operand:SI 3 "immediate_operand" "O"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"TARGET_64BIT
&& DEFAULT_ABI == ABI_AIX
[(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
(match_operand 1 "" ""))
(use (match_operand 2 "immediate_operand" "O,n"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"(DEFAULT_ABI == ABI_DARWIN
|| DEFAULT_ABI == ABI_V4)
(call (mem:SI (match_operand 1 "address_operand" ""))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)])]
""
"
(call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
(match_operand 2 "" "")))
(use (match_operand:SI 3 "immediate_operand" "O,n"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"(DEFAULT_ABI == ABI_DARWIN
|| DEFAULT_ABI == ABI_V4)
(define_insn "movesi_from_cr"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
- (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
+ (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
+ (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
+ (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
+ (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
UNSPEC_MOVESI_FROM_CR))]
""
"mfcr %0"
;; MA 02110-1301, USA.
(define_constants
- [(SPE_ACC_REGNO 111)
- (SPEFSCR_REGNO 112)
-
- (CMPDFEQ_GPR 1006)
+ [(CMPDFEQ_GPR 1006)
(TSTDFEQ_GPR 1007)
(CMPDFGT_GPR 1008)
(TSTDFGT_GPR 1009)
projects / platform / upstream / linaro-gcc.git / commitdiff