[S5PC100] modifiled timer structures in s5pc1xx.h

diff --git a/cpu/arm_cortexa8/s5pc100/interrupts.c b/cpu/arm_cortexa8/s5pc100/interrupts.c
index a3d460c..1f93f10 100644 (file)
--- a/cpu/arm_cortexa8/s5pc100/interrupts.c
+++ b/cpu/arm_cortexa8/s5pc100/interrupts.c
@@ -47,15 +47,15 @@ static ulong timer_load_val;
 
 #define PRESCALER      167
 
-static s3c64xx_timers *s3c64xx_get_base_timers(void)
+static s5pc1xx_timers *s5pc1xx_get_base_timers(void)
 {
-       return (s3c64xx_timers *)S5P_TIMER_BASE;
+       return (s5pc1xx_timers *)S5P_TIMER_BASE;
 }
 
 /* macro to read the 16 bit timer */
 static inline ulong read_timer(void)
 {
-       s3c64xx_timers *const timers = s3c64xx_get_base_timers();
+       s5pc1xx_timers *const timers = s5pc1xx_get_base_timers();
 
        return timers->TCNTO4;
 }
@@ -68,7 +68,7 @@ static unsigned long long timestamp;
 
 int interrupt_init(void)
 {
-       s3c64xx_timers *const timers = s3c64xx_get_base_timers();
+       s5pc1xx_timers *const timers = s5pc1xx_get_base_timers();
 
        /* use PWM Timer 4 because it has no ouput */
        /* prescaler for timer 4 is 16 */

diff --git a/include/s5pc1x0.h b/include/s5pc1x0.h
index 435ac59..6a0ad11 100644 (file)
--- a/include/s5pc1x0.h
+++ b/include/s5pc1x0.h
@@ -71,20 +71,22 @@ typedef struct {
 #endif
 } s5pc1xx_uart;
 
-/* PWM TIMER (see manual chapter 10) */
 typedef struct {
        volatile u32    TCNTB;
        volatile u32    TCMPB;
        volatile u32    TCNTO;
-} s3c64xx_timer;
+} s5pc1xx_timer;
 
 typedef struct {
        volatile u32    TCFG0;
        volatile u32    TCFG1;
        volatile u32    TCON;
-       s3c64xx_timer   ch[4];
+       s5pc1xx_timer   ch[3];
+       volatile u32    TCNTB3;
+       volatile u32    TCNTO3;
        volatile u32    TCNTB4;
        volatile u32    TCNTO4;
-} s3c64xx_timers;
+       volatile u32    TINTCSTAT;
+} s5pc1xx_timers;
 
 #endif