PARAMS ((CGEN_OPCODE_DESC, bfd_vma, disassemble_info *));
\f
/* -- disassembler routines inserted here */
+/* -- dis.c */
+
+static void
+print_register_list (dis_info, value, offset)
+ PTR dis_info;
+ long value;
+ long offset;
+{
+ disassemble_info *info = dis_info;
+ int mask = 1;
+ int index;
+
+ if (value & mask)
+ (*info->fprintf_func) (info->stream, "r%i", index + offset);
+
+ for (index = 1; index <= 7; ++index)
+ {
+ mask <<= 1;
+ if (value & mask)
+ (*info->fprintf_func) (info->stream, ",r%i", index + offset);
+ }
+}
+
+static void
+print_reglist_hi (od, dis_info, value, attrs, pc, length)
+ CGEN_OPCODE_DESC od;
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
+{
+ print_register_list (dis_info, value, 8);
+}
+
+static void
+print_reglist_low (od, dis_info, value, attrs, pc, length)
+ CGEN_OPCODE_DESC od;
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
+{
+ print_register_list (dis_info, value, 0);
+}
+
+/* -- */
/* Main entry point for operand extraction.
case FR30_OPERAND_RJ :
length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_Rj);
break;
+ case FR30_OPERAND_RIC :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 28, 4, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_Ric);
+ break;
+ case FR30_OPERAND_RJC :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 24, 4, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_Rjc);
+ break;
+ case FR30_OPERAND_CRI :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 28, 4, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_CRi);
+ break;
+ case FR30_OPERAND_CRJ :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 24, 4, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_CRj);
+ break;
case FR30_OPERAND_RS1 :
length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_Rs1);
break;
case FR30_OPERAND_U4 :
length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_u4);
break;
+ case FR30_OPERAND_U4C :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_u4c);
+ break;
case FR30_OPERAND_M4 :
{
long value;
fields->f_rel12 = value;
}
break;
+ case FR30_OPERAND_REGLIST_LOW :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_reglist_low);
+ break;
+ case FR30_OPERAND_REGLIST_HI :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_reglist_hi);
+ break;
case FR30_OPERAND_CC :
length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_cc);
break;
+ case FR30_OPERAND_CCC :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 16, 8, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_ccc);
+ break;
default :
/* xgettext:c-format */
case FR30_OPERAND_RJ :
print_keyword (od, info, & fr30_cgen_opval_h_gr, fields->f_Rj, 0|(1<<CGEN_OPERAND_UNSIGNED));
break;
+ case FR30_OPERAND_RIC :
+ print_keyword (od, info, & fr30_cgen_opval_h_gr, fields->f_Ric, 0|(1<<CGEN_OPERAND_UNSIGNED));
+ break;
+ case FR30_OPERAND_RJC :
+ print_keyword (od, info, & fr30_cgen_opval_h_gr, fields->f_Rjc, 0|(1<<CGEN_OPERAND_UNSIGNED));
+ break;
+ case FR30_OPERAND_CRI :
+ print_keyword (od, info, & fr30_cgen_opval_h_cr, fields->f_CRi, 0|(1<<CGEN_OPERAND_UNSIGNED));
+ break;
+ case FR30_OPERAND_CRJ :
+ print_keyword (od, info, & fr30_cgen_opval_h_cr, fields->f_CRj, 0|(1<<CGEN_OPERAND_UNSIGNED));
+ break;
case FR30_OPERAND_RS1 :
print_keyword (od, info, & fr30_cgen_opval_h_dr, fields->f_Rs1, 0|(1<<CGEN_OPERAND_UNSIGNED));
break;
case FR30_OPERAND_U4 :
print_normal (od, info, fields->f_u4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
break;
+ case FR30_OPERAND_U4C :
+ print_normal (od, info, fields->f_u4c, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
case FR30_OPERAND_M4 :
print_normal (od, info, fields->f_m4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
break;
case FR30_OPERAND_LABEL12 :
print_normal (od, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
+ case FR30_OPERAND_REGLIST_LOW :
+ print_reglist_low (od, info, fields->f_reglist_low, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case FR30_OPERAND_REGLIST_HI :
+ print_reglist_hi (od, info, fields->f_reglist_hi, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
case FR30_OPERAND_CC :
print_normal (od, info, fields->f_cc, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
break;
+ case FR30_OPERAND_CCC :
+ print_normal (od, info, fields->f_ccc, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
default :
/* xgettext:c-format */
19
};
+CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
+{
+ { "cr0", 0 },
+ { "cr1", 1 },
+ { "cr2", 2 },
+ { "cr3", 3 },
+ { "cr4", 4 },
+ { "cr5", 5 },
+ { "cr6", 6 },
+ { "cr7", 7 },
+ { "cr8", 8 },
+ { "cr9", 9 },
+ { "cr10", 10 },
+ { "cr11", 11 },
+ { "cr12", 12 },
+ { "cr13", 13 },
+ { "cr14", 14 },
+ { "cr15", 15 }
+};
+
+CGEN_KEYWORD fr30_cgen_opval_h_cr =
+{
+ & fr30_cgen_opval_h_cr_entries[0],
+ 16
+};
+
CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
{
{ "tbr", 0 },
{ HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
{ HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
{ HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
+ { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
{ HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0, { 0 } } },
{ HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
{ HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
/* Rj: source register */
{ "Rj", & HW_ENT (HW_H_GR), 8, 4,
{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* Ric: target register coproc insn */
+ { "Ric", & HW_ENT (HW_H_GR), 28, 4,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* Rjc: source register coproc insn */
+ { "Rjc", & HW_ENT (HW_H_GR), 24, 4,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* CRi: coprocessor register */
+ { "CRi", & HW_ENT (HW_H_CR), 28, 4,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* CRj: coprocessor register */
+ { "CRj", & HW_ENT (HW_H_CR), 24, 4,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* Rs1: dedicated register */
{ "Rs1", & HW_ENT (HW_H_DR), 8, 4,
{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* u4: 4 bit unsigned immediate */
{ "u4", & HW_ENT (HW_H_UINT), 8, 4,
{ 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* u4c: 4 bit unsigned immediate */
+ { "u4c", & HW_ENT (HW_H_UINT), 12, 4,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* m4: 4 bit negative immediate */
{ "m4", & HW_ENT (HW_H_UINT), 8, 4,
{ 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* label12: 12 bit pc relative address */
{ "label12", & HW_ENT (HW_H_SINT), 5, 11,
{ 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
+/* reglist_low: 8 bit register mask */
+ { "reglist_low", & HW_ENT (HW_H_UINT), 8, 8,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* reglist_hi: 8 bit register mask */
+ { "reglist_hi", & HW_ENT (HW_H_UINT), 8, 8,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* cc: condition codes */
{ "cc", & HW_ENT (HW_H_UINT), 4, 4,
{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* ccc: coprocessor calc */
+ { "ccc", & HW_ENT (HW_H_UINT), 16, 8,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* nbit: negative bit */
{ "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
{ 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* call $label12 */
+/* call @$Ri */
{
{ 1, 1, 1, 1 },
- FR30_INSN_CALL, "call", "call",
- { { MNEM, ' ', OP (LABEL12), 0 } },
- { 16, 16, 0xf400 }, 0xd000,
+ FR30_INSN_CALLR, "callr", "call",
+ { { MNEM, ' ', '@', OP (RI), 0 } },
+ { 16, 16, 0xfff0 }, 0x9710,
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* call:D $label12 */
+/* call:D @$Ri */
{
{ 1, 1, 1, 1 },
- FR30_INSN_CALLD, "calld", "call:D",
- { { MNEM, ' ', OP (LABEL12), 0 } },
- { 16, 16, 0xf400 }, 0xd400,
+ FR30_INSN_CALLRD, "callrd", "call:D",
+ { { MNEM, ' ', '@', OP (RI), 0 } },
+ { 16, 16, 0xfff0 }, 0x9f10,
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* call @$Ri */
+/* call $label12 */
{
{ 1, 1, 1, 1 },
- FR30_INSN_CALLR, "callr", "call",
- { { MNEM, ' ', '@', OP (RI), 0 } },
- { 16, 16, 0xfff0 }, 0x9710,
+ FR30_INSN_CALL, "call", "call",
+ { { MNEM, ' ', OP (LABEL12), 0 } },
+ { 16, 16, 0xf400 }, 0xd000,
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* call:D @$Ri */
+/* call:D $label12 */
{
{ 1, 1, 1, 1 },
- FR30_INSN_CALLRD, "callrd", "call:D",
- { { MNEM, ' ', '@', OP (RI), 0 } },
- { 16, 16, 0xfff0 }, 0x9f10,
+ FR30_INSN_CALLD, "calld", "call:D",
+ { { MNEM, ' ', OP (LABEL12), 0 } },
+ { 16, 16, 0xf400 }, 0xd400,
(PTR) 0,
{ 0, 0, { 0 } }
},
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* dmov @$dir10,$R13 */
+/* dmov $R13,@$dir10 */
{
{ 1, 1, 1, 1 },
- FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
- { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
- { 16, 16, 0xff00 }, 0x800,
+ FR30_INSN_DMOVR13, "dmovr13", "dmov",
+ { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
+ { 16, 16, 0xff00 }, 0x1800,
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* dmovh @$dir9,$R13 */
+/* dmovh $R13,@$dir9 */
{
{ 1, 1, 1, 1 },
- FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
- { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
- { 16, 16, 0xff00 }, 0x900,
+ FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
+ { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
+ { 16, 16, 0xff00 }, 0x1900,
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* dmovb @$dir8,$R13 */
+/* dmovb $R13,@$dir8 */
{
{ 1, 1, 1, 1 },
- FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
- { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
- { 16, 16, 0xff00 }, 0xa00,
+ FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
+ { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
+ { 16, 16, 0xff00 }, 0x1a00,
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* dmov $R13,@$dir10 */
+/* dmov @$R13+,@$dir10 */
{
{ 1, 1, 1, 1 },
- FR30_INSN_DMOVR13, "dmovr13", "dmov",
- { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
- { 16, 16, 0xff00 }, 0x1800,
+ FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
+ { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
+ { 16, 16, 0xff00 }, 0x1c00,
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* dmovh $R13,@$dir9 */
+/* dmovh @$R13+,@$dir9 */
{
{ 1, 1, 1, 1 },
- FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
- { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
- { 16, 16, 0xff00 }, 0x1900,
+ FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
+ { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
+ { 16, 16, 0xff00 }, 0x1d00,
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* dmovb $R13,@$dir8 */
+/* dmovb @$R13+,@$dir8 */
{
{ 1, 1, 1, 1 },
- FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
- { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
- { 16, 16, 0xff00 }, 0x1a00,
+ FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
+ { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
+ { 16, 16, 0xff00 }, 0x1e00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmov @$R15+,@$dir10 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
+ { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
+ { 16, 16, 0xff00 }, 0x1b00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmov @$dir10,$R13 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
+ { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
+ { 16, 16, 0xff00 }, 0x800,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmovh @$dir9,$R13 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
+ { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
+ { 16, 16, 0xff00 }, 0x900,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmovb @$dir8,$R13 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
+ { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
+ { 16, 16, 0xff00 }, 0xa00,
(PTR) 0,
{ 0, 0, { 0 } }
},
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* dmov @$R13+,@$dir10 */
+/* dmov @$dir10,@-$R15 */
{
{ 1, 1, 1, 1 },
- FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
- { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
- { 16, 16, 0xff00 }, 0x1c00,
+ FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
+ { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
+ { 16, 16, 0xff00 }, 0xb00,
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* dmovh @$R13+,@$dir9 */
+/* ldres @$Ri+,$u4 */
{
{ 1, 1, 1, 1 },
- FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
- { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
- { 16, 16, 0xff00 }, 0x1d00,
+ FR30_INSN_LDRES, "ldres", "ldres",
+ { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
+ { 16, 16, 0xff00 }, 0xbc00,
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* dmovb @$R13+,@$dir8 */
+/* stres $u4,@$Ri+ */
{
{ 1, 1, 1, 1 },
- FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
- { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
- { 16, 16, 0xff00 }, 0x1e00,
+ FR30_INSN_STRES, "stres", "stres",
+ { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
+ { 16, 16, 0xff00 }, 0xbd00,
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* dmov @$dir10,@-$R15 */
+/* copop $u4c,$ccc,$CRj,$CRi */
{
{ 1, 1, 1, 1 },
- FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
- { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
- { 16, 16, 0xff00 }, 0xb00,
+ FR30_INSN_COPOP, "copop", "copop",
+ { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } },
+ { 16, 32, 0xfff0 }, 0x9fc0,
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* dmov @$R15+,@$dir10 */
+/* copld $u4c,$ccc,$Rjc,$CRi */
{
{ 1, 1, 1, 1 },
- FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
- { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
- { 16, 16, 0xff00 }, 0x1b00,
+ FR30_INSN_COPLD, "copld", "copld",
+ { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } },
+ { 16, 32, 0xfff0 }, 0x9fd0,
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* ldres @$Ri+,$u4 */
+/* copst $u4c,$ccc,$CRj,$Ric */
{
{ 1, 1, 1, 1 },
- FR30_INSN_LDRES, "ldres", "ldres",
- { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
- { 16, 16, 0xff00 }, 0xbc00,
+ FR30_INSN_COPST, "copst", "copst",
+ { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
+ { 16, 32, 0xfff0 }, 0x9fe0,
(PTR) 0,
{ 0, 0, { 0 } }
},
-/* stres $u4,@$Ri+ */
+/* copsv $u4c,$ccc,$CRj,$Ric */
{
{ 1, 1, 1, 1 },
- FR30_INSN_STRES, "stres", "stres",
- { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
- { 16, 16, 0xff00 }, 0xbd00,
+ FR30_INSN_COPSV, "copsv", "copsv",
+ { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
+ { 16, 32, 0xfff0 }, 0x9ff0,
(PTR) 0,
{ 0, 0, { 0 } }
},
(PTR) 0,
{ 0, 0, { 0 } }
},
+/* ldm0 ($reglist_low) */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDM0, "ldm0", "ldm0",
+ { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
+ { 16, 16, 0xff00 }, 0x8c00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* ldm1 ($reglist_hi) */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDM1, "ldm1", "ldm1",
+ { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
+ { 16, 16, 0xff00 }, 0x8d00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* stm0 ($reglist_low) */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_STM0, "stm0", "stm0",
+ { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
+ { 16, 16, 0xff00 }, 0x8e00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* stm1 ($reglist_hi) */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_STM1, "stm1", "stm1",
+ { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
+ { 16, 16, 0xff00 }, 0x8f00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
/* enter $u10 */
{
{ 1, 1, 1, 1 },
case FR30_OPERAND_RJ :
value = fields->f_Rj;
break;
+ case FR30_OPERAND_RIC :
+ value = fields->f_Ric;
+ break;
+ case FR30_OPERAND_RJC :
+ value = fields->f_Rjc;
+ break;
+ case FR30_OPERAND_CRI :
+ value = fields->f_CRi;
+ break;
+ case FR30_OPERAND_CRJ :
+ value = fields->f_CRj;
+ break;
case FR30_OPERAND_RS1 :
value = fields->f_Rs1;
break;
case FR30_OPERAND_U4 :
value = fields->f_u4;
break;
+ case FR30_OPERAND_U4C :
+ value = fields->f_u4c;
+ break;
case FR30_OPERAND_M4 :
value = fields->f_m4;
break;
case FR30_OPERAND_LABEL12 :
value = fields->f_rel12;
break;
+ case FR30_OPERAND_REGLIST_LOW :
+ value = fields->f_reglist_low;
+ break;
+ case FR30_OPERAND_REGLIST_HI :
+ value = fields->f_reglist_hi;
+ break;
case FR30_OPERAND_CC :
value = fields->f_cc;
break;
+ case FR30_OPERAND_CCC :
+ value = fields->f_ccc;
+ break;
default :
/* xgettext:c-format */
case FR30_OPERAND_RJ :
value = fields->f_Rj;
break;
+ case FR30_OPERAND_RIC :
+ value = fields->f_Ric;
+ break;
+ case FR30_OPERAND_RJC :
+ value = fields->f_Rjc;
+ break;
+ case FR30_OPERAND_CRI :
+ value = fields->f_CRi;
+ break;
+ case FR30_OPERAND_CRJ :
+ value = fields->f_CRj;
+ break;
case FR30_OPERAND_RS1 :
value = fields->f_Rs1;
break;
case FR30_OPERAND_U4 :
value = fields->f_u4;
break;
+ case FR30_OPERAND_U4C :
+ value = fields->f_u4c;
+ break;
case FR30_OPERAND_M4 :
value = fields->f_m4;
break;
case FR30_OPERAND_LABEL12 :
value = fields->f_rel12;
break;
+ case FR30_OPERAND_REGLIST_LOW :
+ value = fields->f_reglist_low;
+ break;
+ case FR30_OPERAND_REGLIST_HI :
+ value = fields->f_reglist_hi;
+ break;
case FR30_OPERAND_CC :
value = fields->f_cc;
break;
+ case FR30_OPERAND_CCC :
+ value = fields->f_ccc;
+ break;
default :
/* xgettext:c-format */
case FR30_OPERAND_RJ :
fields->f_Rj = value;
break;
+ case FR30_OPERAND_RIC :
+ fields->f_Ric = value;
+ break;
+ case FR30_OPERAND_RJC :
+ fields->f_Rjc = value;
+ break;
+ case FR30_OPERAND_CRI :
+ fields->f_CRi = value;
+ break;
+ case FR30_OPERAND_CRJ :
+ fields->f_CRj = value;
+ break;
case FR30_OPERAND_RS1 :
fields->f_Rs1 = value;
break;
case FR30_OPERAND_U4 :
fields->f_u4 = value;
break;
+ case FR30_OPERAND_U4C :
+ fields->f_u4c = value;
+ break;
case FR30_OPERAND_M4 :
fields->f_m4 = value;
break;
case FR30_OPERAND_LABEL12 :
fields->f_rel12 = value;
break;
+ case FR30_OPERAND_REGLIST_LOW :
+ fields->f_reglist_low = value;
+ break;
+ case FR30_OPERAND_REGLIST_HI :
+ fields->f_reglist_hi = value;
+ break;
case FR30_OPERAND_CC :
fields->f_cc = value;
break;
+ case FR30_OPERAND_CCC :
+ fields->f_ccc = value;
+ break;
default :
/* xgettext:c-format */
case FR30_OPERAND_RJ :
fields->f_Rj = value;
break;
+ case FR30_OPERAND_RIC :
+ fields->f_Ric = value;
+ break;
+ case FR30_OPERAND_RJC :
+ fields->f_Rjc = value;
+ break;
+ case FR30_OPERAND_CRI :
+ fields->f_CRi = value;
+ break;
+ case FR30_OPERAND_CRJ :
+ fields->f_CRj = value;
+ break;
case FR30_OPERAND_RS1 :
fields->f_Rs1 = value;
break;
case FR30_OPERAND_U4 :
fields->f_u4 = value;
break;
+ case FR30_OPERAND_U4C :
+ fields->f_u4c = value;
+ break;
case FR30_OPERAND_M4 :
fields->f_m4 = value;
break;
case FR30_OPERAND_LABEL12 :
fields->f_rel12 = value;
break;
+ case FR30_OPERAND_REGLIST_LOW :
+ fields->f_reglist_low = value;
+ break;
+ case FR30_OPERAND_REGLIST_HI :
+ fields->f_reglist_hi = value;
+ break;
case FR30_OPERAND_CC :
fields->f_cc = value;
break;
+ case FR30_OPERAND_CCC :
+ fields->f_ccc = value;
+ break;
default :
/* xgettext:c-format */
, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
} H_GR;
+/* Enum declaration for coprocessor registers. */
+typedef enum h_cr {
+ H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3
+ , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7
+ , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11
+ , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15
+} H_CR;
+
/* Enum declaration for dedicated registers. */
typedef enum h_dr {
H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
/* Enum declaration for fr30 operand types. */
typedef enum cgen_operand_type {
- FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RS1
+ FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
+ , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1
, FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
- , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_M4, FR30_OPERAND_U8
- , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
- , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
- , FR30_OPERAND_DIR8, FR30_OPERAND_DIR9, FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9
- , FR30_OPERAND_LABEL12, FR30_OPERAND_CC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT
+ , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_M4
+ , FR30_OPERAND_U8, FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8
+ , FR30_OPERAND_DISP9, FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10
+ , FR30_OPERAND_I32, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9, FR30_OPERAND_DIR10
+ , FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW, FR30_OPERAND_REGLIST_HI
+ , FR30_OPERAND_CC, FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT
, FR30_OPERAND_ZBIT, FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT
, FR30_OPERAND_MAX
} CGEN_OPERAND_TYPE;
, FR30_INSN_STR14B, FR30_INSN_STR15, FR30_INSN_STR15GR, FR30_INSN_STR15DR
, FR30_INSN_STR15PS, FR30_INSN_MOV, FR30_INSN_MOVDR, FR30_INSN_MOVPS
, FR30_INSN_MOV2DR, FR30_INSN_MOV2PS, FR30_INSN_JMP, FR30_INSN_JMPD
- , FR30_INSN_CALL, FR30_INSN_CALLD, FR30_INSN_CALLR, FR30_INSN_CALLRD
+ , FR30_INSN_CALLR, FR30_INSN_CALLRD, FR30_INSN_CALL, FR30_INSN_CALLD
, FR30_INSN_RET, FR30_INSN_RETD, FR30_INSN_INT, FR30_INSN_INTE
, FR30_INSN_RETI, FR30_INSN_BRA, FR30_INSN_BNO, FR30_INSN_BEQ
, FR30_INSN_BNE, FR30_INSN_BC, FR30_INSN_BNC, FR30_INSN_BN
, FR30_INSN_BNED, FR30_INSN_BCD, FR30_INSN_BNCD, FR30_INSN_BND
, FR30_INSN_BPD, FR30_INSN_BVD, FR30_INSN_BNVD, FR30_INSN_BLTD
, FR30_INSN_BGED, FR30_INSN_BLED, FR30_INSN_BGTD, FR30_INSN_BLSD
- , FR30_INSN_BHID, FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B
- , FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H, FR30_INSN_DMOVR13B, FR30_INSN_DMOV2R13PI
- , FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH
- , FR30_INSN_DMOVR13PIB, FR30_INSN_DMOV2R15PD, FR30_INSN_DMOVR15PI, FR30_INSN_LDRES
- , FR30_INSN_STRES, FR30_INSN_NOP, FR30_INSN_ANDCCR, FR30_INSN_ORCCR
+ , FR30_INSN_BHID, FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H, FR30_INSN_DMOVR13B
+ , FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH, FR30_INSN_DMOVR13PIB, FR30_INSN_DMOVR15PI
+ , FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B, FR30_INSN_DMOV2R13PI
+ , FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOV2R15PD, FR30_INSN_LDRES
+ , FR30_INSN_STRES, FR30_INSN_COPOP, FR30_INSN_COPLD, FR30_INSN_COPST
+ , FR30_INSN_COPSV, FR30_INSN_NOP, FR30_INSN_ANDCCR, FR30_INSN_ORCCR
, FR30_INSN_STILM, FR30_INSN_ADDSP, FR30_INSN_EXTSB, FR30_INSN_EXTUB
- , FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_ENTER, FR30_INSN_LEAVE
+ , FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_LDM0, FR30_INSN_LDM1
+ , FR30_INSN_STM0, FR30_INSN_STM1, FR30_INSN_ENTER, FR30_INSN_LEAVE
, FR30_INSN_XCHB, FR30_INSN_MAX
} CGEN_INSN_TYPE;
long f_op4;
long f_op5;
long f_cc;
+ long f_ccc;
long f_Rj;
long f_Ri;
long f_Rs1;
long f_Rs2;
+ long f_Rjc;
+ long f_Ric;
+ long f_CRj;
+ long f_CRi;
long f_u4;
+ long f_u4c;
long f_i4;
long f_m4;
long f_u8;
long f_dir9;
long f_dir10;
long f_rel12;
+ long f_reglist_hi;
+ long f_reglist_low;
int length;
};
/* Enum declaration for fr30 hardware types. */
typedef enum hw_type {
HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
- , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_DR
- , HW_H_PS, HW_H_R13, HW_H_R14, HW_H_R15
- , HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT, HW_H_CBIT
- , HW_H_IBIT, HW_H_SBIT, HW_MAX
+ , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CR
+ , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
+ , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
+ , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_MAX
} HW_TYPE;
#define MAX_HW ((int) HW_MAX)
/* Hardware decls. */
extern CGEN_KEYWORD fr30_cgen_opval_h_gr;
+extern CGEN_KEYWORD fr30_cgen_opval_h_cr;
extern CGEN_KEYWORD fr30_cgen_opval_h_dr;
extern CGEN_KEYWORD fr30_cgen_opval_h_ps;
extern CGEN_KEYWORD fr30_cgen_opval_h_r13;
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