arm64: dts: ti: k3-am64-main: Enable crypto accelerator
authorPeter Ujfalusi <peter.ujfalusi@ti.com>
Mon, 11 Jul 2022 08:57:43 +0000 (14:27 +0530)
committerVignesh Raghavendra <vigneshr@ti.com>
Thu, 1 Sep 2022 10:05:53 +0000 (15:35 +0530)
Add the node for SA2UL.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[s-anna@ti.com: drop label, minor cleanups]
Signed-off-by: Suman Anna <s-anna@ti.com>
[j-choudhary@ti.com: disable rng-node, change flag to shared]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
Link: https://lore.kernel.org/r/20220711085743.10128-3-j-choudhary@ti.com
arch/arm64/boot/dts/ti/k3-am64-main.dtsi

index a364c17..744629c 100644 (file)
                interrupt-names = "int0", "int1";
                bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
        };
+
+       crypto: crypto@40900000 {
+               compatible = "ti,am64-sa2ul";
+               reg = <0x00 0x40900000 0x00 0x1200>;
+               power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
+               dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>,
+                      <&main_pktdma 0x4003 0>;
+               dma-names = "tx", "rx1", "rx2";
+
+               rng: rng@40910000 {
+                       compatible = "inside-secure,safexcel-eip76";
+                       reg = <0x00 0x40910000 0x00 0x7d>;
+                       interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&k3_clks 133 1>;
+                       status = "disabled"; /* Used by OP-TEE */
+               };
+       };
 };