arm64: dts: qcom: ipq5332: enable the CPUFreq support

Add the APCS, A53 PLL, cpu-opp-table nodes to bump the CPU frequency
above 800MHz.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230217083308.12017-6-quic_kathirav@quicinc.com

diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 76d739b..04ef80f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -5,6 +5,7 @@
  * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include <dt-bindings/clock/qcom,apss-ipq.h>
 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
@@ -35,6 +36,8 @@
                        reg = <0x0>;
                        enable-method = "psci";
                        next-level-cache = <&L2_0>;
+                       clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+                       operating-points-v2 = <&cpu_opp_table>;
                };
 
                CPU1: cpu@1 {
@@ -43,6 +46,8 @@
                        reg = <0x1>;
                        enable-method = "psci";
                        next-level-cache = <&L2_0>;
+                       clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+                       operating-points-v2 = <&cpu_opp_table>;
                };
 
                CPU2: cpu@2 {
@@ -51,6 +56,8 @@
                        reg = <0x2>;
                        enable-method = "psci";
                        next-level-cache = <&L2_0>;
+                       clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+                       operating-points-v2 = <&cpu_opp_table>;
                };
 
                CPU3: cpu@3 {
@@ -59,6 +66,8 @@
                        reg = <0x3>;
                        enable-method = "psci";
                        next-level-cache = <&L2_0>;
+                       clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+                       operating-points-v2 = <&cpu_opp_table>;
                };
 
                L2_0: l2-cache {
@@ -80,6 +89,16 @@
                reg = <0x0 0x40000000 0x0 0x0>;
        };
 
+       cpu_opp_table: opp-table-cpu {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-1488000000 {
+                       opp-hz = /bits/ 64 <1488000000>;
+                       clock-latency-ns = <200000>;
+               };
+       };
+
        pmu {
                compatible = "arm,cortex-a53-pmu";
                interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
@@ -214,6 +233,24 @@
                        };
                };
 
+               apcs_glb: mailbox@b111000 {
+                       compatible = "qcom,ipq5332-apcs-apps-global",
+                                    "qcom,ipq6018-apcs-apps-global";
+                       reg = <0x0b111000 0x1000>;
+                       #clock-cells = <1>;
+                       clocks = <&a53pll>, <&xo_board>;
+                       clock-names = "pll", "xo";
+                       #mbox-cells = <1>;
+               };
+
+               a53pll: clock@b116000 {
+                       compatible = "qcom,ipq5332-a53pll";
+                       reg = <0x0b116000 0x40>;
+                       #clock-cells = <0>;
+                       clocks = <&xo_board>;
+                       clock-names = "xo";
+               };
+
                timer@b120000 {
                        compatible = "arm,armv7-timer-mem";
                        reg = <0x0b120000 0x1000>;