ptp: idt82p33: Add .getmaxphase ptp_clock_info callback

Advertise the maximum offset the .adjphase callback is capable of
supporting in nanoseconds for IDT devices.

Refactor the negation of the offset stored in the register to be after the
boundary check of the offset value rather than before. Boundary check based
on the intended value rather than its device-specific representation.
Depend on ptp_clock_adjtime for handling out-of-range offsets.
ptp_clock_adjtime returns -ERANGE instead of clamping out-of-range offsets.

Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Min Li <min.li.xe@renesas.com>
Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/ptp/ptp_idt82p33.c b/drivers/ptp/ptp_idt82p33.c
index afc76c22271ad3dd8d4d650abe7408b15f753f54..057190b9cd3d85ae7f579437ff141184c1dc9ad3 100644 (file)
--- a/drivers/ptp/ptp_idt82p33.c
+++ b/drivers/ptp/ptp_idt82p33.c
@@ -978,24 +978,23 @@ static int idt82p33_enable(struct ptp_clock_info *ptp,
        return err;
 }
 
+static s32 idt82p33_getmaxphase(__always_unused struct ptp_clock_info *ptp)
+{
+       return WRITE_PHASE_OFFSET_LIMIT;
+}
+
 static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 offset_ns)
 {
        struct idt82p33_channel *channel =
                container_of(ptp, struct idt82p33_channel, caps);
        struct idt82p33 *idt82p33 = channel->idt82p33;
-       s64 offset_regval, offset_fs;
+       s64 offset_regval;
        u8 val[4] = {0};
        int err;
 
-       offset_fs = (s64)(-offset_ns) * 1000000;
-
-       if (offset_fs > WRITE_PHASE_OFFSET_LIMIT)
-               offset_fs = WRITE_PHASE_OFFSET_LIMIT;
-       else if (offset_fs < -WRITE_PHASE_OFFSET_LIMIT)
-               offset_fs = -WRITE_PHASE_OFFSET_LIMIT;
-
        /* Convert from phaseoffset_fs to register value */
-       offset_regval = div_s64(offset_fs * 1000, IDT_T0DPLL_PHASE_RESOL);
+       offset_regval = div_s64((s64)(-offset_ns) * 1000000000ll,
+                               IDT_T0DPLL_PHASE_RESOL);
 
        val[0] = offset_regval & 0xFF;
        val[1] = (offset_regval >> 8) & 0xFF;
@@ -1175,6 +1174,7 @@ static void idt82p33_caps_init(u32 index, struct ptp_clock_info *caps,
        caps->n_ext_ts = MAX_PHC_PLL,
        caps->n_pins = max_pins,
        caps->adjphase = idt82p33_adjwritephase,
+       caps->getmaxphase = idt82p33_getmaxphase,
        caps->adjfine = idt82p33_adjfine;
        caps->adjtime = idt82p33_adjtime;
        caps->gettime64 = idt82p33_gettime;

diff --git a/drivers/ptp/ptp_idt82p33.h b/drivers/ptp/ptp_idt82p33.h
index 8fcb0b17d20782259461d069640d4be7eee3d415..6a63c14b6966b62da0c40d8bb4eef7da5ce4720a 100644 (file)
--- a/drivers/ptp/ptp_idt82p33.h
+++ b/drivers/ptp/ptp_idt82p33.h
@@ -43,9 +43,9 @@
 #define DEFAULT_OUTPUT_MASK_PLL1       DEFAULT_OUTPUT_MASK_PLL0
 
 /**
- * @brief Maximum absolute value for write phase offset in femtoseconds
+ * @brief Maximum absolute value for write phase offset in nanoseconds
  */
-#define WRITE_PHASE_OFFSET_LIMIT (20000052084ll)
+#define WRITE_PHASE_OFFSET_LIMIT (20000l)
 
 /** @brief Phase offset resolution
  *