; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=X32
-; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=X64
+; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=X86
+; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=X64
; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/avx2-builtins.c
define <4 x i64> @test_mm256_abs_epi8(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_abs_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpabsb %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_abs_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpabsb %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_abs_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpabsb %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg = bitcast <4 x i64> %a0 to <32 x i8>
%sub = sub <32 x i8> zeroinitializer, %arg
%cmp = icmp sgt <32 x i8> %arg, zeroinitializer
declare <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_abs_epi16(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_abs_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpabsw %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_abs_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpabsw %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_abs_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpabsw %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg = bitcast <4 x i64> %a0 to <16 x i16>
%sub = sub <16 x i16> zeroinitializer, %arg
%cmp = icmp sgt <16 x i16> %arg, zeroinitializer
declare <16 x i16> @llvm.x86.avx2.pabs.w(<16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_abs_epi32(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_abs_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpabsd %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_abs_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpabsd %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_abs_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpabsd %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg = bitcast <4 x i64> %a0 to <8 x i32>
%sub = sub <8 x i32> zeroinitializer, %arg
%cmp = icmp sgt <8 x i32> %arg, zeroinitializer
declare <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_add_epi8(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_add_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpaddb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_add_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpaddb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_add_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpaddb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = add <32 x i8> %arg0, %arg1
}
define <4 x i64> @test_mm256_add_epi16(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_add_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpaddw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_add_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpaddw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_add_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpaddw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = add <16 x i16> %arg0, %arg1
}
define <4 x i64> @test_mm256_add_epi32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_add_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpaddd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_add_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpaddd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_add_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = add <8 x i32> %arg0, %arg1
}
define <4 x i64> @test_mm256_add_epi64(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_add_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpaddq %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_add_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpaddq %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_add_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpaddq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = add <4 x i64> %a0, %a1
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_adds_epi8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_adds_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpaddsb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_adds_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpaddsb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_adds_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpaddsb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = call <32 x i8> @llvm.x86.avx2.padds.b(<32 x i8> %arg0, <32 x i8> %arg1)
declare <32 x i8> @llvm.x86.avx2.padds.b(<32 x i8>, <32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_adds_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_adds_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpaddsw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_adds_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpaddsw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_adds_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpaddsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.padds.w(<16 x i16> %arg0, <16 x i16> %arg1)
declare <16 x i16> @llvm.x86.avx2.padds.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_adds_epu8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_adds_epu8:
-; X32: # BB#0:
-; X32-NEXT: vpaddusb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_adds_epu8:
-; X64: # BB#0:
-; X64-NEXT: vpaddusb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_adds_epu8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpaddusb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = call <32 x i8> @llvm.x86.avx2.paddus.b(<32 x i8> %arg0, <32 x i8> %arg1)
declare <32 x i8> @llvm.x86.avx2.paddus.b(<32 x i8>, <32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_adds_epu16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_adds_epu16:
-; X32: # BB#0:
-; X32-NEXT: vpaddusw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_adds_epu16:
-; X64: # BB#0:
-; X64-NEXT: vpaddusw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_adds_epu16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpaddusw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.paddus.w(<16 x i16> %arg0, <16 x i16> %arg1)
declare <16 x i16> @llvm.x86.avx2.paddus.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_alignr_epi8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_alignr_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm1[0,1],ymm0[18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm1[16,17]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_alignr_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm1[0,1],ymm0[18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm1[16,17]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_alignr_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm1[0,1],ymm0[18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm1[16,17]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%shuf = shufflevector <32 x i8> %arg0, <32 x i8> %arg1, <32 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49>
}
define <4 x i64> @test2_mm256_alignr_epi8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test2_mm256_alignr_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm1[0],ymm0[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm1[16]
-; X32-NEXT: retl
-;
-; X64-LABEL: test2_mm256_alignr_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm1[0],ymm0[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm1[16]
-; X64-NEXT: retq
+; CHECK-LABEL: test2_mm256_alignr_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm1[0],ymm0[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm1[16]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%shuf = shufflevector <32 x i8> %arg0, <32 x i8> %arg1, <32 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48>
}
define <4 x i64> @test_mm256_and_si256(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_and_si256:
-; X32: # BB#0:
-; X32-NEXT: vandps %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_and_si256:
-; X64: # BB#0:
-; X64-NEXT: vandps %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_and_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vandps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = and <4 x i64> %a0, %a1
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_andnot_si256(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_andnot_si256:
-; X32: # BB#0:
-; X32-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
-; X32-NEXT: vpxor %ymm2, %ymm0, %ymm0
-; X32-NEXT: vpand %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_andnot_si256:
-; X64: # BB#0:
-; X64-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
-; X64-NEXT: vpxor %ymm2, %ymm0, %ymm0
-; X64-NEXT: vpand %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_andnot_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; CHECK-NEXT: vpxor %ymm2, %ymm0, %ymm0
+; CHECK-NEXT: vpand %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%not = xor <4 x i64> %a0, <i64 -1, i64 -1, i64 -1, i64 -1>
%res = and <4 x i64> %not, %a1
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_avg_epu8(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_avg_epu8:
-; X32: # BB#0:
-; X32-NEXT: vpavgb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_avg_epu8:
-; X64: # BB#0:
-; X64-NEXT: vpavgb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_avg_epu8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpavgb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%zext0 = zext <32 x i8> %arg0 to <32 x i16>
}
define <4 x i64> @test_mm256_avg_epu16(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_avg_epu16:
-; X32: # BB#0:
-; X32-NEXT: vpavgw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_avg_epu16:
-; X64: # BB#0:
-; X64-NEXT: vpavgw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_avg_epu16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpavgw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%zext0 = zext <16 x i16> %arg0 to <16 x i32>
}
define <4 x i64> @test_mm256_blend_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_blend_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7,8],ymm1[9],ymm0[10,11,12,13,14,15]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_blend_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7,8],ymm1[9],ymm0[10,11,12,13,14,15]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_blend_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7,8],ymm1[9],ymm0[10,11,12,13,14,15]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%shuf = shufflevector <16 x i16> %arg0, <16 x i16> %arg1, <16 x i32> <i32 0, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 25, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
}
define <2 x i64> @test_mm_blend_epi32(<2 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_blend_epi32:
-; X32: # BB#0:
-; X32-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_blend_epi32:
-; X64: # BB#0:
-; X64-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_blend_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%shuf = shufflevector <4 x i32> %arg0, <4 x i32> %arg1, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
}
define <4 x i64> @test_mm256_blend_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_blend_epi32:
-; X32: # BB#0:
-; X32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_blend_epi32:
-; X64: # BB#0:
-; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_blend_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%shuf = shufflevector <8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 13, i32 6, i32 7>
}
define <4 x i64> @test_mm256_blendv_epi8(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) {
-; X32-LABEL: test_mm256_blendv_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_blendv_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_blendv_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%arg2 = bitcast <4 x i64> %a2 to <32 x i8>
declare <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8>, <32 x i8>, <32 x i8>) nounwind readnone
define <2 x i64> @test_mm_broadcastb_epi8(<2 x i64> %a0) {
-; X32-LABEL: test_mm_broadcastb_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpbroadcastb %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_broadcastb_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpbroadcastb %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_broadcastb_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpbroadcastb %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%shuf = shufflevector <16 x i8> %arg0, <16 x i8> undef, <16 x i32> zeroinitializer
%res = bitcast <16 x i8> %shuf to <2 x i64>
}
define <4 x i64> @test_mm256_broadcastb_epi8(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_broadcastb_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpbroadcastb %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_broadcastb_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpbroadcastb %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_broadcastb_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpbroadcastb %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%shuf = shufflevector <32 x i8> %arg0, <32 x i8> undef, <32 x i32> zeroinitializer
%res = bitcast <32 x i8> %shuf to <4 x i64>
}
define <2 x i64> @test_mm_broadcastd_epi32(<2 x i64> %a0) {
-; X32-LABEL: test_mm_broadcastd_epi32:
-; X32: # BB#0:
-; X32-NEXT: vbroadcastss %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_broadcastd_epi32:
-; X64: # BB#0:
-; X64-NEXT: vbroadcastss %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_broadcastd_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vbroadcastss %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%shuf = shufflevector <4 x i32> %arg0, <4 x i32> undef, <4 x i32> zeroinitializer
%res = bitcast <4 x i32> %shuf to <2 x i64>
}
define <4 x i64> @test_mm256_broadcastd_epi32(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_broadcastd_epi32:
-; X32: # BB#0:
-; X32-NEXT: vbroadcastss %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_broadcastd_epi32:
-; X64: # BB#0:
-; X64-NEXT: vbroadcastss %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_broadcastd_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%shuf = shufflevector <8 x i32> %arg0, <8 x i32> undef, <8 x i32> zeroinitializer
%res = bitcast <8 x i32> %shuf to <4 x i64>
}
define <2 x i64> @test_mm_broadcastq_epi64(<2 x i64> %a0) {
-; X32-LABEL: test_mm_broadcastq_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpbroadcastq %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_broadcastq_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpbroadcastq %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_broadcastq_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpbroadcastq %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <2 x i64> %a0, <2 x i64> undef, <2 x i32> zeroinitializer
ret <2 x i64> %res
}
define <4 x i64> @test_mm256_broadcastq_epi64(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_broadcastq_epi64:
-; X32: # BB#0:
-; X32-NEXT: vbroadcastsd %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_broadcastq_epi64:
-; X64: # BB#0:
-; X64-NEXT: vbroadcastsd %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_broadcastq_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> zeroinitializer
ret <4 x i64> %res
}
define <2 x double> @test_mm_broadcastsd_pd(<2 x double> %a0) {
-; X32-LABEL: test_mm_broadcastsd_pd:
-; X32: # BB#0:
-; X32-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_broadcastsd_pd:
-; X64: # BB#0:
-; X64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_broadcastsd_pd:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <2 x double> %a0, <2 x double> undef, <2 x i32> zeroinitializer
ret <2 x double> %res
}
define <4 x double> @test_mm256_broadcastsd_pd(<4 x double> %a0) {
-; X32-LABEL: test_mm256_broadcastsd_pd:
-; X32: # BB#0:
-; X32-NEXT: vbroadcastsd %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_broadcastsd_pd:
-; X64: # BB#0:
-; X64-NEXT: vbroadcastsd %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_broadcastsd_pd:
+; CHECK: # BB#0:
+; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> zeroinitializer
ret <4 x double> %res
}
define <4 x i64> @test_mm256_broadcastsi128_si256(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_broadcastsi128_si256:
-; X32: # BB#0:
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
-; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_broadcastsi128_si256:
-; X64: # BB#0:
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
-; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_broadcastsi128_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <2 x i64> %a0, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_broadcastsi128_si256_mem(<2 x i64>* %p0) {
-; X32-LABEL: test_mm256_broadcastsi128_si256_mem:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_broadcastsi128_si256_mem:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_broadcastsi128_si256_mem:
; X64: # BB#0:
; X64-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%a0 = load <2 x i64>, <2 x i64>* %p0
%res = shufflevector <2 x i64> %a0, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
ret <4 x i64> %res
}
define <4 x float> @test_mm_broadcastss_ps(<4 x float> %a0) {
-; X32-LABEL: test_mm_broadcastss_ps:
-; X32: # BB#0:
-; X32-NEXT: vbroadcastss %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_broadcastss_ps:
-; X64: # BB#0:
-; X64-NEXT: vbroadcastss %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_broadcastss_ps:
+; CHECK: # BB#0:
+; CHECK-NEXT: vbroadcastss %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> zeroinitializer
ret <4 x float> %res
}
define <8 x float> @test_mm256_broadcastss_ps(<8 x float> %a0) {
-; X32-LABEL: test_mm256_broadcastss_ps:
-; X32: # BB#0:
-; X32-NEXT: vbroadcastss %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_broadcastss_ps:
-; X64: # BB#0:
-; X64-NEXT: vbroadcastss %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_broadcastss_ps:
+; CHECK: # BB#0:
+; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <8 x float> %a0, <8 x float> undef, <8 x i32> zeroinitializer
ret <8 x float> %res
}
define <2 x i64> @test_mm_broadcastw_epi16(<2 x i64> %a0) {
-; X32-LABEL: test_mm_broadcastw_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpbroadcastw %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_broadcastw_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpbroadcastw %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_broadcastw_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpbroadcastw %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <8 x i16>
%shuf = shufflevector <8 x i16> %arg0, <8 x i16> undef, <8 x i32> zeroinitializer
%res = bitcast <8 x i16> %shuf to <2 x i64>
}
define <4 x i64> @test_mm256_broadcastw_epi16(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_broadcastw_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpbroadcastw %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_broadcastw_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpbroadcastw %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_broadcastw_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpbroadcastw %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%shuf = shufflevector <16 x i16> %arg0, <16 x i16> undef, <16 x i32> zeroinitializer
%res = bitcast <16 x i16> %shuf to <4 x i64>
}
define <4 x i64> @test_mm256_bslli_epi128(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_bslli_epi128:
-; X32: # BB#0:
-; X32-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12],zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_bslli_epi128:
-; X64: # BB#0:
-; X64-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12],zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_bslli_epi128:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12],zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%shuf = shufflevector <32 x i8> zeroinitializer, <32 x i8> %arg0, <32 x i32> <i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60>
%res = bitcast <32 x i8> %shuf to <4 x i64>
}
define <4 x i64> @test_mm256_bsrli_epi128(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_bsrli_epi128:
-; X32: # BB#0:
-; X32-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,ymm0[19,20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_bsrli_epi128:
-; X64: # BB#0:
-; X64-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,ymm0[19,20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_bsrli_epi128:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,ymm0[19,20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%shuf = shufflevector <32 x i8> %arg0, <32 x i8> zeroinitializer, <32 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50>
%res = bitcast <32 x i8> %shuf to <4 x i64>
}
define <4 x i64> @test_mm256_cmpeq_epi8(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_cmpeq_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cmpeq_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cmpeq_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%cmp = icmp eq <32 x i8> %arg0, %arg1
}
define <4 x i64> @test_mm256_cmpeq_epi16(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_cmpeq_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cmpeq_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cmpeq_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%cmp = icmp eq <16 x i16> %arg0, %arg1
}
define <4 x i64> @test_mm256_cmpeq_epi32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_cmpeq_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpcmpeqd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cmpeq_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpcmpeqd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cmpeq_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpeqd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%cmp = icmp eq <8 x i32> %arg0, %arg1
}
define <4 x i64> @test_mm256_cmpeq_epi64(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_cmpeq_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cmpeq_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cmpeq_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%cmp = icmp eq <4 x i64> %a0, %a1
%res = sext <4 x i1> %cmp to <4 x i64>
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_cmpgt_epi8(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_cmpgt_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cmpgt_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cmpgt_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%cmp = icmp sgt <32 x i8> %arg0, %arg1
}
define <4 x i64> @test_mm256_cmpgt_epi16(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_cmpgt_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cmpgt_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cmpgt_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%cmp = icmp sgt <16 x i16> %arg0, %arg1
}
define <4 x i64> @test_mm256_cmpgt_epi32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_cmpgt_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cmpgt_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cmpgt_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%cmp = icmp sgt <8 x i32> %arg0, %arg1
}
define <4 x i64> @test_mm256_cmpgt_epi64(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_cmpgt_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cmpgt_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cmpgt_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%cmp = icmp sgt <4 x i64> %a0, %a1
%res = sext <4 x i1> %cmp to <4 x i64>
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_cvtepi8_epi16(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepi8_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpmovsxbw %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepi8_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpmovsxbw %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepi8_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovsxbw %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%ext = sext <16 x i8> %arg0 to <16 x i16>
%res = bitcast <16 x i16> %ext to <4 x i64>
}
define <4 x i64> @test_mm256_cvtepi8_epi32(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepi8_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpmovsxbd %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepi8_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpmovsxbd %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepi8_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovsxbd %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%shuf = shufflevector <16 x i8> %arg0, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%ext = sext <8 x i8> %shuf to <8 x i32>
}
define <4 x i64> @test_mm256_cvtepi8_epi64(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepi8_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpmovsxbq %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepi8_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpmovsxbq %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepi8_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovsxbq %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%shuf = shufflevector <16 x i8> %arg0, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%ext = sext <4 x i8> %shuf to <4 x i64>
}
define <4 x i64> @test_mm256_cvtepi16_epi32(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepi16_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpmovsxwd %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepi16_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpmovsxwd %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepi16_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovsxwd %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <8 x i16>
%ext = sext <8 x i16> %arg0 to <8 x i32>
%res = bitcast <8 x i32> %ext to <4 x i64>
}
define <4 x i64> @test_mm256_cvtepi16_epi64(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepi16_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpmovsxwq %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepi16_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpmovsxwq %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepi16_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovsxwq %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <8 x i16>
%shuf = shufflevector <8 x i16> %arg0, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%ext = sext <4 x i16> %shuf to <4 x i64>
}
define <4 x i64> @test_mm256_cvtepi32_epi64(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepi32_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpmovsxdq %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepi32_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpmovsxdq %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepi32_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovsxdq %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%ext = sext <4 x i32> %arg0 to <4 x i64>
ret <4 x i64> %ext
}
define <4 x i64> @test_mm256_cvtepu8_epi16(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepu8_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepu8_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepu8_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%ext = zext <16 x i8> %arg0 to <16 x i16>
%res = bitcast <16 x i16> %ext to <4 x i64>
}
define <4 x i64> @test_mm256_cvtepu8_epi32(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepu8_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepu8_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepu8_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%shuf = shufflevector <16 x i8> %arg0, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%ext = zext <8 x i8> %shuf to <8 x i32>
}
define <4 x i64> @test_mm256_cvtepu8_epi64(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepu8_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepu8_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepu8_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%shuf = shufflevector <16 x i8> %arg0, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%ext = zext <4 x i8> %shuf to <4 x i64>
}
define <4 x i64> @test_mm256_cvtepu16_epi32(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepu16_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepu16_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepu16_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <8 x i16>
%ext = zext <8 x i16> %arg0 to <8 x i32>
%res = bitcast <8 x i32> %ext to <4 x i64>
}
define <4 x i64> @test_mm256_cvtepu16_epi64(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepu16_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepu16_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepu16_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <8 x i16>
%shuf = shufflevector <8 x i16> %arg0, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%ext = zext <4 x i16> %shuf to <4 x i64>
}
define <4 x i64> @test_mm256_cvtepu32_epi64(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepu32_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepu32_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepu32_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%ext = zext <4 x i32> %arg0 to <4 x i64>
ret <4 x i64> %ext
}
define <2 x i64> @test_mm256_extracti128_si256(<4 x i64> %a0) nounwind {
-; X32-LABEL: test_mm256_extracti128_si256:
-; X32: # BB#0:
-; X32-NEXT: vextractf128 $1, %ymm0, %xmm0
-; X32-NEXT: vzeroupper
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_extracti128_si256:
-; X64: # BB#0:
-; X64-NEXT: vextractf128 $1, %ymm0, %xmm0
-; X64-NEXT: vzeroupper
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_extracti128_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x i64> %a0, <4 x i64> %a0, <2 x i32> <i32 2, i32 3>
ret <2 x i64> %res
}
define <4 x i64> @test_mm256_hadd_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_hadd_epi16:
-; X32: # BB#0:
-; X32-NEXT: vphaddw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_hadd_epi16:
-; X64: # BB#0:
-; X64-NEXT: vphaddw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_hadd_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vphaddw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> %arg0, <16 x i16> %arg1)
declare <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_hadd_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_hadd_epi32:
-; X32: # BB#0:
-; X32-NEXT: vphaddd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_hadd_epi32:
-; X64: # BB#0:
-; X64-NEXT: vphaddd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_hadd_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vphaddd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = call <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32> %arg0, <8 x i32> %arg1)
declare <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32>, <8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_hadds_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_hadds_epi16:
-; X32: # BB#0:
-; X32-NEXT: vphaddsw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_hadds_epi16:
-; X64: # BB#0:
-; X64-NEXT: vphaddsw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_hadds_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vphaddsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16> %arg0, <16 x i16> %arg1)
declare <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_hsub_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_hsub_epi16:
-; X32: # BB#0:
-; X32-NEXT: vphsubw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_hsub_epi16:
-; X64: # BB#0:
-; X64-NEXT: vphsubw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_hsub_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vphsubw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16> %arg0, <16 x i16> %arg1)
declare <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_hsub_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_hsub_epi32:
-; X32: # BB#0:
-; X32-NEXT: vphsubd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_hsub_epi32:
-; X64: # BB#0:
-; X64-NEXT: vphsubd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_hsub_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vphsubd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = call <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32> %arg0, <8 x i32> %arg1)
declare <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32>, <8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_hsubs_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_hsubs_epi16:
-; X32: # BB#0:
-; X32-NEXT: vphsubsw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_hsubs_epi16:
-; X64: # BB#0:
-; X64-NEXT: vphsubsw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_hsubs_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vphsubsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16> %arg0, <16 x i16> %arg1)
declare <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16>, <16 x i16>) nounwind readnone
define <2 x i64> @test_mm_i32gather_epi32(i32 *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_i32gather_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpgatherdd %xmm2, (%eax,%xmm0,2), %xmm1
-; X32-NEXT: vmovdqa %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_i32gather_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpgatherdd %xmm2, (%eax,%xmm0,2), %xmm1
+; X86-NEXT: vmovdqa %xmm1, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_i32gather_epi32:
; X64: # BB#0:
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherdd %xmm2, (%rdi,%xmm0,2), %xmm1
; X64-NEXT: vmovdqa %xmm1, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i32 *%a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%mask = bitcast <2 x i64> <i64 -1, i64 -1> to <4 x i32>
declare <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32>, i8*, <4 x i32>, <4 x i32>, i8) nounwind readonly
define <2 x i64> @test_mm_mask_i32gather_epi32(<2 x i64> %a0, i32 *%a1, <2 x i64> %a2, <2 x i64> %a3) {
-; X32-LABEL: test_mm_mask_i32gather_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpgatherdd %xmm2, (%eax,%xmm1,2), %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_mask_i32gather_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpgatherdd %xmm2, (%eax,%xmm1,2), %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_mask_i32gather_epi32:
; X64: # BB#0:
; X64-NEXT: vpgatherdd %xmm2, (%rdi,%xmm1,2), %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%arg1 = bitcast i32 *%a1 to i8*
%arg2 = bitcast <2 x i64> %a2 to <4 x i32>
}
define <4 x i64> @test_mm256_i32gather_epi32(i32 *%a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_i32gather_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpgatherdd %ymm2, (%eax,%ymm0,2), %ymm1
-; X32-NEXT: vmovdqa %ymm1, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_i32gather_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpgatherdd %ymm2, (%eax,%ymm0,2), %ymm1
+; X86-NEXT: vmovdqa %ymm1, %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_i32gather_epi32:
; X64: # BB#0:
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherdd %ymm2, (%rdi,%ymm0,2), %ymm1
; X64-NEXT: vmovdqa %ymm1, %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i32 *%a0 to i8*
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%mask = bitcast <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1> to <8 x i32>
declare <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32>, i8*, <8 x i32>, <8 x i32>, i8) nounwind readonly
define <4 x i64> @test_mm256_mask_i32gather_epi32(<4 x i64> %a0, i32 *%a1, <4 x i64> %a2, <4 x i64> %a3) {
-; X32-LABEL: test_mm256_mask_i32gather_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpgatherdd %ymm2, (%eax,%ymm1,2), %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_mask_i32gather_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpgatherdd %ymm2, (%eax,%ymm1,2), %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_mask_i32gather_epi32:
; X64: # BB#0:
; X64-NEXT: vpgatherdd %ymm2, (%rdi,%ymm1,2), %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast i32 *%a1 to i8*
%arg2 = bitcast <4 x i64> %a2 to <8 x i32>
}
define <2 x i64> @test_mm_i32gather_epi64(i64 *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_i32gather_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpgatherdq %xmm2, (%eax,%xmm0,2), %xmm1
-; X32-NEXT: vmovdqa %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_i32gather_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpgatherdq %xmm2, (%eax,%xmm0,2), %xmm1
+; X86-NEXT: vmovdqa %xmm1, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_i32gather_epi64:
; X64: # BB#0:
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherdq %xmm2, (%rdi,%xmm0,2), %xmm1
; X64-NEXT: vmovdqa %xmm1, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i64 *%a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64> undef, i8* %arg0, <4 x i32> %arg1, <2 x i64> <i64 -1, i64 -1>, i8 2)
declare <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64>, i8*, <4 x i32>, <2 x i64>, i8) nounwind readonly
define <2 x i64> @test_mm_mask_i32gather_epi64(<2 x i64> %a0, i64 *%a1, <2 x i64> %a2, <2 x i64> %a3) {
-; X32-LABEL: test_mm_mask_i32gather_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpgatherdq %xmm2, (%eax,%xmm1,2), %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_mask_i32gather_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpgatherdq %xmm2, (%eax,%xmm1,2), %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_mask_i32gather_epi64:
; X64: # BB#0:
; X64-NEXT: vpgatherdq %xmm2, (%rdi,%xmm1,2), %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast i64 *%a1 to i8*
%arg2 = bitcast <2 x i64> %a2 to <4 x i32>
%res = call <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64> %a0, i8* %arg1, <4 x i32> %arg2, <2 x i64> %a3, i8 2)
}
define <4 x i64> @test_mm256_i32gather_epi64(i64 *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_i32gather_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpgatherdq %ymm2, (%eax,%xmm0,2), %ymm1
-; X32-NEXT: vmovdqa %ymm1, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_i32gather_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpgatherdq %ymm2, (%eax,%xmm0,2), %ymm1
+; X86-NEXT: vmovdqa %ymm1, %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_i32gather_epi64:
; X64: # BB#0:
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherdq %ymm2, (%rdi,%xmm0,2), %ymm1
; X64-NEXT: vmovdqa %ymm1, %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i64 *%a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> undef, i8* %arg0, <4 x i32> %arg1, <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, i8 2)
declare <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64>, i8*, <4 x i32>, <4 x i64>, i8) nounwind readonly
define <4 x i64> @test_mm256_mask_i32gather_epi64(<4 x i64> %a0, i64 *%a1, <2 x i64> %a2, <4 x i64> %a3) {
-; X32-LABEL: test_mm256_mask_i32gather_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpgatherdq %ymm2, (%eax,%xmm1,2), %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_mask_i32gather_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpgatherdq %ymm2, (%eax,%xmm1,2), %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_mask_i32gather_epi64:
; X64: # BB#0:
; X64-NEXT: vpgatherdq %ymm2, (%rdi,%xmm1,2), %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast i64 *%a1 to i8*
%arg2 = bitcast <2 x i64> %a2 to <4 x i32>
%res = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> %a0, i8* %arg1, <4 x i32> %arg2, <4 x i64> %a3, i8 2)
}
define <2 x double> @test_mm_i32gather_pd(double *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_i32gather_pd:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; X32-NEXT: vgatherdpd %xmm2, (%eax,%xmm0,2), %xmm1
-; X32-NEXT: vmovapd %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_i32gather_pd:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; X86-NEXT: vgatherdpd %xmm2, (%eax,%xmm0,2), %xmm1
+; X86-NEXT: vmovapd %xmm1, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_i32gather_pd:
; X64: # BB#0:
; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-NEXT: vgatherdpd %xmm2, (%rdi,%xmm0,2), %xmm1
; X64-NEXT: vmovapd %xmm1, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast double *%a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%cmp = fcmp oeq <2 x double> zeroinitializer, zeroinitializer
declare <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double>, i8*, <4 x i32>, <2 x double>, i8) nounwind readonly
define <2 x double> @test_mm_mask_i32gather_pd(<2 x double> %a0, double *%a1, <2 x i64> %a2, <2 x double> %a3) {
-; X32-LABEL: test_mm_mask_i32gather_pd:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vgatherdpd %xmm2, (%eax,%xmm1,2), %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_mask_i32gather_pd:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vgatherdpd %xmm2, (%eax,%xmm1,2), %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_mask_i32gather_pd:
; X64: # BB#0:
; X64-NEXT: vgatherdpd %xmm2, (%rdi,%xmm1,2), %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast double *%a1 to i8*
%arg2 = bitcast <2 x i64> %a2 to <4 x i32>
%res = call <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double> %a0, i8* %arg1, <4 x i32> %arg2, <2 x double> %a3, i8 2)
}
define <4 x double> @test_mm256_i32gather_pd(double *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_i32gather_pd:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; X32-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2
-; X32-NEXT: vgatherdpd %ymm2, (%eax,%xmm0,2), %ymm1
-; X32-NEXT: vmovapd %ymm1, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_i32gather_pd:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; X86-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2
+; X86-NEXT: vgatherdpd %ymm2, (%eax,%xmm0,2), %ymm1
+; X86-NEXT: vmovapd %ymm1, %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_i32gather_pd:
; X64: # BB#0:
; X64-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2
; X64-NEXT: vgatherdpd %ymm2, (%rdi,%xmm0,2), %ymm1
; X64-NEXT: vmovapd %ymm1, %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast double *%a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%mask = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> zeroinitializer, <4 x double> zeroinitializer, i8 0)
declare <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double>, i8*, <4 x i32>, <4 x double>, i8) nounwind readonly
define <4 x double> @test_mm256_mask_i32gather_pd(<4 x double> %a0, double *%a1, <2 x i64> %a2, <4 x double> %a3) {
-; X32-LABEL: test_mm256_mask_i32gather_pd:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vgatherdpd %ymm2, (%eax,%xmm1,2), %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_mask_i32gather_pd:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vgatherdpd %ymm2, (%eax,%xmm1,2), %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_mask_i32gather_pd:
; X64: # BB#0:
; X64-NEXT: vgatherdpd %ymm2, (%rdi,%xmm1,2), %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast double *%a1 to i8*
%arg2 = bitcast <2 x i64> %a2 to <4 x i32>
%res = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> %a0, i8* %arg1, <4 x i32> %arg2, <4 x double> %a3, i8 2)
}
define <4 x float> @test_mm_i32gather_ps(float *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_i32gather_ps:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; X32-NEXT: vgatherdps %xmm2, (%eax,%xmm0,2), %xmm1
-; X32-NEXT: vmovaps %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_i32gather_ps:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; X86-NEXT: vgatherdps %xmm2, (%eax,%xmm0,2), %xmm1
+; X86-NEXT: vmovaps %xmm1, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_i32gather_ps:
; X64: # BB#0:
; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vgatherdps %xmm2, (%rdi,%xmm0,2), %xmm1
; X64-NEXT: vmovaps %xmm1, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast float *%a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%cmp = fcmp oeq <4 x float> zeroinitializer, zeroinitializer
declare <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float>, i8*, <4 x i32>, <4 x float>, i8) nounwind readonly
define <4 x float> @test_mm_mask_i32gather_ps(<4 x float> %a0, float *%a1, <2 x i64> %a2, <4 x float> %a3) {
-; X32-LABEL: test_mm_mask_i32gather_ps:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vgatherdps %xmm2, (%eax,%xmm1,2), %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_mask_i32gather_ps:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vgatherdps %xmm2, (%eax,%xmm1,2), %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_mask_i32gather_ps:
; X64: # BB#0:
; X64-NEXT: vgatherdps %xmm2, (%rdi,%xmm1,2), %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast float *%a1 to i8*
%arg2 = bitcast <2 x i64> %a2 to <4 x i32>
%call = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> %a0, i8* %arg1, <4 x i32> %arg2, <4 x float> %a3, i8 2)
}
define <8 x float> @test_mm256_i32gather_ps(float *%a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_i32gather_ps:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; X32-NEXT: vcmpeqps %ymm1, %ymm1, %ymm2
-; X32-NEXT: vgatherdps %ymm2, (%eax,%ymm0,2), %ymm1
-; X32-NEXT: vmovaps %ymm1, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_i32gather_ps:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; X86-NEXT: vcmpeqps %ymm1, %ymm1, %ymm2
+; X86-NEXT: vgatherdps %ymm2, (%eax,%ymm0,2), %ymm1
+; X86-NEXT: vmovaps %ymm1, %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_i32gather_ps:
; X64: # BB#0:
; X64-NEXT: vcmpeqps %ymm1, %ymm1, %ymm2
; X64-NEXT: vgatherdps %ymm2, (%rdi,%ymm0,2), %ymm1
; X64-NEXT: vmovaps %ymm1, %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast float *%a0 to i8*
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%mask = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> zeroinitializer, <8 x float> zeroinitializer, i8 0)
declare <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float>, i8*, <8 x i32>, <8 x float>, i8) nounwind readonly
define <8 x float> @test_mm256_mask_i32gather_ps(<8 x float> %a0, float *%a1, <4 x i64> %a2, <8 x float> %a3) {
-; X32-LABEL: test_mm256_mask_i32gather_ps:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vgatherdps %ymm2, (%eax,%ymm1,2), %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_mask_i32gather_ps:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vgatherdps %ymm2, (%eax,%ymm1,2), %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_mask_i32gather_ps:
; X64: # BB#0:
; X64-NEXT: vgatherdps %ymm2, (%rdi,%ymm1,2), %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast float *%a1 to i8*
%arg2 = bitcast <4 x i64> %a2 to <8 x i32>
%call = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> %a0, i8* %arg1, <8 x i32> %arg2, <8 x float> %a3, i8 2)
}
define <2 x i64> @test_mm_i64gather_epi32(i32 *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_i64gather_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpgatherqd %xmm2, (%eax,%xmm0,2), %xmm1
-; X32-NEXT: vmovdqa %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_i64gather_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpgatherqd %xmm2, (%eax,%xmm0,2), %xmm1
+; X86-NEXT: vmovdqa %xmm1, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_i64gather_epi32:
; X64: # BB#0:
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherqd %xmm2, (%rdi,%xmm0,2), %xmm1
; X64-NEXT: vmovdqa %xmm1, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i32 *%a0 to i8*
%mask = bitcast <2 x i64> <i64 -1, i64 -1> to <4 x i32>
%call = call <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32> undef, i8* %arg0, <2 x i64> %a1, <4 x i32> %mask, i8 2)
declare <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32>, i8*, <2 x i64>, <4 x i32>, i8) nounwind readonly
define <2 x i64> @test_mm_mask_i64gather_epi32(<2 x i64> %a0, i32 *%a1, <2 x i64> %a2, <2 x i64> %a3) {
-; X32-LABEL: test_mm_mask_i64gather_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpgatherqd %xmm2, (%eax,%xmm1,2), %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_mask_i64gather_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpgatherqd %xmm2, (%eax,%xmm1,2), %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_mask_i64gather_epi32:
; X64: # BB#0:
; X64-NEXT: vpgatherqd %xmm2, (%rdi,%xmm1,2), %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%arg1 = bitcast i32 *%a1 to i8*
%arg3 = bitcast <2 x i64> %a3 to <4 x i32>
}
define <2 x i64> @test_mm256_i64gather_epi32(i32 *%a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_i64gather_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpgatherqd %xmm2, (%eax,%ymm0,2), %xmm1
-; X32-NEXT: vmovdqa %xmm1, %xmm0
-; X32-NEXT: vzeroupper
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_i64gather_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpgatherqd %xmm2, (%eax,%ymm0,2), %xmm1
+; X86-NEXT: vmovdqa %xmm1, %xmm0
+; X86-NEXT: vzeroupper
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_i64gather_epi32:
; X64: # BB#0:
; X64-NEXT: vpgatherqd %xmm2, (%rdi,%ymm0,2), %xmm1
; X64-NEXT: vmovdqa %xmm1, %xmm0
; X64-NEXT: vzeroupper
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i32 *%a0 to i8*
%mask = bitcast <2 x i64> <i64 -1, i64 -1> to <4 x i32>
%call = call <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32> undef, i8* %arg0, <4 x i64> %a1, <4 x i32> %mask, i8 2)
declare <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32>, i8*, <4 x i64>, <4 x i32>, i8) nounwind readonly
define <2 x i64> @test_mm256_mask_i64gather_epi32(<2 x i64> %a0, i32 *%a1, <4 x i64> %a2, <2 x i64> %a3) {
-; X32-LABEL: test_mm256_mask_i64gather_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpgatherqd %xmm2, (%eax,%ymm1,2), %xmm0
-; X32-NEXT: vzeroupper
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_mask_i64gather_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpgatherqd %xmm2, (%eax,%ymm1,2), %xmm0
+; X86-NEXT: vzeroupper
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_mask_i64gather_epi32:
; X64: # BB#0:
; X64-NEXT: vpgatherqd %xmm2, (%rdi,%ymm1,2), %xmm0
; X64-NEXT: vzeroupper
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%arg1 = bitcast i32 *%a1 to i8*
%arg3 = bitcast <2 x i64> %a3 to <4 x i32>
}
define <2 x i64> @test_mm_i64gather_epi64(i64 *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_i64gather_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpgatherqq %xmm2, (%eax,%xmm0,2), %xmm1
-; X32-NEXT: vmovdqa %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_i64gather_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpgatherqq %xmm2, (%eax,%xmm0,2), %xmm1
+; X86-NEXT: vmovdqa %xmm1, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_i64gather_epi64:
; X64: # BB#0:
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherqq %xmm2, (%rdi,%xmm0,2), %xmm1
; X64-NEXT: vmovdqa %xmm1, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i64 *%a0 to i8*
%call = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> undef, i8* %arg0, <2 x i64> %a1, <2 x i64> <i64 -1, i64 -1>, i8 2)
ret <2 x i64> %call
declare <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64>, i8*, <2 x i64>, <2 x i64>, i8) nounwind readonly
define <2 x i64> @test_mm_mask_i64gather_epi64(<2 x i64> %a0, i64 *%a1, <2 x i64> %a2, <2 x i64> %a3) {
-; X32-LABEL: test_mm_mask_i64gather_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpgatherqq %xmm2, (%eax,%xmm1,2), %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_mask_i64gather_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpgatherqq %xmm2, (%eax,%xmm1,2), %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_mask_i64gather_epi64:
; X64: # BB#0:
; X64-NEXT: vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast i64 *%a1 to i8*
%call = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> %a0, i8* %arg1, <2 x i64> %a2, <2 x i64> %a3, i8 2)
ret <2 x i64> %call
}
define <4 x i64> @test_mm256_i64gather_epi64(i64 *%a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_i64gather_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpgatherqq %ymm2, (%eax,%ymm0,2), %ymm1
-; X32-NEXT: vmovdqa %ymm1, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_i64gather_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpgatherqq %ymm2, (%eax,%ymm0,2), %ymm1
+; X86-NEXT: vmovdqa %ymm1, %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_i64gather_epi64:
; X64: # BB#0:
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherqq %ymm2, (%rdi,%ymm0,2), %ymm1
; X64-NEXT: vmovdqa %ymm1, %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i64 *%a0 to i8*
%call = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> undef, i8* %arg0, <4 x i64> %a1, <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, i8 2)
ret <4 x i64> %call
declare <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64>, i8*, <4 x i64>, <4 x i64>, i8) nounwind readonly
define <4 x i64> @test_mm256_mask_i64gather_epi64(<4 x i64> %a0, i64 *%a1, <4 x i64> %a2, <4 x i64> %a3) {
-; X32-LABEL: test_mm256_mask_i64gather_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpgatherqq %ymm2, (%eax,%ymm1,2), %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_mask_i64gather_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpgatherqq %ymm2, (%eax,%ymm1,2), %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_mask_i64gather_epi64:
; X64: # BB#0:
; X64-NEXT: vpgatherqq %ymm2, (%rdi,%ymm1,2), %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast i64 *%a1 to i8*
%call = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> %a0, i8* %arg1, <4 x i64> %a2, <4 x i64> %a3, i8 2)
ret <4 x i64> %call
}
define <2 x double> @test_mm_i64gather_pd(double *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_i64gather_pd:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; X32-NEXT: vgatherqpd %xmm2, (%eax,%xmm0,2), %xmm1
-; X32-NEXT: vmovapd %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_i64gather_pd:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; X86-NEXT: vgatherqpd %xmm2, (%eax,%xmm0,2), %xmm1
+; X86-NEXT: vmovapd %xmm1, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_i64gather_pd:
; X64: # BB#0:
; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-NEXT: vgatherqpd %xmm2, (%rdi,%xmm0,2), %xmm1
; X64-NEXT: vmovapd %xmm1, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast double *%a0 to i8*
%cmp = fcmp oeq <2 x double> zeroinitializer, zeroinitializer
%sext = sext <2 x i1> %cmp to <2 x i64>
declare <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double>, i8*, <2 x i64>, <2 x double>, i8) nounwind readonly
define <2 x double> @test_mm_mask_i64gather_pd(<2 x double> %a0, double *%a1, <2 x i64> %a2, <2 x double> %a3) {
-; X32-LABEL: test_mm_mask_i64gather_pd:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vgatherqpd %xmm2, (%eax,%xmm1,2), %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_mask_i64gather_pd:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vgatherqpd %xmm2, (%eax,%xmm1,2), %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_mask_i64gather_pd:
; X64: # BB#0:
; X64-NEXT: vgatherqpd %xmm2, (%rdi,%xmm1,2), %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast double *%a1 to i8*
%call = call <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double> %a0, i8* %arg1, <2 x i64> %a2, <2 x double> %a3, i8 2)
ret <2 x double> %call
}
define <4 x double> @test_mm256_i64gather_pd(double *%a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_i64gather_pd:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; X32-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2
-; X32-NEXT: vgatherqpd %ymm2, (%eax,%ymm0,2), %ymm1
-; X32-NEXT: vmovapd %ymm1, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_i64gather_pd:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; X86-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2
+; X86-NEXT: vgatherqpd %ymm2, (%eax,%ymm0,2), %ymm1
+; X86-NEXT: vmovapd %ymm1, %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_i64gather_pd:
; X64: # BB#0:
; X64-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2
; X64-NEXT: vgatherqpd %ymm2, (%rdi,%ymm0,2), %ymm1
; X64-NEXT: vmovapd %ymm1, %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast double *%a0 to i8*
%mask = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> zeroinitializer, <4 x double> zeroinitializer, i8 0)
%call = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> undef, i8* %arg0, <4 x i64> %a1, <4 x double> %mask, i8 2)
declare <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double>, i8*, <4 x i64>, <4 x double>, i8) nounwind readonly
define <4 x double> @test_mm256_mask_i64gather_pd(<4 x double> %a0, i64 *%a1, <4 x i64> %a2, <4 x double> %a3) {
-; X32-LABEL: test_mm256_mask_i64gather_pd:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vgatherqpd %ymm2, (%eax,%ymm1,2), %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_mask_i64gather_pd:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vgatherqpd %ymm2, (%eax,%ymm1,2), %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_mask_i64gather_pd:
; X64: # BB#0:
; X64-NEXT: vgatherqpd %ymm2, (%rdi,%ymm1,2), %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast i64 *%a1 to i8*
%call = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> %a0, i8* %arg1, <4 x i64> %a2, <4 x double> %a3, i8 2)
ret <4 x double> %call
}
define <4 x float> @test_mm_i64gather_ps(float *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_i64gather_ps:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; X32-NEXT: vgatherqps %xmm2, (%eax,%xmm0,2), %xmm1
-; X32-NEXT: vmovaps %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_i64gather_ps:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; X86-NEXT: vgatherqps %xmm2, (%eax,%xmm0,2), %xmm1
+; X86-NEXT: vmovaps %xmm1, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_i64gather_ps:
; X64: # BB#0:
; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vgatherqps %xmm2, (%rdi,%xmm0,2), %xmm1
; X64-NEXT: vmovaps %xmm1, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast float *%a0 to i8*
%cmp = fcmp oeq <4 x float> zeroinitializer, zeroinitializer
%sext = sext <4 x i1> %cmp to <4 x i32>
declare <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float>, i8*, <2 x i64>, <4 x float>, i8) nounwind readonly
define <4 x float> @test_mm_mask_i64gather_ps(<4 x float> %a0, float *%a1, <2 x i64> %a2, <4 x float> %a3) {
-; X32-LABEL: test_mm_mask_i64gather_ps:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vgatherqps %xmm2, (%eax,%xmm1,2), %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_mask_i64gather_ps:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vgatherqps %xmm2, (%eax,%xmm1,2), %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_mask_i64gather_ps:
; X64: # BB#0:
; X64-NEXT: vgatherqps %xmm2, (%rdi,%xmm1,2), %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast float *%a1 to i8*
%call = call <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float> %a0, i8* %arg1, <2 x i64> %a2, <4 x float> %a3, i8 2)
ret <4 x float> %call
}
define <4 x float> @test_mm256_i64gather_ps(float *%a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_i64gather_ps:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; X32-NEXT: vgatherqps %xmm2, (%eax,%ymm0,2), %xmm1
-; X32-NEXT: vmovaps %xmm1, %xmm0
-; X32-NEXT: vzeroupper
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_i64gather_ps:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; X86-NEXT: vgatherqps %xmm2, (%eax,%ymm0,2), %xmm1
+; X86-NEXT: vmovaps %xmm1, %xmm0
+; X86-NEXT: vzeroupper
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_i64gather_ps:
; X64: # BB#0:
; X64-NEXT: vgatherqps %xmm2, (%rdi,%ymm0,2), %xmm1
; X64-NEXT: vmovaps %xmm1, %xmm0
; X64-NEXT: vzeroupper
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast float *%a0 to i8*
%cmp = fcmp oeq <4 x float> zeroinitializer, zeroinitializer
%sext = sext <4 x i1> %cmp to <4 x i32>
declare <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float>, i8*, <4 x i64>, <4 x float>, i8) nounwind readonly
define <4 x float> @test_mm256_mask_i64gather_ps(<4 x float> %a0, float *%a1, <4 x i64> %a2, <4 x float> %a3) {
-; X32-LABEL: test_mm256_mask_i64gather_ps:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vgatherqps %xmm2, (%eax,%ymm1,2), %xmm0
-; X32-NEXT: vzeroupper
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_mask_i64gather_ps:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vgatherqps %xmm2, (%eax,%ymm1,2), %xmm0
+; X86-NEXT: vzeroupper
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_mask_i64gather_ps:
; X64: # BB#0:
; X64-NEXT: vgatherqps %xmm2, (%rdi,%ymm1,2), %xmm0
; X64-NEXT: vzeroupper
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast float *%a1 to i8*
%call = call <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float> %a0, i8* %arg1, <4 x i64> %a2, <4 x float> %a3, i8 2)
ret <4 x float> %call
}
define <4 x i64> @test0_mm256_inserti128_si256(<4 x i64> %a0, <2 x i64> %a1) nounwind {
-; X32-LABEL: test0_mm256_inserti128_si256:
-; X32: # BB#0:
-; X32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
-; X32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
-; X32-NEXT: retl
-;
-; X64-LABEL: test0_mm256_inserti128_si256:
-; X64: # BB#0:
-; X64-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
-; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
-; X64-NEXT: retq
+; CHECK-LABEL: test0_mm256_inserti128_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
+; CHECK-NEXT: ret{{[l|q]}}
%ext = shufflevector <2 x i64> %a1, <2 x i64> %a1, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%res = shufflevector <4 x i64> %a0, <4 x i64> %ext, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
ret <4 x i64> %res
}
define <4 x i64> @test1_mm256_inserti128_si256(<4 x i64> %a0, <2 x i64> %a1) nounwind {
-; X32-LABEL: test1_mm256_inserti128_si256:
-; X32: # BB#0:
-; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test1_mm256_inserti128_si256:
-; X64: # BB#0:
-; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test1_mm256_inserti128_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%ext = shufflevector <2 x i64> %a1, <2 x i64> %a1, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%res = shufflevector <4 x i64> %a0, <4 x i64> %ext, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_madd_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_madd_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_madd_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_madd_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %arg0, <16 x i16> %arg1)
declare <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_maddubs_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_maddubs_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_maddubs_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_maddubs_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> %arg0, <32 x i8> %arg1)
declare <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8>, <32 x i8>) nounwind readnone
define <2 x i64> @test_mm_maskload_epi32(i32* %a0, <2 x i64> %a1) nounwind {
-; X32-LABEL: test_mm_maskload_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmaskmovd (%eax), %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_maskload_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaskmovd (%eax), %xmm0, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_maskload_epi32:
; X64: # BB#0:
; X64-NEXT: vpmaskmovd (%rdi), %xmm0, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i32* %a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%call = call <4 x i32> @llvm.x86.avx2.maskload.d(i8* %arg0, <4 x i32> %arg1)
declare <4 x i32> @llvm.x86.avx2.maskload.d(i8*, <4 x i32>) nounwind readonly
define <4 x i64> @test_mm256_maskload_epi32(i32* %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_maskload_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmaskmovd (%eax), %ymm0, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_maskload_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaskmovd (%eax), %ymm0, %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_maskload_epi32:
; X64: # BB#0:
; X64-NEXT: vpmaskmovd (%rdi), %ymm0, %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i32* %a0 to i8*
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%call = call <8 x i32> @llvm.x86.avx2.maskload.d.256(i8* %arg0, <8 x i32> %arg1)
declare <8 x i32> @llvm.x86.avx2.maskload.d.256(i8*, <8 x i32>) nounwind readonly
define <2 x i64> @test_mm_maskload_epi64(i64* %a0, <2 x i64> %a1) nounwind {
-; X32-LABEL: test_mm_maskload_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmaskmovq (%eax), %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_maskload_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaskmovq (%eax), %xmm0, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_maskload_epi64:
; X64: # BB#0:
; X64-NEXT: vpmaskmovq (%rdi), %xmm0, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i64* %a0 to i8*
%res = call <2 x i64> @llvm.x86.avx2.maskload.q(i8* %arg0, <2 x i64> %a1)
ret <2 x i64> %res
declare <2 x i64> @llvm.x86.avx2.maskload.q(i8*, <2 x i64>) nounwind readonly
define <4 x i64> @test_mm256_maskload_epi64(i64* %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_maskload_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmaskmovq (%eax), %ymm0, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_maskload_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaskmovq (%eax), %ymm0, %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_maskload_epi64:
; X64: # BB#0:
; X64-NEXT: vpmaskmovq (%rdi), %ymm0, %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i64* %a0 to i8*
%res = call <4 x i64> @llvm.x86.avx2.maskload.q.256(i8* %arg0, <4 x i64> %a1)
ret <4 x i64> %res
declare <4 x i64> @llvm.x86.avx2.maskload.q.256(i8*, <4 x i64>) nounwind readonly
define void @test_mm_maskstore_epi32(float* %a0, <2 x i64> %a1, <2 x i64> %a2) nounwind {
-; X32-LABEL: test_mm_maskstore_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmaskmovd %xmm1, %xmm0, (%eax)
-; X32-NEXT: retl
+; X86-LABEL: test_mm_maskstore_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaskmovd %xmm1, %xmm0, (%eax)
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_maskstore_epi32:
; X64: # BB#0:
; X64-NEXT: vpmaskmovd %xmm1, %xmm0, (%rdi)
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast float* %a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%arg2 = bitcast <2 x i64> %a2 to <4 x i32>
declare void @llvm.x86.avx2.maskstore.d(i8*, <4 x i32>, <4 x i32>) nounwind readnone
define void @test_mm256_maskstore_epi32(float* %a0, <4 x i64> %a1, <4 x i64> %a2) nounwind {
-; X32-LABEL: test_mm256_maskstore_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmaskmovd %ymm1, %ymm0, (%eax)
-; X32-NEXT: vzeroupper
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_maskstore_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaskmovd %ymm1, %ymm0, (%eax)
+; X86-NEXT: vzeroupper
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_maskstore_epi32:
; X64: # BB#0:
; X64-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi)
; X64-NEXT: vzeroupper
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast float* %a0 to i8*
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%arg2 = bitcast <4 x i64> %a2 to <8 x i32>
declare void @llvm.x86.avx2.maskstore.d.256(i8*, <8 x i32>, <8 x i32>) nounwind readnone
define void @test_mm_maskstore_epi64(i64* %a0, <2 x i64> %a1, <2 x i64> %a2) nounwind {
-; X32-LABEL: test_mm_maskstore_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmaskmovq %xmm1, %xmm0, (%eax)
-; X32-NEXT: retl
+; X86-LABEL: test_mm_maskstore_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaskmovq %xmm1, %xmm0, (%eax)
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_maskstore_epi64:
; X64: # BB#0:
; X64-NEXT: vpmaskmovq %xmm1, %xmm0, (%rdi)
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i64* %a0 to i8*
call void @llvm.x86.avx2.maskstore.q(i8* %arg0, <2 x i64> %a1, <2 x i64> %a2)
ret void
declare void @llvm.x86.avx2.maskstore.q(i8*, <2 x i64>, <2 x i64>) nounwind readnone
define void @test_mm256_maskstore_epi64(i64* %a0, <4 x i64> %a1, <4 x i64> %a2) nounwind {
-; X32-LABEL: test_mm256_maskstore_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmaskmovq %ymm1, %ymm0, (%eax)
-; X32-NEXT: vzeroupper
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_maskstore_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaskmovq %ymm1, %ymm0, (%eax)
+; X86-NEXT: vzeroupper
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_maskstore_epi64:
; X64: # BB#0:
; X64-NEXT: vpmaskmovq %ymm1, %ymm0, (%rdi)
; X64-NEXT: vzeroupper
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i64* %a0 to i8*
call void @llvm.x86.avx2.maskstore.q.256(i8* %arg0, <4 x i64> %a1, <4 x i64> %a2)
ret void
declare void @llvm.x86.avx2.maskstore.q.256(i8*, <4 x i64>, <4 x i64>) nounwind readnone
define <4 x i64> @test_mm256_max_epi8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_max_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_max_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_max_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%cmp = icmp sgt <32 x i8> %arg0, %arg1
}
define <4 x i64> @test_mm256_max_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_max_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_max_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_max_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%cmp = icmp sgt <16 x i16> %arg0, %arg1
}
define <4 x i64> @test_mm256_max_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_max_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_max_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_max_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%cmp = icmp sgt <8 x i32> %arg0, %arg1
}
define <4 x i64> @test_mm256_max_epu8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_max_epu8:
-; X32: # BB#0:
-; X32-NEXT: vpmaxub %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_max_epu8:
-; X64: # BB#0:
-; X64-NEXT: vpmaxub %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_max_epu8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaxub %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%cmp = icmp ugt <32 x i8> %arg0, %arg1
}
define <4 x i64> @test_mm256_max_epu16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_max_epu16:
-; X32: # BB#0:
-; X32-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_max_epu16:
-; X64: # BB#0:
-; X64-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_max_epu16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%cmp = icmp ugt <16 x i16> %arg0, %arg1
}
define <4 x i64> @test_mm256_max_epu32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_max_epu32:
-; X32: # BB#0:
-; X32-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_max_epu32:
-; X64: # BB#0:
-; X64-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_max_epu32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%cmp = icmp ugt <8 x i32> %arg0, %arg1
}
define <4 x i64> @test_mm256_min_epi8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_min_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpminsb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_min_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpminsb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_min_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpminsb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%cmp = icmp slt <32 x i8> %arg0, %arg1
}
define <4 x i64> @test_mm256_min_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_min_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpminsw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_min_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpminsw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_min_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpminsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%cmp = icmp slt <16 x i16> %arg0, %arg1
}
define <4 x i64> @test_mm256_min_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_min_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpminsd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_min_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpminsd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_min_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpminsd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%cmp = icmp slt <8 x i32> %arg0, %arg1
}
define <4 x i64> @test_mm256_min_epu8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_min_epu8:
-; X32: # BB#0:
-; X32-NEXT: vpminub %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_min_epu8:
-; X64: # BB#0:
-; X64-NEXT: vpminub %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_min_epu8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpminub %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%cmp = icmp ult <32 x i8> %arg0, %arg1
}
define <4 x i64> @test_mm256_min_epu16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_min_epu16:
-; X32: # BB#0:
-; X32-NEXT: vpminuw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_min_epu16:
-; X64: # BB#0:
-; X64-NEXT: vpminuw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_min_epu16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpminuw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%cmp = icmp ult <16 x i16> %arg0, %arg1
}
define <4 x i64> @test_mm256_min_epu32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_min_epu32:
-; X32: # BB#0:
-; X32-NEXT: vpminud %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_min_epu32:
-; X64: # BB#0:
-; X64-NEXT: vpminud %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_min_epu32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpminud %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%cmp = icmp ult <8 x i32> %arg0, %arg1
}
define i32 @test_mm256_movemask_epi8(<4 x i64> %a0) nounwind {
-; X32-LABEL: test_mm256_movemask_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpmovmskb %ymm0, %eax
-; X32-NEXT: vzeroupper
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_movemask_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpmovmskb %ymm0, %eax
-; X64-NEXT: vzeroupper
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_movemask_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovmskb %ymm0, %eax
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%res = call i32 @llvm.x86.avx2.pmovmskb(<32 x i8> %arg0)
ret i32 %res
declare i32 @llvm.x86.avx2.pmovmskb(<32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_mpsadbw_epu8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_mpsadbw_epu8:
-; X32: # BB#0:
-; X32-NEXT: vmpsadbw $3, %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_mpsadbw_epu8:
-; X64: # BB#0:
-; X64-NEXT: vmpsadbw $3, %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_mpsadbw_epu8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmpsadbw $3, %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%call = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> %arg0, <32 x i8> %arg1, i8 3)
declare <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8>, <32 x i8>, i8) nounwind readnone
define <4 x i64> @test_mm256_mul_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_mul_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpmuldq %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_mul_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpmuldq %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_mul_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmuldq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = call <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32> %arg0, <8 x i32> %arg1)
declare <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32>, <8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_mul_epu32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_mul_epu32:
-; X32: # BB#0:
-; X32-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_mul_epu32:
-; X64: # BB#0:
-; X64-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_mul_epu32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = call <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32> %arg0, <8 x i32> %arg1)
declare <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32>, <8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_mulhi_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_mulhi_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpmulhw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_mulhi_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpmulhw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_mulhi_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmulhw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %arg0, <16 x i16> %arg1)
declare <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_mulhi_epu16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_mulhi_epu16:
-; X32: # BB#0:
-; X32-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_mulhi_epu16:
-; X64: # BB#0:
-; X64-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_mulhi_epu16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %arg0, <16 x i16> %arg1)
declare <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_mulhrs_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_mulhrs_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_mulhrs_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_mulhrs_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.pmul.hr.sw(<16 x i16> %arg0, <16 x i16> %arg1)
declare <16 x i16> @llvm.x86.avx2.pmul.hr.sw(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_mullo_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_mullo_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpmullw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_mullo_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpmullw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_mullo_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmullw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = mul <16 x i16> %arg0, %arg1
}
define <4 x i64> @test_mm256_mullo_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_mullo_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpmulld %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_mullo_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpmulld %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_mullo_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmulld %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = mul <8 x i32> %arg0, %arg1
}
define <4 x i64> @test_mm256_or_si256(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_or_si256:
-; X32: # BB#0:
-; X32-NEXT: vorps %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_or_si256:
-; X64: # BB#0:
-; X64-NEXT: vorps %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_or_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vorps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = or <4 x i64> %a0, %a1
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_packs_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_packs_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpacksswb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_packs_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpacksswb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_packs_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpacksswb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%call = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> %arg0, <16 x i16> %arg1)
declare <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_packs_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_packs_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpackssdw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_packs_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpackssdw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_packs_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpackssdw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%call = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %arg0, <8 x i32> %arg1)
declare <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32>, <8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_packus_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_packus_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpackuswb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_packus_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpackuswb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_packus_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpackuswb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%call = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> %arg0, <16 x i16> %arg1)
declare <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_packus_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_packus_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpackusdw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_packus_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpackusdw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_packus_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpackusdw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%call = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> %arg0, <8 x i32> %arg1)
declare <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32>, <8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_permute2x128_si256(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_permute2x128_si256:
-; X32: # BB#0:
-; X32-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_permute2x128_si256:
-; X64: # BB#0:
-; X64-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_permute2x128_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x i64> %a0, <4 x i64> %a1, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
ret <4 x i64> %res
}
declare <4 x i64> @llvm.x86.avx2.vperm2i128(<4 x i64>, <4 x i64>, i8) nounwind readonly
define <4 x i64> @test_mm256_permute4x64_epi64(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_permute4x64_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,0,2,0]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_permute4x64_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,0,2,0]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_permute4x64_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,0,2,0]
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 3, i32 0, i32 2, i32 0>
ret <4 x i64> %res
}
define <4 x double> @test_mm256_permute4x64_pd(<4 x double> %a0) {
-; X32-LABEL: test_mm256_permute4x64_pd:
-; X32: # BB#0:
-; X32-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[1,2,1,0]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_permute4x64_pd:
-; X64: # BB#0:
-; X64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[1,2,1,0]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_permute4x64_pd:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[1,2,1,0]
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 1, i32 2, i32 1, i32 0>
ret <4 x double> %res
}
define <4 x i64> @test_mm256_permutevar8x32_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_permutevar8x32_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_permutevar8x32_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_permutevar8x32_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%call = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %arg0, <8 x i32> %arg1)
declare <8 x i32> @llvm.x86.avx2.permd(<8 x i32>, <8 x i32>) nounwind readonly
define <8 x float> @test_mm256_permutevar8x32_ps(<8 x float> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_permutevar8x32_ps:
-; X32: # BB#0:
-; X32-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_permutevar8x32_ps:
-; X64: # BB#0:
-; X64-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_permutevar8x32_ps:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> %arg1)
ret <8 x float> %res
declare <8 x float> @llvm.x86.avx2.permps(<8 x float>, <8 x i32>) nounwind readonly
define <4 x i64> @test_mm256_sad_epu8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_sad_epu8:
-; X32: # BB#0:
-; X32-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sad_epu8:
-; X64: # BB#0:
-; X64-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sad_epu8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = call <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8> %arg0, <32 x i8> %arg1)
declare <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8>, <32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_shuffle_epi32(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_shuffle_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,3,0,0,7,7,4,4]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_shuffle_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,3,0,0,7,7,4,4]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_shuffle_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,3,0,0,7,7,4,4]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%shuf = shufflevector <8 x i32> %arg0, <8 x i32> undef, <8 x i32> <i32 3, i32 3, i32 0, i32 0, i32 7, i32 7, i32 4, i32 4>
%res = bitcast <8 x i32> %shuf to <4 x i64>
}
define <4 x i64> @test_mm256_shuffle_epi8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_shuffle_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_shuffle_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_shuffle_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpshufb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%shuf = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %arg0, <32 x i8> %arg1)
declare <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8>, <32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_shufflehi_epi16(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_shufflehi_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,7,6,6,5,8,9,10,11,15,14,14,13]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_shufflehi_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,7,6,6,5,8,9,10,11,15,14,14,13]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_shufflehi_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,7,6,6,5,8,9,10,11,15,14,14,13]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%shuf = shufflevector <16 x i16> %arg0, <16 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 6, i32 6, i32 5, i32 8, i32 9, i32 10, i32 11, i32 15, i32 14, i32 14, i32 13>
%res = bitcast <16 x i16> %shuf to <4 x i64>
}
define <4 x i64> @test_mm256_shufflelo_epi16(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_shufflelo_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[3,0,1,1,4,5,6,7,11,8,9,9,12,13,14,15]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_shufflelo_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[3,0,1,1,4,5,6,7,11,8,9,9,12,13,14,15]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_shufflelo_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[3,0,1,1,4,5,6,7,11,8,9,9,12,13,14,15]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%shuf = shufflevector <16 x i16> %arg0, <16 x i16> undef, <16 x i32> <i32 3, i32 0, i32 1, i32 1, i32 4, i32 5, i32 6, i32 7, i32 11, i32 8, i32 9, i32 9, i32 12, i32 13, i32 14, i32 15>
%res = bitcast <16 x i16> %shuf to <4 x i64>
}
define <4 x i64> @test_mm256_sign_epi8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_sign_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpsignb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sign_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpsignb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sign_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsignb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%call = call <32 x i8> @llvm.x86.avx2.psign.b(<32 x i8> %arg0, <32 x i8> %arg1)
declare <32 x i8> @llvm.x86.avx2.psign.b(<32 x i8>, <32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_sign_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_sign_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsignw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sign_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsignw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sign_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsignw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%call = call <16 x i16> @llvm.x86.avx2.psign.w(<16 x i16> %arg0, <16 x i16> %arg1)
declare <16 x i16> @llvm.x86.avx2.psign.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_sign_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_sign_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsignd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sign_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsignd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sign_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsignd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%call = call <8 x i32> @llvm.x86.avx2.psign.d(<8 x i32> %arg0, <8 x i32> %arg1)
declare <8 x i32> @llvm.x86.avx2.psign.d(<8 x i32>, <8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_sll_epi16(<4 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_sll_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsllw %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sll_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsllw %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sll_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsllw %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <2 x i64> %a1 to <8 x i16>
%res = call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %arg0, <8 x i16> %arg1)
declare <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16>, <8 x i16>) nounwind readnone
define <4 x i64> @test_mm256_sll_epi32(<4 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_sll_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpslld %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sll_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpslld %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sll_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpslld %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %arg0, <4 x i32> %arg1)
declare <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32>, <4 x i32>) nounwind readnone
define <4 x i64> @test_mm256_sll_epi64(<4 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_sll_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsllq %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sll_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsllq %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sll_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsllq %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %a0, <2 x i64> %a1)
ret <4 x i64> %res
}
declare <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64>, <2 x i64>) nounwind readnone
define <4 x i64> @test_mm256_slli_epi16(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_slli_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsllw $3, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_slli_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsllw $3, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_slli_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsllw $3, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %arg0, i32 3)
%bc = bitcast <16 x i16> %res to <4 x i64>
declare <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16>, i32) nounwind readnone
define <4 x i64> @test_mm256_slli_epi32(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_slli_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpslld $3, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_slli_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpslld $3, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_slli_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpslld $3, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%res = call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %arg0, i32 3)
%bc = bitcast <8 x i32> %res to <4 x i64>
declare <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32>, i32) nounwind readnone
define <4 x i64> @test_mm256_slli_epi64(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_slli_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsllq $3, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_slli_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsllq $3, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_slli_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsllq $3, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %a0, i32 3)
ret <4 x i64> %res
}
declare <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64>, i32) nounwind readnone
define <4 x i64> @test_mm256_slli_si256(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_slli_si256:
-; X32: # BB#0:
-; X32-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12],zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_slli_si256:
-; X64: # BB#0:
-; X64-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12],zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_slli_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12],zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%shuf = shufflevector <32 x i8> zeroinitializer, <32 x i8> %arg0, <32 x i32> <i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60>
%res = bitcast <32 x i8> %shuf to <4 x i64>
}
define <2 x i64> @test_mm_sllv_epi32(<2 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_sllv_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_sllv_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_sllv_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %arg0, <4 x i32> %arg1)
declare <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x i64> @test_mm256_sllv_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_sllv_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sllv_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sllv_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %arg0, <8 x i32> %arg1)
declare <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32>, <8 x i32>) nounwind readnone
define <2 x i64> @test_mm_sllv_epi64(<2 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_sllv_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_sllv_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_sllv_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %a0, <2 x i64> %a1)
ret <2 x i64> %res
}
declare <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64>, <2 x i64>) nounwind readnone
define <4 x i64> @test_mm256_sllv_epi64(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_sllv_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsllvq %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sllv_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsllvq %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sllv_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsllvq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %a0, <4 x i64> %a1)
ret <4 x i64> %res
}
declare <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64>, <4 x i64>) nounwind readnone
define <4 x i64> @test_mm256_sra_epi16(<4 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_sra_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsraw %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sra_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsraw %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sra_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsraw %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <2 x i64> %a1 to <8 x i16>
%res = call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %arg0, <8 x i16> %arg1)
declare <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16>, <8 x i16>) nounwind readnone
define <4 x i64> @test_mm256_sra_epi32(<4 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_sra_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsrad %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sra_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsrad %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sra_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrad %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %arg0, <4 x i32> %arg1)
declare <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32>, <4 x i32>) nounwind readnone
define <4 x i64> @test_mm256_srai_epi16(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_srai_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsraw $3, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srai_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsraw $3, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srai_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsraw $3, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %arg0, i32 3)
%bc = bitcast <16 x i16> %res to <4 x i64>
declare <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16>, i32) nounwind readnone
define <4 x i64> @test_mm256_srai_epi32(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_srai_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsrad $3, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srai_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsrad $3, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srai_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrad $3, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%res = call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %arg0, i32 3)
%bc = bitcast <8 x i32> %res to <4 x i64>
declare <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32>, i32) nounwind readnone
define <2 x i64> @test_mm_srav_epi32(<2 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_srav_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsravd %xmm1, %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_srav_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsravd %xmm1, %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_srav_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsravd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %arg0, <4 x i32> %arg1)
declare <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x i64> @test_mm256_srav_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_srav_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsravd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srav_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsravd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srav_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsravd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %arg0, <8 x i32> %arg1)
declare <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32>, <8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_srl_epi16(<4 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_srl_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsrlw %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srl_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsrlw %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srl_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrlw %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <2 x i64> %a1 to <8 x i16>
%res = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %arg0, <8 x i16> %arg1)
declare <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16>, <8 x i16>) nounwind readnone
define <4 x i64> @test_mm256_srl_epi32(<4 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_srl_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsrld %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srl_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsrld %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srl_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrld %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %arg0, <4 x i32> %arg1)
declare <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32>, <4 x i32>) nounwind readnone
define <4 x i64> @test_mm256_srl_epi64(<4 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_srl_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsrlq %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srl_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsrlq %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srl_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrlq %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %a0, <2 x i64> %a1)
ret <4 x i64> %res
}
declare <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64>, <2 x i64>) nounwind readnone
define <4 x i64> @test_mm256_srli_epi16(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_srli_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsrlw $3, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srli_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsrlw $3, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srli_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrlw $3, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %arg0, i32 3)
%bc = bitcast <16 x i16> %res to <4 x i64>
declare <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16>, i32) nounwind readnone
define <4 x i64> @test_mm256_srli_epi32(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_srli_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsrld $3, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srli_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsrld $3, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srli_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrld $3, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%res = call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %arg0, i32 3)
%bc = bitcast <8 x i32> %res to <4 x i64>
declare <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32>, i32) nounwind readnone
define <4 x i64> @test_mm256_srli_epi64(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_srli_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsrlq $3, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srli_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsrlq $3, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srli_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrlq $3, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %a0, i32 3)
ret <4 x i64> %res
}
declare <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64>, i32) nounwind readnone
define <4 x i64> @test_mm256_srli_si256(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_srli_si256:
-; X32: # BB#0:
-; X32-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,ymm0[19,20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srli_si256:
-; X64: # BB#0:
-; X64-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,ymm0[19,20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srli_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,ymm0[19,20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%shuf = shufflevector <32 x i8> %arg0, <32 x i8> zeroinitializer, <32 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50>
%res = bitcast <32 x i8> %shuf to <4 x i64>
}
define <2 x i64> @test_mm_srlv_epi32(<2 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_srlv_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_srlv_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_srlv_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %arg0, <4 x i32> %arg1)
declare <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x i64> @test_mm256_srlv_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_srlv_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srlv_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srlv_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %arg0, <8 x i32> %arg1)
declare <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32>, <8 x i32>) nounwind readnone
define <2 x i64> @test_mm_srlv_epi64(<2 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_srlv_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_srlv_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_srlv_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %a0, <2 x i64> %a1)
ret <2 x i64> %res
}
declare <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64>, <2 x i64>) nounwind readnone
define <4 x i64> @test_mm256_srlv_epi64(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_srlv_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srlv_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srlv_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %a0, <4 x i64> %a1)
ret <4 x i64> %res
}
declare <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64>, <4 x i64>) nounwind readnone
define <4 x i64> @test_mm256_stream_load_si256(<4 x i64> *%a0) {
-; X32-LABEL: test_mm256_stream_load_si256:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vmovntdqa (%eax), %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_stream_load_si256:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vmovntdqa (%eax), %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_stream_load_si256:
; X64: # BB#0:
; X64-NEXT: vmovntdqa (%rdi), %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> *%a0 to i8*
%res = call <4 x i64> @llvm.x86.avx2.movntdqa(i8* %arg0)
ret <4 x i64> %res
declare <4 x i64> @llvm.x86.avx2.movntdqa(i8*) nounwind readonly
define <4 x i64> @test_mm256_sub_epi8(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_sub_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpsubb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sub_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpsubb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sub_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsubb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = sub <32 x i8> %arg0, %arg1
}
define <4 x i64> @test_mm256_sub_epi16(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_sub_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsubw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sub_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsubw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sub_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsubw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = sub <16 x i16> %arg0, %arg1
}
define <4 x i64> @test_mm256_sub_epi32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_sub_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsubd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sub_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsubd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sub_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsubd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = sub <8 x i32> %arg0, %arg1
}
define <4 x i64> @test_mm256_sub_epi64(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_sub_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsubq %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sub_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsubq %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sub_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsubq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = sub <4 x i64> %a0, %a1
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_subs_epi8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_subs_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpsubsb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_subs_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpsubsb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_subs_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsubsb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = call <32 x i8> @llvm.x86.avx2.psubs.b(<32 x i8> %arg0, <32 x i8> %arg1)
declare <32 x i8> @llvm.x86.avx2.psubs.b(<32 x i8>, <32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_subs_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_subs_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsubsw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_subs_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsubsw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_subs_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsubsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.psubs.w(<16 x i16> %arg0, <16 x i16> %arg1)
declare <16 x i16> @llvm.x86.avx2.psubs.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_subs_epu8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_subs_epu8:
-; X32: # BB#0:
-; X32-NEXT: vpsubusb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_subs_epu8:
-; X64: # BB#0:
-; X64-NEXT: vpsubusb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_subs_epu8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsubusb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = call <32 x i8> @llvm.x86.avx2.psubus.b(<32 x i8> %arg0, <32 x i8> %arg1)
declare <32 x i8> @llvm.x86.avx2.psubus.b(<32 x i8>, <32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_subs_epu16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_subs_epu16:
-; X32: # BB#0:
-; X32-NEXT: vpsubusw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_subs_epu16:
-; X64: # BB#0:
-; X64-NEXT: vpsubusw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_subs_epu16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsubusw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.psubus.w(<16 x i16> %arg0, <16 x i16> %arg1)
declare <16 x i16> @llvm.x86.avx2.psubus.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_unpackhi_epi8(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_unpackhi_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_unpackhi_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_unpackhi_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = shufflevector <32 x i8> %arg0, <32 x i8> %arg1, <32 x i32> <i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47, i32 24, i32 56, i32 25, i32 57, i32 26, i32 58, i32 27, i32 59, i32 28, i32 60, i32 29, i32 61, i32 30, i32 62, i32 31, i32 63>
}
define <4 x i64> @test_mm256_unpackhi_epi16(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_unpackhi_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_unpackhi_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_unpackhi_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = shufflevector <16 x i16> %arg0, <16 x i16> %arg1, <16 x i32> <i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
}
define <4 x i64> @test_mm256_unpackhi_epi32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_unpackhi_epi32:
-; X32: # BB#0:
-; X32-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_unpackhi_epi32:
-; X64: # BB#0:
-; X64-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_unpackhi_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = shufflevector <8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15>
}
define <4 x i64> @test_mm256_unpackhi_epi64(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_unpackhi_epi64:
-; X32: # BB#0:
-; X32-NEXT: vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_unpackhi_epi64:
-; X64: # BB#0:
-; X64-NEXT: vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_unpackhi_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x i64> %a0, <4 x i64> %a1, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_unpacklo_epi8(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_unpacklo_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_unpacklo_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_unpacklo_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = shufflevector <32 x i8> %arg0, <32 x i8> %arg1, <32 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 16, i32 48, i32 17, i32 49, i32 18, i32 50, i32 19, i32 51, i32 20, i32 52, i32 21, i32 53, i32 22, i32 54, i32 23, i32 55>
}
define <4 x i64> @test_mm256_unpacklo_epi16(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_unpacklo_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_unpacklo_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_unpacklo_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = shufflevector <16 x i16> %arg0, <16 x i16> %arg1, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27>
}
define <4 x i64> @test_mm256_unpacklo_epi32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_unpacklo_epi32:
-; X32: # BB#0:
-; X32-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_unpacklo_epi32:
-; X64: # BB#0:
-; X64-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_unpacklo_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = shufflevector <8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13>
}
define <4 x i64> @test_mm256_unpacklo_epi64(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_unpacklo_epi64:
-; X32: # BB#0:
-; X32-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_unpacklo_epi64:
-; X64: # BB#0:
-; X64-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_unpacklo_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x i64> %a0, <4 x i64> %a1, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_xor_si256(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_xor_si256:
-; X32: # BB#0:
-; X32-NEXT: vxorps %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_xor_si256:
-; X64: # BB#0:
-; X64-NEXT: vxorps %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_xor_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vxorps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = xor <4 x i64> %a0, %a1
ret <4 x i64> %res
}
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=avx2 -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2
-; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=avx2 -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2 --check-prefix=X86 --check-prefix=X86-AVX
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL --check-prefix=X86 --check-prefix=X86-AVX512VL
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx2 -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2 --check-prefix=X64 --check-prefix=X64-AVX
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL --check-prefix=X64 --check-prefix=X64-AVX512VL
define <16 x i16> @test_x86_avx2_packssdw(<8 x i32> %a0, <8 x i32> %a1) {
; AVX2-LABEL: test_x86_avx2_packssdw:
; AVX2: ## BB#0:
; AVX2-NEXT: vpackssdw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x6b,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_packssdw:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpackssdw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6b,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %a0, <8 x i32> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
define <16 x i16> @test_x86_avx2_packssdw_fold() {
-; AVX2-LABEL: test_x86_avx2_packssdw_fold:
-; AVX2: ## BB#0:
-; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
-; AVX2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI1_0, kind: FK_Data_4
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_packssdw_fold:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: vmovaps LCPI1_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
-; AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI1_0, kind: FK_Data_4
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_packssdw_fold:
+; X86-AVX: ## BB#0:
+; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
+; X86-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI1_0, kind: FK_Data_4
+; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_packssdw_fold:
+; X86-AVX512VL: ## BB#0:
+; X86-AVX512VL-NEXT: vmovaps LCPI1_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
+; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI1_0, kind: FK_Data_4
+; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_packssdw_fold:
+; X64-AVX: ## BB#0:
+; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
+; X64-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI1_0-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_packssdw_fold:
+; X64-AVX512VL: ## BB#0:
+; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
+; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI1_0-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> zeroinitializer, <8 x i32> <i32 255, i32 32767, i32 65535, i32 -1, i32 -32767, i32 -65535, i32 0, i32 -256>)
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_packsswb:
; AVX2: ## BB#0:
; AVX2-NEXT: vpacksswb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x63,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_packsswb:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpacksswb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x63,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> %a0, <16 x i16> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
define <32 x i8> @test_x86_avx2_packsswb_fold() {
-; AVX2-LABEL: test_x86_avx2_packsswb_fold:
-; AVX2: ## BB#0:
-; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
-; AVX2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI3_0, kind: FK_Data_4
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_packsswb_fold:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: vmovaps LCPI3_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
-; AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI3_0, kind: FK_Data_4
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_packsswb_fold:
+; X86-AVX: ## BB#0:
+; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
+; X86-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI3_0, kind: FK_Data_4
+; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_packsswb_fold:
+; X86-AVX512VL: ## BB#0:
+; X86-AVX512VL-NEXT: vmovaps LCPI3_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
+; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI3_0, kind: FK_Data_4
+; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_packsswb_fold:
+; X64-AVX: ## BB#0:
+; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
+; X64-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI3_0-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_packsswb_fold:
+; X64-AVX512VL: ## BB#0:
+; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 ## EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
+; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI3_0-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678, i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <16 x i16> zeroinitializer)
ret <32 x i8> %res
}
; AVX2-LABEL: test_x86_avx2_packuswb:
; AVX2: ## BB#0:
; AVX2-NEXT: vpackuswb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x67,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_packuswb:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpackuswb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x67,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> %a0, <16 x i16> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
define <32 x i8> @test_x86_avx2_packuswb_fold() {
-; AVX2-LABEL: test_x86_avx2_packuswb_fold:
-; AVX2: ## BB#0:
-; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
-; AVX2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI5_0, kind: FK_Data_4
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_packuswb_fold:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: vmovaps LCPI5_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
-; AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI5_0, kind: FK_Data_4
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_packuswb_fold:
+; X86-AVX: ## BB#0:
+; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; X86-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI5_0, kind: FK_Data_4
+; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_packuswb_fold:
+; X86-AVX512VL: ## BB#0:
+; X86-AVX512VL-NEXT: vmovaps LCPI5_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI5_0, kind: FK_Data_4
+; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_packuswb_fold:
+; X64-AVX: ## BB#0:
+; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; X64-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI5_0-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_packuswb_fold:
+; X64-AVX512VL: ## BB#0:
+; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 ## EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI5_0-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678, i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <16 x i16> zeroinitializer)
ret <32 x i8> %res
}
; AVX2-LABEL: test_x86_avx2_padds_b:
; AVX2: ## BB#0:
; AVX2-NEXT: vpaddsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xec,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_padds_b:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpaddsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xec,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.padds.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
; AVX2-LABEL: test_x86_avx2_padds_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpaddsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xed,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_padds_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpaddsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xed,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.padds.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_paddus_b:
; AVX2: ## BB#0:
; AVX2-NEXT: vpaddusb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xdc,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_paddus_b:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpaddusb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdc,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.paddus.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
; AVX2-LABEL: test_x86_avx2_paddus_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpaddusw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xdd,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_paddus_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpaddusw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdd,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.paddus.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_pmadd_wd:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf5,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmadd_wd:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf5,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a0, <16 x i16> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_pmaxs_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xee,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmaxs_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xee,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmaxs.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_pmaxu_b:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xde,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmaxu_b:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xde,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pmaxu.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
; AVX2-LABEL: test_x86_avx2_pmins_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpminsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xea,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmins_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpminsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xea,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmins.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_pminu_b:
; AVX2: ## BB#0:
; AVX2-NEXT: vpminub %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xda,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pminu_b:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpminub %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xda,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pminu.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovmskb %ymm0, %eax ## encoding: [0xc5,0xfd,0xd7,0xc0]
; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call i32 @llvm.x86.avx2.pmovmskb(<32 x i8> %a0) ; <i32> [#uses=1]
ret i32 %res
}
; AVX2-LABEL: test_x86_avx2_pmulh_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmulhw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe5,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmulh_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmulhw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe5,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_pmulhu_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe4,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmulhu_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe4,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_pmulu_dq:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmuludq %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf4,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmulu_dq:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmuludq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf4,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32> %a0, <8 x i32> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
; AVX2-LABEL: test_x86_avx2_psad_bw:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf6,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psad_bw:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf6,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8> %a0, <32 x i8> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
; AVX2-LABEL: test_x86_avx2_psll_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpslld %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf2,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psll_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpslld %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf2,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_psll_q:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsllq %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf3,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psll_q:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsllq %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf3,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
; AVX2-LABEL: test_x86_avx2_psll_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf1,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psll_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf1,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_pslli_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpslld $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x72,0xf0,0x07]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pslli_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpslld $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x72,0xf0,0x07]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_pslli_q:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsllq $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x73,0xf0,0x07]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pslli_q:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsllq $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x73,0xf0,0x07]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
; AVX2-LABEL: test_x86_avx2_pslli_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsllw $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x71,0xf0,0x07]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pslli_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsllw $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x71,0xf0,0x07]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_psra_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrad %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe2,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psra_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrad %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe2,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_psra_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsraw %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe1,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psra_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsraw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe1,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_psrai_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrad $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x72,0xe0,0x07]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrai_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrad $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x72,0xe0,0x07]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_psrai_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsraw $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x71,0xe0,0x07]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrai_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsraw $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x71,0xe0,0x07]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_psrl_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrld %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd2,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrl_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrld %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd2,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_psrl_q:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrlq %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd3,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrl_q:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrlq %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd3,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
; AVX2-LABEL: test_x86_avx2_psrl_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd1,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrl_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd1,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_psrli_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrld $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x72,0xd0,0x07]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrli_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrld $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x72,0xd0,0x07]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_psrli_q:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrlq $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x73,0xd0,0x07]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrli_q:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrlq $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x73,0xd0,0x07]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
; AVX2-LABEL: test_x86_avx2_psrli_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrlw $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x71,0xd0,0x07]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrli_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x71,0xd0,0x07]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_psubs_b:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsubsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe8,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psubs_b:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsubsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe8,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.psubs.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
; AVX2-LABEL: test_x86_avx2_psubs_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsubsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe9,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psubs_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsubsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe9,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psubs.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_psubus_b:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd8,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psubus_b:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd8,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.psubus.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
; AVX2-LABEL: test_x86_avx2_psubus_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd9,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psubus_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd9,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psubus.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; CHECK-LABEL: test_x86_avx2_phadd_d:
; CHECK: ## BB#0:
; CHECK-NEXT: vphaddd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x02,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; CHECK-LABEL: test_x86_avx2_phadd_sw:
; CHECK: ## BB#0:
; CHECK-NEXT: vphaddsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x03,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; CHECK-LABEL: test_x86_avx2_phadd_w:
; CHECK: ## BB#0:
; CHECK-NEXT: vphaddw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x01,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; CHECK-LABEL: test_x86_avx2_phsub_d:
; CHECK: ## BB#0:
; CHECK-NEXT: vphsubd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x06,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; CHECK-LABEL: test_x86_avx2_phsub_sw:
; CHECK: ## BB#0:
; CHECK-NEXT: vphsubsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x07,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; CHECK-LABEL: test_x86_avx2_phsub_w:
; CHECK: ## BB#0:
; CHECK-NEXT: vphsubw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x05,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_pmadd_ub_sw:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x04,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmadd_ub_sw:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x04,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> %a0, <32 x i8> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; Make sure we don't commute this operation.
define <16 x i16> @test_x86_avx2_pmadd_ub_sw_load_op0(<32 x i8>* %ptr, <32 x i8> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0:
-; AVX2: ## BB#0:
-; AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; AVX2-NEXT: vmovdqa (%eax), %ymm1 ## encoding: [0xc5,0xfd,0x6f,0x08]
-; AVX2-NEXT: vpmaddubsw %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x04,0xc0]
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; AVX512VL-NEXT: vmovdqa (%eax), %ymm1 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0x08]
-; AVX512VL-NEXT: vpmaddubsw %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x04,0xc0]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0:
+; X86-AVX: ## BB#0:
+; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-AVX-NEXT: vmovdqa (%eax), %ymm1 ## encoding: [0xc5,0xfd,0x6f,0x08]
+; X86-AVX-NEXT: vpmaddubsw %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x04,0xc0]
+; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0:
+; X86-AVX512VL: ## BB#0:
+; X86-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-AVX512VL-NEXT: vmovdqa (%eax), %ymm1 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0x08]
+; X86-AVX512VL-NEXT: vpmaddubsw %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x04,0xc0]
+; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0:
+; X64-AVX: ## BB#0:
+; X64-AVX-NEXT: vmovdqa (%rdi), %ymm1 ## encoding: [0xc5,0xfd,0x6f,0x0f]
+; X64-AVX-NEXT: vpmaddubsw %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x04,0xc0]
+; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0:
+; X64-AVX512VL: ## BB#0:
+; X64-AVX512VL-NEXT: vmovdqa (%rdi), %ymm1 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0x0f]
+; X64-AVX512VL-NEXT: vpmaddubsw %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x04,0xc0]
+; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%a0 = load <32 x i8>, <32 x i8>* %ptr
%res = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> %a0, <32 x i8> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
; AVX2-LABEL: test_x86_avx2_pmul_hr_sw:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x0b,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmul_hr_sw:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x0b,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmul.hr.sw(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_pshuf_b:
; AVX2: ## BB#0:
; AVX2-NEXT: vpshufb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x00,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pshuf_b:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpshufb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x00,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> %a1) ; <<16 x i8>> [#uses=1]
ret <32 x i8> %res
}
; CHECK-LABEL: test_x86_avx2_psign_b:
; CHECK: ## BB#0:
; CHECK-NEXT: vpsignb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x08,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.psign.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
; CHECK-LABEL: test_x86_avx2_psign_d:
; CHECK: ## BB#0:
; CHECK-NEXT: vpsignd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x0a,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psign.d(<8 x i32> %a0, <8 x i32> %a1) ; <<4 x i32>> [#uses=1]
ret <8 x i32> %res
}
; CHECK-LABEL: test_x86_avx2_psign_w:
; CHECK: ## BB#0:
; CHECK-NEXT: vpsignw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x09,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psign.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; CHECK-LABEL: test_x86_avx2_mpsadbw:
; CHECK: ## BB#0:
; CHECK-NEXT: vmpsadbw $7, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x42,0xc1,0x07]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> %a0, <32 x i8> %a1, i8 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_packusdw:
; AVX2: ## BB#0:
; AVX2-NEXT: vpackusdw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x2b,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_packusdw:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpackusdw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x2b,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> %a0, <8 x i32> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
define <16 x i16> @test_x86_avx2_packusdw_fold() {
-; AVX2-LABEL: test_x86_avx2_packusdw_fold:
-; AVX2: ## BB#0:
-; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
-; AVX2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI55_0, kind: FK_Data_4
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_packusdw_fold:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: vmovaps LCPI55_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
-; AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI55_0, kind: FK_Data_4
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_packusdw_fold:
+; X86-AVX: ## BB#0:
+; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
+; X86-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI55_0, kind: FK_Data_4
+; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_packusdw_fold:
+; X86-AVX512VL: ## BB#0:
+; X86-AVX512VL-NEXT: vmovaps LCPI55_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
+; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI55_0, kind: FK_Data_4
+; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_packusdw_fold:
+; X64-AVX: ## BB#0:
+; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
+; X64-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI55_0-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_packusdw_fold:
+; X64-AVX512VL: ## BB#0:
+; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
+; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI55_0-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> zeroinitializer, <8 x i32> <i32 255, i32 32767, i32 65535, i32 -1, i32 -32767, i32 -65535, i32 0, i32 -256>)
ret <16 x i16> %res
}
; CHECK-LABEL: test_x86_avx2_pblendvb:
; CHECK: ## BB#0:
; CHECK-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x4c,0xc1,0x20]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %a2) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
; CHECK: ## BB#0:
; CHECK-NEXT: vpblendw $7, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x0e,0xc1,0x07]
; CHECK-NEXT: ## ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7],ymm1[8,9,10],ymm0[11,12,13,14,15]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i8 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_pmaxsb:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3c,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmaxsb:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3c,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pmaxs.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
; AVX2-LABEL: test_x86_avx2_pmaxsd:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3d,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmaxsd:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3d,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pmaxs.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_pmaxud:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3f,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmaxud:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3f,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pmaxu.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_pmaxuw:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3e,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmaxuw:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3e,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmaxu.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; AVX2-LABEL: test_x86_avx2_pminsb:
; AVX2: ## BB#0:
; AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x38,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pminsb:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpminsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x38,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pmins.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
; AVX2-LABEL: test_x86_avx2_pminsd:
; AVX2: ## BB#0:
; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x39,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pminsd:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpminsd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x39,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pmins.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_pminud:
; AVX2: ## BB#0:
; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3b,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pminud:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpminud %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3b,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pminu.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_pminuw:
; AVX2: ## BB#0:
; AVX2-NEXT: vpminuw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3a,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pminuw:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpminuw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3a,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pminu.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
; CHECK: ## BB#0:
; CHECK-NEXT: vblendps $8, %xmm0, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x71,0x0c,0xc0,0x08]
; CHECK-NEXT: ## xmm0 = xmm1[0,1,2],xmm0[3]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a1, i8 7) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
; CHECK: ## BB#0:
; CHECK-NEXT: vblendps $7, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x0c,0xc1,0x07]
; CHECK-NEXT: ## ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a1, i8 7) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_permd:
; AVX2: ## BB#0:
; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x16,0xc0]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_permd:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x16,0xc0]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_permps:
; AVX2: ## BB#0:
; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x16,0xc0]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_permps:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x16,0xc0]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> %a1) ; <<8 x float>> [#uses=1]
ret <8 x float> %res
}
define <2 x i64> @test_x86_avx2_maskload_q(i8* %a0, <2 x i64> %a1) {
-; CHECK-LABEL: test_x86_avx2_maskload_q:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpmaskmovq (%eax), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x8c,0x00]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_maskload_q:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpmaskmovq (%eax), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x8c,0x00]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_maskload_q:
+; X64: ## BB#0:
+; X64-NEXT: vpmaskmovq (%rdi), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x8c,0x07]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.maskload.q(i8* %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
ret <2 x i64> %res
}
define <4 x i64> @test_x86_avx2_maskload_q_256(i8* %a0, <4 x i64> %a1) {
-; CHECK-LABEL: test_x86_avx2_maskload_q_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpmaskmovq (%eax), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x8c,0x00]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_maskload_q_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpmaskmovq (%eax), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x8c,0x00]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_maskload_q_256:
+; X64: ## BB#0:
+; X64-NEXT: vpmaskmovq (%rdi), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x8c,0x07]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.maskload.q.256(i8* %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
define <4 x i32> @test_x86_avx2_maskload_d(i8* %a0, <4 x i32> %a1) {
-; CHECK-LABEL: test_x86_avx2_maskload_d:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpmaskmovd (%eax), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x8c,0x00]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_maskload_d:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpmaskmovd (%eax), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x8c,0x00]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_maskload_d:
+; X64: ## BB#0:
+; X64-NEXT: vpmaskmovd (%rdi), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x8c,0x07]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.maskload.d(i8* %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
define <8 x i32> @test_x86_avx2_maskload_d_256(i8* %a0, <8 x i32> %a1) {
-; CHECK-LABEL: test_x86_avx2_maskload_d_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpmaskmovd (%eax), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x8c,0x00]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_maskload_d_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpmaskmovd (%eax), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x8c,0x00]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_maskload_d_256:
+; X64: ## BB#0:
+; X64-NEXT: vpmaskmovd (%rdi), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x8c,0x07]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.maskload.d.256(i8* %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
define void @test_x86_avx2_maskstore_q(i8* %a0, <2 x i64> %a1, <2 x i64> %a2) {
-; CHECK-LABEL: test_x86_avx2_maskstore_q:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpmaskmovq %xmm1, %xmm0, (%eax) ## encoding: [0xc4,0xe2,0xf9,0x8e,0x08]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_maskstore_q:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpmaskmovq %xmm1, %xmm0, (%eax) ## encoding: [0xc4,0xe2,0xf9,0x8e,0x08]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_maskstore_q:
+; X64: ## BB#0:
+; X64-NEXT: vpmaskmovq %xmm1, %xmm0, (%rdi) ## encoding: [0xc4,0xe2,0xf9,0x8e,0x0f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
call void @llvm.x86.avx2.maskstore.q(i8* %a0, <2 x i64> %a1, <2 x i64> %a2)
ret void
}
define void @test_x86_avx2_maskstore_q_256(i8* %a0, <4 x i64> %a1, <4 x i64> %a2) {
-; CHECK-LABEL: test_x86_avx2_maskstore_q_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpmaskmovq %ymm1, %ymm0, (%eax) ## encoding: [0xc4,0xe2,0xfd,0x8e,0x08]
-; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_maskstore_q_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpmaskmovq %ymm1, %ymm0, (%eax) ## encoding: [0xc4,0xe2,0xfd,0x8e,0x08]
+; X86-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_maskstore_q_256:
+; X64: ## BB#0:
+; X64-NEXT: vpmaskmovq %ymm1, %ymm0, (%rdi) ## encoding: [0xc4,0xe2,0xfd,0x8e,0x0f]
+; X64-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
call void @llvm.x86.avx2.maskstore.q.256(i8* %a0, <4 x i64> %a1, <4 x i64> %a2)
ret void
}
define void @test_x86_avx2_maskstore_d(i8* %a0, <4 x i32> %a1, <4 x i32> %a2) {
-; CHECK-LABEL: test_x86_avx2_maskstore_d:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpmaskmovd %xmm1, %xmm0, (%eax) ## encoding: [0xc4,0xe2,0x79,0x8e,0x08]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_maskstore_d:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpmaskmovd %xmm1, %xmm0, (%eax) ## encoding: [0xc4,0xe2,0x79,0x8e,0x08]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_maskstore_d:
+; X64: ## BB#0:
+; X64-NEXT: vpmaskmovd %xmm1, %xmm0, (%rdi) ## encoding: [0xc4,0xe2,0x79,0x8e,0x0f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
call void @llvm.x86.avx2.maskstore.d(i8* %a0, <4 x i32> %a1, <4 x i32> %a2)
ret void
}
define void @test_x86_avx2_maskstore_d_256(i8* %a0, <8 x i32> %a1, <8 x i32> %a2) {
-; CHECK-LABEL: test_x86_avx2_maskstore_d_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpmaskmovd %ymm1, %ymm0, (%eax) ## encoding: [0xc4,0xe2,0x7d,0x8e,0x08]
-; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_maskstore_d_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpmaskmovd %ymm1, %ymm0, (%eax) ## encoding: [0xc4,0xe2,0x7d,0x8e,0x08]
+; X86-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_maskstore_d_256:
+; X64: ## BB#0:
+; X64-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi) ## encoding: [0xc4,0xe2,0x7d,0x8e,0x0f]
+; X64-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
call void @llvm.x86.avx2.maskstore.d.256(i8* %a0, <8 x i32> %a1, <8 x i32> %a2)
ret void
}
; AVX2-LABEL: test_x86_avx2_psllv_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x47,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psllv_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x47,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_psllv_d_256:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x47,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psllv_d_256:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x47,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_psllv_q:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x47,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psllv_q:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x47,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
ret <2 x i64> %res
}
; AVX2-LABEL: test_x86_avx2_psllv_q_256:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x47,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psllv_q_256:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x47,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
; AVX2-LABEL: test_x86_avx2_psrlv_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x45,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrlv_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x45,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_psrlv_d_256:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x45,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrlv_d_256:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x45,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_psrlv_q:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x45,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrlv_q:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x45,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
ret <2 x i64> %res
}
; AVX2-LABEL: test_x86_avx2_psrlv_q_256:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x45,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrlv_q_256:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x45,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
; AVX2-LABEL: test_x86_avx2_psrav_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsravd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x46,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrav_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsravd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
define <4 x i32> @test_x86_avx2_psrav_d_const(<4 x i32> %a0, <4 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_psrav_d_const:
-; AVX2: ## BB#0:
-; AVX2-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,4294967284,23]
-; AVX2-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI88_0, kind: FK_Data_4
-; AVX2-NEXT: vpsravd LCPI88_1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
-; AVX2-NEXT: ## fixup A - offset: 5, value: LCPI88_1, kind: FK_Data_4
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrav_d_const:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: vmovdqa LCPI88_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [2,9,4294967284,23]
-; AVX512VL-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI88_0, kind: FK_Data_4
-; AVX512VL-NEXT: vpsravd LCPI88_1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI88_1, kind: FK_Data_4
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrav_d_const:
+; X86-AVX: ## BB#0:
+; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,4294967284,23]
+; X86-AVX-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI88_0, kind: FK_Data_4
+; X86-AVX-NEXT: vpsravd LCPI88_1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 5, value: LCPI88_1, kind: FK_Data_4
+; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrav_d_const:
+; X86-AVX512VL: ## BB#0:
+; X86-AVX512VL-NEXT: vmovdqa LCPI88_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [2,9,4294967284,23]
+; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI88_0, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsravd LCPI88_1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI88_1, kind: FK_Data_4
+; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrav_d_const:
+; X64-AVX: ## BB#0:
+; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,4294967284,23]
+; X64-AVX-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
+; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI88_0-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
+; X64-AVX-NEXT: ## fixup A - offset: 5, value: LCPI88_1-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrav_d_const:
+; X64-AVX512VL: ## BB#0:
+; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 ## EVEX TO VEX Compression xmm0 = [2,9,4294967284,23]
+; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI88_0-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI88_1-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> <i32 2, i32 9, i32 -12, i32 23>, <4 x i32> <i32 1, i32 18, i32 35, i32 52>)
ret <4 x i32> %res
}
; AVX2-LABEL: test_x86_avx2_psrav_d_256:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x46,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrav_d_256:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
define <8 x i32> @test_x86_avx2_psrav_d_256_const(<8 x i32> %a0, <8 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_psrav_d_256_const:
-; AVX2: ## BB#0:
-; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
-; AVX2-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI90_0, kind: FK_Data_4
-; AVX2-NEXT: vpsravd LCPI90_1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
-; AVX2-NEXT: ## fixup A - offset: 5, value: LCPI90_1, kind: FK_Data_4
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrav_d_256_const:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: vmovdqa LCPI90_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
-; AVX512VL-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI90_0, kind: FK_Data_4
-; AVX512VL-NEXT: vpsravd LCPI90_1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI90_1, kind: FK_Data_4
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrav_d_256_const:
+; X86-AVX: ## BB#0:
+; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
+; X86-AVX-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI90_0, kind: FK_Data_4
+; X86-AVX-NEXT: vpsravd LCPI90_1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 5, value: LCPI90_1, kind: FK_Data_4
+; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrav_d_256_const:
+; X86-AVX512VL: ## BB#0:
+; X86-AVX512VL-NEXT: vmovdqa LCPI90_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
+; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI90_0, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsravd LCPI90_1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI90_1, kind: FK_Data_4
+; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrav_d_256_const:
+; X64-AVX: ## BB#0:
+; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
+; X64-AVX-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
+; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI90_0-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
+; X64-AVX-NEXT: ## fixup A - offset: 5, value: LCPI90_1-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrav_d_256_const:
+; X64-AVX512VL: ## BB#0:
+; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm0 ## EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
+; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI90_0-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI90_1-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> <i32 2, i32 9, i32 -12, i32 23, i32 -26, i32 37, i32 -40, i32 51>, <8 x i32> <i32 1, i32 18, i32 35, i32 52, i32 69, i32 15, i32 32, i32 49>)
ret <8 x i32> %res
}
declare <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32>, <8 x i32>) nounwind readnone
define <2 x double> @test_x86_avx2_gather_d_pd(<2 x double> %a0, i8* %a1, <4 x i32> %idx, <2 x double> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_d_pd:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vgatherdpd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x92,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_d_pd:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vgatherdpd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x92,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_d_pd:
+; X64: ## BB#0:
+; X64-NEXT: vgatherdpd %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x92,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double> %a0,
i8* %a1, <4 x i32> %idx, <2 x double> %mask, i8 2) ;
ret <2 x double> %res
<4 x i32>, <2 x double>, i8) nounwind readonly
define <4 x double> @test_x86_avx2_gather_d_pd_256(<4 x double> %a0, i8* %a1, <4 x i32> %idx, <4 x double> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_d_pd_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vgatherdpd %ymm2, (%eax,%xmm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x92,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_d_pd_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vgatherdpd %ymm2, (%eax,%xmm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x92,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_d_pd_256:
+; X64: ## BB#0:
+; X64-NEXT: vgatherdpd %ymm2, (%rdi,%xmm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x92,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> %a0,
i8* %a1, <4 x i32> %idx, <4 x double> %mask, i8 2) ;
ret <4 x double> %res
<4 x i32>, <4 x double>, i8) nounwind readonly
define <2 x double> @test_x86_avx2_gather_q_pd(<2 x double> %a0, i8* %a1, <2 x i64> %idx, <2 x double> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_q_pd:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vgatherqpd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x93,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_q_pd:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vgatherqpd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x93,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_q_pd:
+; X64: ## BB#0:
+; X64-NEXT: vgatherqpd %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x93,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double> %a0,
i8* %a1, <2 x i64> %idx, <2 x double> %mask, i8 2) ;
ret <2 x double> %res
<2 x i64>, <2 x double>, i8) nounwind readonly
define <4 x double> @test_x86_avx2_gather_q_pd_256(<4 x double> %a0, i8* %a1, <4 x i64> %idx, <4 x double> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_q_pd_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vgatherqpd %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x93,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_q_pd_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vgatherqpd %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x93,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_q_pd_256:
+; X64: ## BB#0:
+; X64-NEXT: vgatherqpd %ymm2, (%rdi,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x93,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> %a0,
i8* %a1, <4 x i64> %idx, <4 x double> %mask, i8 2) ;
ret <4 x double> %res
<4 x i64>, <4 x double>, i8) nounwind readonly
define <4 x float> @test_x86_avx2_gather_d_ps(<4 x float> %a0, i8* %a1, <4 x i32> %idx, <4 x float> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_d_ps:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vgatherdps %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x92,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_d_ps:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vgatherdps %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x92,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_d_ps:
+; X64: ## BB#0:
+; X64-NEXT: vgatherdps %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x92,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> %a0,
i8* %a1, <4 x i32> %idx, <4 x float> %mask, i8 2) ;
ret <4 x float> %res
<4 x i32>, <4 x float>, i8) nounwind readonly
define <8 x float> @test_x86_avx2_gather_d_ps_256(<8 x float> %a0, i8* %a1, <8 x i32> %idx, <8 x float> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_d_ps_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vgatherdps %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0x6d,0x92,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_d_ps_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vgatherdps %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0x6d,0x92,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_d_ps_256:
+; X64: ## BB#0:
+; X64-NEXT: vgatherdps %ymm2, (%rdi,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0x6d,0x92,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> %a0,
i8* %a1, <8 x i32> %idx, <8 x float> %mask, i8 2) ;
ret <8 x float> %res
<8 x i32>, <8 x float>, i8) nounwind readonly
define <4 x float> @test_x86_avx2_gather_q_ps(<4 x float> %a0, i8* %a1, <2 x i64> %idx, <4 x float> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_q_ps:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vgatherqps %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x93,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_q_ps:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vgatherqps %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x93,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_q_ps:
+; X64: ## BB#0:
+; X64-NEXT: vgatherqps %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x93,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float> %a0,
i8* %a1, <2 x i64> %idx, <4 x float> %mask, i8 2) ;
ret <4 x float> %res
<2 x i64>, <4 x float>, i8) nounwind readonly
define <4 x float> @test_x86_avx2_gather_q_ps_256(<4 x float> %a0, i8* %a1, <4 x i64> %idx, <4 x float> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_q_ps_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vgatherqps %xmm2, (%eax,%ymm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x6d,0x93,0x04,0x48]
-; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_q_ps_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vgatherqps %xmm2, (%eax,%ymm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x6d,0x93,0x04,0x48]
+; X86-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_q_ps_256:
+; X64: ## BB#0:
+; X64-NEXT: vgatherqps %xmm2, (%rdi,%ymm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x6d,0x93,0x04,0x4f]
+; X64-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float> %a0,
i8* %a1, <4 x i64> %idx, <4 x float> %mask, i8 2) ;
ret <4 x float> %res
<4 x i64>, <4 x float>, i8) nounwind readonly
define <2 x i64> @test_x86_avx2_gather_d_q(<2 x i64> %a0, i8* %a1, <4 x i32> %idx, <2 x i64> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_d_q:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpgatherdq %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x90,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_d_q:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpgatherdq %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x90,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_d_q:
+; X64: ## BB#0:
+; X64-NEXT: vpgatherdq %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x90,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64> %a0,
i8* %a1, <4 x i32> %idx, <2 x i64> %mask, i8 2) ;
ret <2 x i64> %res
<4 x i32>, <2 x i64>, i8) nounwind readonly
define <4 x i64> @test_x86_avx2_gather_d_q_256(<4 x i64> %a0, i8* %a1, <4 x i32> %idx, <4 x i64> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_d_q_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpgatherdq %ymm2, (%eax,%xmm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x90,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_d_q_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpgatherdq %ymm2, (%eax,%xmm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x90,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_d_q_256:
+; X64: ## BB#0:
+; X64-NEXT: vpgatherdq %ymm2, (%rdi,%xmm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x90,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> %a0,
i8* %a1, <4 x i32> %idx, <4 x i64> %mask, i8 2) ;
ret <4 x i64> %res
<4 x i32>, <4 x i64>, i8) nounwind readonly
define <2 x i64> @test_x86_avx2_gather_q_q(<2 x i64> %a0, i8* %a1, <2 x i64> %idx, <2 x i64> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_q_q:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpgatherqq %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x91,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_q_q:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpgatherqq %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x91,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_q_q:
+; X64: ## BB#0:
+; X64-NEXT: vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x91,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> %a0,
i8* %a1, <2 x i64> %idx, <2 x i64> %mask, i8 2) ;
ret <2 x i64> %res
<2 x i64>, <2 x i64>, i8) nounwind readonly
define <4 x i64> @test_x86_avx2_gather_q_q_256(<4 x i64> %a0, i8* %a1, <4 x i64> %idx, <4 x i64> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_q_q_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpgatherqq %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x91,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_q_q_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpgatherqq %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x91,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_q_q_256:
+; X64: ## BB#0:
+; X64-NEXT: vpgatherqq %ymm2, (%rdi,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x91,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> %a0,
i8* %a1, <4 x i64> %idx, <4 x i64> %mask, i8 2) ;
ret <4 x i64> %res
<4 x i64>, <4 x i64>, i8) nounwind readonly
define <4 x i32> @test_x86_avx2_gather_d_d(<4 x i32> %a0, i8* %a1, <4 x i32> %idx, <4 x i32> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_d_d:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpgatherdd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x90,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_d_d:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpgatherdd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x90,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_d_d:
+; X64: ## BB#0:
+; X64-NEXT: vpgatherdd %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x90,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32> %a0,
i8* %a1, <4 x i32> %idx, <4 x i32> %mask, i8 2) ;
ret <4 x i32> %res
<4 x i32>, <4 x i32>, i8) nounwind readonly
define <8 x i32> @test_x86_avx2_gather_d_d_256(<8 x i32> %a0, i8* %a1, <8 x i32> %idx, <8 x i32> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_d_d_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpgatherdd %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0x6d,0x90,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_d_d_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpgatherdd %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0x6d,0x90,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_d_d_256:
+; X64: ## BB#0:
+; X64-NEXT: vpgatherdd %ymm2, (%rdi,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0x6d,0x90,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32> %a0,
i8* %a1, <8 x i32> %idx, <8 x i32> %mask, i8 2) ;
ret <8 x i32> %res
<8 x i32>, <8 x i32>, i8) nounwind readonly
define <4 x i32> @test_x86_avx2_gather_q_d(<4 x i32> %a0, i8* %a1, <2 x i64> %idx, <4 x i32> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_q_d:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpgatherqd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x91,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_q_d:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpgatherqd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x91,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_q_d:
+; X64: ## BB#0:
+; X64-NEXT: vpgatherqd %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x91,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32> %a0,
i8* %a1, <2 x i64> %idx, <4 x i32> %mask, i8 2) ;
ret <4 x i32> %res
<2 x i64>, <4 x i32>, i8) nounwind readonly
define <4 x i32> @test_x86_avx2_gather_q_d_256(<4 x i32> %a0, i8* %a1, <4 x i64> %idx, <4 x i32> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_q_d_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpgatherqd %xmm2, (%eax,%ymm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x6d,0x91,0x04,0x48]
-; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_q_d_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpgatherqd %xmm2, (%eax,%ymm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x6d,0x91,0x04,0x48]
+; X86-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_q_d_256:
+; X64: ## BB#0:
+; X64-NEXT: vpgatherqd %xmm2, (%rdi,%ymm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x6d,0x91,0x04,0x4f]
+; X64-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32> %a0,
i8* %a1, <4 x i64> %idx, <4 x i32> %mask, i8 2) ;
ret <4 x i32> %res
; PR13298
define <8 x float> @test_gather_mask(<8 x float> %a0, float* %a, <8 x i32> %idx, <8 x float> %mask, float* nocapture %out) {
;; gather with mask
-; AVX2-LABEL: test_gather_mask:
-; AVX2: ## BB#0:
-; AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08]
-; AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04]
-; AVX2-NEXT: vmovaps %ymm2, %ymm3 ## encoding: [0xc5,0xfc,0x28,0xda]
-; AVX2-NEXT: vgatherdps %ymm3, (%ecx,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x89]
-; AVX2-NEXT: vmovups %ymm2, (%eax) ## encoding: [0xc5,0xfc,0x11,0x10]
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_gather_mask:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08]
-; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04]
-; AVX512VL-NEXT: vmovaps %ymm2, %ymm3 ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xda]
-; AVX512VL-NEXT: vgatherdps %ymm3, (%ecx,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x89]
-; AVX512VL-NEXT: vmovups %ymm2, (%eax) ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x11,0x10]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; X86-AVX-LABEL: test_gather_mask:
+; X86-AVX: ## BB#0:
+; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08]
+; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04]
+; X86-AVX-NEXT: vmovaps %ymm2, %ymm3 ## encoding: [0xc5,0xfc,0x28,0xda]
+; X86-AVX-NEXT: vgatherdps %ymm3, (%ecx,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x89]
+; X86-AVX-NEXT: vmovups %ymm2, (%eax) ## encoding: [0xc5,0xfc,0x11,0x10]
+; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_gather_mask:
+; X86-AVX512VL: ## BB#0:
+; X86-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08]
+; X86-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04]
+; X86-AVX512VL-NEXT: vmovaps %ymm2, %ymm3 ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xda]
+; X86-AVX512VL-NEXT: vgatherdps %ymm3, (%ecx,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x89]
+; X86-AVX512VL-NEXT: vmovups %ymm2, (%eax) ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x11,0x10]
+; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_gather_mask:
+; X64-AVX: ## BB#0:
+; X64-AVX-NEXT: vmovaps %ymm2, %ymm3 ## encoding: [0xc5,0xfc,0x28,0xda]
+; X64-AVX-NEXT: vgatherdps %ymm3, (%rdi,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x8f]
+; X64-AVX-NEXT: vmovups %ymm2, (%rsi) ## encoding: [0xc5,0xfc,0x11,0x16]
+; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_gather_mask:
+; X64-AVX512VL: ## BB#0:
+; X64-AVX512VL-NEXT: vmovaps %ymm2, %ymm3 ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xda]
+; X64-AVX512VL-NEXT: vgatherdps %ymm3, (%rdi,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x8f]
+; X64-AVX512VL-NEXT: vmovups %ymm2, (%rsi) ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x11,0x16]
+; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%a_i8 = bitcast float* %a to i8*
%res = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> %a0,
i8* %a_i8, <8 x i32> %idx, <8 x float> %mask, i8 4) ;