clk: samsung: add new clocks for Exynos5422 SoC

This patch provides support for clocks needed for Dynamic Memory Controller
in Exynos5422. It also defines new PLL rates for BPLL which is used
for DMC.

Change-Id: I85d151a19a176ef5ea8057b49b0afbfb778fe5a9
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index caf98b4..46082ce 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -132,6 +132,8 @@
 #define BPLL_LOCK              0x20010
 #define BPLL_CON0              0x20110
 #define SRC_CDREX              0x20200
+#define GATE_BUS_CDREX0                0x20700
+#define GATE_BUS_CDREX1                0x20704
 #define DIV_CDREX0             0x20500
 #define DIV_CDREX1             0x20504
 #define KPLL_LOCK              0x28000
@@ -252,6 +254,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = {
        DIV_CDREX1,
        SRC_KFC,
        DIV_KFC0,
+       GATE_BUS_CDREX0,
+       GATE_BUS_CDREX1,
 };
 
 static const unsigned long exynos5800_clk_regs[] __initconst = {
@@ -489,6 +493,9 @@ PNAME(mout_group13_5800_p)  = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
 PNAME(mout_group14_5800_p)     = { "dout_aclk550_cam", "dout_sclk_sw" };
 PNAME(mout_group15_5800_p)     = { "dout_osc_div", "mout_sw_aclk550_cam" };
 PNAME(mout_group16_5800_p)     = { "dout_osc_div", "mout_mau_epll_clk" };
+PNAME(mout_mx_mspll_ccore_phy_p)        = { "sclk_bpll", "mout_dpll_ctrl",
+                                       "mout_mpll_ctrl", "ff_dout_spll2",
+                                       "mout_sclk_spll"};
 
 /* fixed rate clocks generated outside the soc */
 static struct samsung_fixed_rate_clock
@@ -514,7 +521,7 @@ static const struct samsung_fixed_factor_clock
 static const struct samsung_fixed_factor_clock
                exynos5800_fixed_factor_clks[] __initconst = {
        FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
-       FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
+       FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
 };
 
 static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
@@ -536,11 +543,14 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
        MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
        MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
 
+       MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy",
+           mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),
+
        MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
-                       mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2),
+                       mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3),
        MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
                        SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
-       MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
+       MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
        MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
 
        MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
@@ -710,7 +720,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 
        MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
        MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
-       MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
+       MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
        MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
        MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
        MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
@@ -877,9 +887,13 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
                        DIV_CDREX0, 16, 3),
        DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0",
                        DIV_CDREX0, 8, 3),
+       DIV(0, "dout_cclk_drex1", "dout_clk2x_phy0", DIV_CDREX0, 8, 3),
        DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex",
                        DIV_CDREX0, 3, 5),
 
+       DIV(0, "dout_pclk_drex0", "dout_cclk_drex0", DIV_CDREX0, 28, 3),
+       DIV(0, "dout_pclk_drex1", "dout_cclk_drex1", DIV_CDREX0, 28, 3),
+
        DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex",
                        DIV_CDREX1, 8, 3),
 
@@ -1261,6 +1275,29 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
        GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
 
        GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
+
+       GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex", GATE_BUS_CDREX0, 0, 0, 0),
+       GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex", GATE_BUS_CDREX0, 1, 0, 0),
+       GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy",
+            SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0),
+
+       GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1",
+            GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1",
+            GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1",
+            GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1",
+            GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0),
+
+       GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex",
+            GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex",
+            GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex",
+            GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex",
+            GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0),
 };
 
 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
@@ -1286,6 +1323,20 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini
        PLL_35XX_RATE(200000000,  200, 3, 3),
 };
 
+static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] __initconst = {
+       PLL_35XX_RATE(933000000, 311, 4, 1),
+       PLL_35XX_RATE(925000000, 307, 4, 1),
+       PLL_35XX_RATE(825000000, 275, 4, 1),
+       PLL_35XX_RATE(728000000, 182, 3, 1),
+       PLL_35XX_RATE(633000000, 211, 4, 1),
+       PLL_35XX_RATE(543000000, 181, 2, 2),
+       PLL_35XX_RATE(413000000, 413, 6, 2),
+       PLL_35XX_RATE(275000000, 275, 3, 3),
+       PLL_35XX_RATE(206000000, 206, 3, 3),
+       PLL_35XX_RATE(165000000, 110, 2, 3),
+       PLL_35XX_RATE(138000000, 184, 2, 4),
+};
+
 static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
        PLL_36XX_RATE(600000000U, 100, 2, 1, 0),
        PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
@@ -1440,6 +1491,8 @@ static void __init exynos5x_clk_init(struct device_node *np,
                exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl;
        }
 
+       exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
+
        samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
                                        reg_base);
        samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,