return DAG.getRegister(RISCV::X4, PtrVT);
}
case Intrinsic::riscv_orc_b:
- // Lower to the GORCI encoding for orc.b.
- return DAG.getNode(RISCVISD::GORC, DL, XLenVT, Op.getOperand(1),
+ case Intrinsic::riscv_brev8: {
+ // Lower to the GORCI encoding for orc.b or the GREVI encoding for brev8.
+ unsigned Opc =
+ IntNo == Intrinsic::riscv_brev8 ? RISCVISD::GREV : RISCVISD::GORC;
+ return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1),
DAG.getConstant(7, DL, XLenVT));
+ }
case Intrinsic::riscv_grev:
case Intrinsic::riscv_gorc: {
unsigned Opc =
let Predicates = [HasStdExtZbf, IsRV64] in
def : PatGprGpr<riscv_bfpw, BFPW>;
-let Predicates = [HasStdExtZbkb] in {
-def : PatGpr<int_riscv_brev8, BREV8>;
-} // Predicates = [HasStdExtZbkb]
-
let Predicates = [HasStdExtZbkb, IsRV32] in {
def : PatGpr<int_riscv_zip, ZIP_RV32>;
def : PatGpr<int_riscv_unzip, UNZIP_RV32>;
ret i32 %val
}
+; Test that rev8 is recognized as preserving zero extension.
+define zeroext i16 @brev8_knownbits(i16 zeroext %a) nounwind {
+; RV32ZBKB-LABEL: brev8_knownbits:
+; RV32ZBKB: # %bb.0:
+; RV32ZBKB-NEXT: brev8 a0, a0
+; RV32ZBKB-NEXT: ret
+ %zext = zext i16 %a to i32
+ %val = call i32 @llvm.riscv.brev8(i32 %zext)
+ %trunc = trunc i32 %val to i16
+ ret i16 %trunc
+}
+
declare i32 @llvm.bswap.i32(i32)
define i32 @rev8_i32(i32 %a) nounwind {
ret i64 %val
}
+; Test that rev8 is recognized as preserving zero extension.
+define zeroext i16 @brev8_knownbits(i16 zeroext %a) nounwind {
+; RV64ZBKB-LABEL: brev8_knownbits:
+; RV64ZBKB: # %bb.0:
+; RV64ZBKB-NEXT: brev8 a0, a0
+; RV64ZBKB-NEXT: ret
+ %zext = zext i16 %a to i64
+ %val = call i64 @llvm.riscv.brev8(i64 %zext)
+ %trunc = trunc i64 %val to i16
+ ret i16 %trunc
+}
+
declare i64 @llvm.bswap.i64(i64)
define i64 @rev8_i64(i64 %a) {