#if CONFIG_IS_ENABLED(DM_GPIO)
+/**
+ * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
+ * @nbanks: number of PIO banks
+ * @last_bank_count: number of lines in the last bank (can be less than
+ * the rest of the banks).
+ */
struct atmel_pioctrl_data {
u32 nbanks;
+ u32 last_bank_count;
};
struct atmel_pio4_plat {
NULL);
uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK;
+ /* if last bank has limited number of pins, adjust accordingly */
+ if (pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
+ uc_priv->gpio_count -= ATMEL_PIO_NPINS_PER_BANK;
+ uc_priv->gpio_count += pioctrl_data->last_bank_count;
+ }
+
return 0;
}
*/
static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
.nbanks = 4,
+ .last_bank_count = ATMEL_PIO_NPINS_PER_BANK,
+};
+
+static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
+ .nbanks = 5,
+ .last_bank_count = 8, /* 5th bank has only 8 lines on sama7g5 */
};
static const struct udevice_id atmel_pio4_ids[] = {
{
.compatible = "atmel,sama5d2-gpio",
.data = (ulong)&atmel_sama5d2_pioctrl_data,
+ }, {
+ .compatible = "microchip,sama7g5-gpio",
+ .data = (ulong)µchip_sama7g5_pioctrl_data,
},
{}
};