+2000-07-27 Alan Modra <alan@linuxcare.com.au>
+
+ * config/tc-d10v.c (find_opcode): Remove extraneous `='.
+
+2000-07-27 Kazu Hirata <kazu@hxi.com>
+
+ * config/tc-d10v.c: Fix formatting.
+ * config/tc-z8k.c: Likewise.
+ * config/tc-sparc.c: Likewise.
+
2000-07-26 Dave Brolley <brolley@redhat.com>
* cgen.c (queue_fixup): Declare opinfo.
/* tc-d10v.c -- Assembler code for the Mitsubishi D10V
- Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation.
+ Copyright (C) 1996, 97, 98, 99, 2000 Free Software Foundation.
This file is part of GAS, the GNU Assembler.
#include <stdio.h>
#include <ctype.h>
#include "as.h"
-#include "subsegs.h"
+#include "subsegs.h"
#include "opcode/d10v.h"
#include "elf/ppc.h"
&& S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT)
#define AT_WORD_RIGHT_SHIFT 2
-
-/* fixups */
+/* Fixups. */
#define MAX_INSN_FIXUPS (5)
struct d10v_fixup
{
static int do_not_ignore_hash = 0;
typedef int packing_type;
-#define PACK_UNSPEC (0) /* packing order not specified */
-#define PACK_PARALLEL (1) /* "||" */
-#define PACK_LEFT_RIGHT (2) /* "->" */
-#define PACK_RIGHT_LEFT (3) /* "<-" */
-static packing_type etype = PACK_UNSPEC; /* used by d10v_cleanup */
+#define PACK_UNSPEC (0) /* Packing order not specified. */
+#define PACK_PARALLEL (1) /* "||" */
+#define PACK_LEFT_RIGHT (2) /* "->" */
+#define PACK_RIGHT_LEFT (3) /* "<-" */
+static packing_type etype = PACK_UNSPEC; /* Used by d10v_cleanup. */
/* True if instruction swapping warnings should be inhibited. */
-static unsigned char flag_warn_suppress_instructionswap; /* --nowarnswap */
+static unsigned char flag_warn_suppress_instructionswap; /* --nowarnswap */
-/* local functions */
+/* Local functions. */
static int reg_name_search PARAMS ((char *name));
static int register_name PARAMS ((expressionS *expressionP));
static int check_range PARAMS ((unsigned long num, int bits, int flags));
static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn));
static void write_long PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
-static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
+static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
struct d10v_opcode *opcode2, unsigned long insn2, packing_type exec_type, Fixups *fx));
static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode));
static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type,
offsetT value, int left, fixS *fix));
-static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
+static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
struct d10v_opcode *opcode2, unsigned long insn2,
packing_type exec_type));
static symbolS * find_symbol_matching_register PARAMS ((expressionS *));
{"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP},
{NULL, no_argument, NULL, 0}
};
-size_t md_longopts_size = sizeof(md_longopts);
+size_t md_longopts_size = sizeof(md_longopts);
static void d10v_dot_word PARAMS ((int));
/* Opcode hash table. */
static struct hash_control *d10v_hash;
-/* reg_name_search does a binary search of the d10v_predefined_registers
- array to see if "name" is a valid regiter name. Returns the register
- number from the array on success, or -1 on failure. */
+/* Do a binary search of the d10v_predefined_registers array to see if
+ NAME is a valid regiter name. Return the register number from the
+ array on success, or -1 on failure. */
static int
reg_name_search (name)
int cmp;
low = 0;
- high = d10v_reg_name_cnt() - 1;
+ high = d10v_reg_name_cnt () - 1;
do
{
high = middle - 1;
else if (cmp > 0)
low = middle + 1;
- else
- return d10v_predefined_registers[middle].value;
+ else
+ return d10v_predefined_registers[middle].value;
}
while (low <= high);
return -1;
}
-/* register_name() checks the string at input_line_pointer
- to see if it is a valid register name */
+/* Check the string at input_line_pointer
+ to see if it is a valid register name. */
static int
register_name (expressionP)
{
int reg_number;
char c, *p = input_line_pointer;
-
- while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')')
+
+ while (*p
+ && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')')
p++;
c = *p;
if (c)
*p++ = 0;
- /* look to see if it's in the register table */
+ /* Look to see if it's in the register table. */
reg_number = reg_name_search (input_line_pointer);
- if (reg_number >= 0)
+ if (reg_number >= 0)
{
expressionP->X_op = O_register;
- /* temporarily store a pointer to the string here */
- expressionP->X_op_symbol = (symbolS *)input_line_pointer;
+ /* Temporarily store a pointer to the string here. */
+ expressionP->X_op_symbol = (symbolS *) input_line_pointer;
expressionP->X_add_number = reg_number;
input_line_pointer = p;
return 1;
}
if (c)
- *(p-1) = c;
+ *(p - 1) = c;
return 0;
}
-
static int
check_range (num, bits, flags)
unsigned long num;
int flags;
{
long min, max, bit1;
- int retval=0;
+ int retval = 0;
- /* don't bother checking 16-bit values */
+ /* Don't bother checking 16-bit values. */
if (bits == 16)
return 0;
if (flags & OPERAND_SHIFT)
{
- /* all special shift operands are unsigned */
- /* and <= 16. We allow 0 for now. */
- if (num>16)
+ /* All special shift operands are unsigned and <= 16.
+ We allow 0 for now. */
+ if (num > 16)
return 1;
else
return 0;
if (flags & OPERAND_SIGNED)
{
- /* Signed 3-bit integers are restricted to the (-2, 3) range */
+ /* Signed 3-bit integers are restricted to the (-2, 3) range. */
if (flags & RESTRICTED_NUM3)
{
if ((long) num < -2 || (long) num > 3)
}
else
{
- max = (1 << (bits - 1)) - 1;
- min = - (1 << (bits - 1));
+ max = (1 << (bits - 1)) - 1;
+ min = - (1 << (bits - 1));
if (((long) num > max) || ((long) num < min))
retval = 1;
}
return retval;
}
-
void
md_show_usage (stream)
- FILE *stream;
+ FILE *stream;
{
- fprintf(stream, _("D10V options:\n\
+ fprintf (stream, _("D10V options:\n\
-O optimize. Will do some operations in parallel.\n"));
-}
+}
int
md_parse_option (c, arg)
switch (c)
{
case 'O':
- /* Optimize. Will attempt to parallelize operations */
+ /* Optimize. Will attempt to parallelize operations. */
Optimizing = 1;
break;
case OPTION_NOWARNSWAP:
symbolS *
md_undefined_symbol (name)
- char *name;
+ char *name;
{
return 0;
}
-/* Turn a string in input_line_pointer into a floating point constant of type
- type, and store the appropriate bytes in *litP. The number of LITTLENUMS
- emitted is stored in *sizeP . An error message is returned, or NULL on OK.
- */
+/* Turn a string in input_line_pointer into a floating point constant
+ of type TYPE, and store the appropriate bytes in *LITP. The number
+ of LITTLENUMS emitted is stored in *SIZEP. An error message is
+ returned, or NULL on OK. */
+
char *
md_atof (type, litP, sizeP)
int type;
LITTLENUM_TYPE words[4];
char *t;
int i;
-
+
switch (type)
{
case 'f':
t = atof_ieee (input_line_pointer, type, words);
if (t)
input_line_pointer = t;
-
+
*sizeP = prec * 2;
-
+
for (i = 0; i < prec; i++)
{
md_number_to_chars (litP, (valueT) words[i], 2);
- litP += 2;
+ litP += 2;
}
return NULL;
}
void
md_convert_frag (abfd, sec, fragP)
- bfd *abfd;
- asection *sec;
- fragS *fragP;
+ bfd *abfd;
+ asection *sec;
+ fragS *fragP;
{
abort ();
}
return ((addr + (1 << align) - 1) & (-1 << align));
}
-
void
md_begin ()
{
char *prev_name = "";
struct d10v_opcode *opcode;
- d10v_hash = hash_new();
+ d10v_hash = hash_new ();
/* Insert unique names into hash table. The D10v instruction set
has many identical opcode names that have different opcodes based
on the operands. This hash table then provides a quick index to
the first opcode with a particular name in the opcode table. */
- for (opcode = (struct d10v_opcode *)d10v_opcodes; opcode->name; opcode++)
+ for (opcode = (struct d10v_opcode *) d10v_opcodes; opcode->name; opcode++)
{
if (strcmp (prev_name, opcode->name))
{
- prev_name = (char *)opcode->name;
+ prev_name = (char *) opcode->name;
hash_insert (d10v_hash, opcode->name, (char *) opcode);
}
}
FixUps[1].next = &FixUps[0];
}
+/* Remove the postincrement or postdecrement operator ( '+' or '-' )
+ from an expression. */
-/* this function removes the postincrement or postdecrement
- operator ( '+' or '-' ) from an expression */
-
-static int postfix (p)
+static int
+postfix (p)
char *p;
{
- while (*p != '-' && *p != '+')
+ while (*p != '-' && *p != '+')
{
- if (*p==0 || *p=='\n' || *p=='\r')
+ if (*p == 0 || *p == '\n' || *p == '\r')
break;
p++;
}
- if (*p == '-')
+ if (*p == '-')
{
*p = ' ';
return (-1);
}
- if (*p == '+')
+ if (*p == '+')
{
*p = ' ';
return (1);
return (0);
}
-
-static bfd_reloc_code_real_type
-get_reloc (op)
+static bfd_reloc_code_real_type
+get_reloc (op)
struct d10v_operand *op;
{
int bits = op->bits;
- if (bits <= 4)
+ if (bits <= 4)
return (0);
-
- if (op->flags & OPERAND_ADDR)
+
+ if (op->flags & OPERAND_ADDR)
{
if (bits == 8)
return (BFD_RELOC_D10V_10_PCREL_R);
return (BFD_RELOC_16);
}
-
-/* get_operands parses a string of operands and returns
- an array of expressions */
+/* Parse a string of operands. Return an array of expressions. */
static int
-get_operands (exp)
+get_operands (exp)
expressionS exp[];
{
char *p = input_line_pointer;
int numops = 0;
int post = 0;
int uses_at = 0;
-
- while (*p)
+
+ while (*p)
{
- while (*p == ' ' || *p == '\t' || *p == ',')
+ while (*p == ' ' || *p == '\t' || *p == ',')
p++;
- if (*p==0 || *p=='\n' || *p=='\r')
+ if (*p == 0 || *p == '\n' || *p == '\r')
break;
-
- if (*p == '@')
+
+ if (*p == '@')
{
uses_at = 1;
-
+
p++;
exp[numops].X_op = O_absent;
- if (*p == '(')
+ if (*p == '(')
{
p++;
exp[numops].X_add_number = OPERAND_ATPAR;
}
- else if (*p == '-')
+ else if (*p == '-')
{
p++;
exp[numops].X_add_number = OPERAND_ATMINUS;
continue;
}
- if (*p == ')')
+ if (*p == ')')
{
- /* just skip the trailing paren */
+ /* Just skip the trailing paren. */
p++;
continue;
}
input_line_pointer = p;
- /* check to see if it might be a register name */
+ /* Check to see if it might be a register name. */
if (!register_name (&exp[numops]))
{
- /* parse as an expression */
+ /* Parse as an expression. */
if (uses_at)
{
/* Any expression that involves the indirect addressing
the use of the hash character is illegal. */
int save = do_not_ignore_hash;
do_not_ignore_hash = 1;
-
+
expression (&exp[numops]);
-
+
do_not_ignore_hash = save;
}
else
input_line_pointer += 5;
if (exp[numops].X_op == O_register)
{
- /* if it looked like a register name but was followed by
+ /* If it looked like a register name but was followed by
"@word" then it was really a symbol, so change it to
- one */
+ one. */
exp[numops].X_op = O_symbol;
- exp[numops].X_add_symbol = symbol_find_or_make ((char *)exp[numops].X_op_symbol);
+ exp[numops].X_add_symbol =
+ symbol_find_or_make ((char *) exp[numops].X_op_symbol);
}
- /* check for identifier@word+constant */
+ /* Check for identifier@word+constant. */
if (*input_line_pointer == '-' || *input_line_pointer == '+')
- {
- char *orig_line = input_line_pointer;
- expressionS new_exp;
- expression (&new_exp);
- exp[numops].X_add_number = new_exp.X_add_number;
- }
+ {
+ char *orig_line = input_line_pointer;
+ expressionS new_exp;
+ expression (&new_exp);
+ exp[numops].X_add_number = new_exp.X_add_number;
+ }
- /* convert expr into a right shift by AT_WORD_RIGHT_SHIFT */
+ /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT. */
{
expressionS new_exp;
memset (&new_exp, 0, sizeof new_exp);
know (AT_WORD_P (&exp[numops]));
}
-
- if (exp[numops].X_op == O_illegal)
+
+ if (exp[numops].X_op == O_illegal)
as_bad (_("illegal operand"));
- else if (exp[numops].X_op == O_absent)
+ else if (exp[numops].X_op == O_absent)
as_bad (_("missing operand"));
numops++;
p = input_line_pointer;
}
- switch (post)
+ switch (post)
{
- case -1: /* postdecrement mode */
+ case -1: /* Postdecrement mode. */
exp[numops].X_op = O_absent;
exp[numops++].X_add_number = OPERAND_MINUS;
break;
- case 1: /* postincrement mode */
+ case 1: /* Postincrement mode. */
exp[numops].X_op = O_absent;
exp[numops++].X_add_number = OPERAND_PLUS;
break;
}
static unsigned long
-d10v_insert_operand (insn, op_type, value, left, fix)
+d10v_insert_operand (insn, op_type, value, left, fix)
unsigned long insn;
int op_type;
offsetT value;
bits = d10v_operands[op_type].bits;
- /* truncate to the proper number of bits */
+ /* Truncate to the proper number of bits. */
if (check_range (value, bits, d10v_operands[op_type].flags))
as_bad_where (fix->fx_file, fix->fx_line, _("operand out of range: %d"), value);
return insn;
}
-
-/* build_insn takes a pointer to the opcode entry in the opcode table
- and the array of operand expressions and returns the instruction */
+/* Take a pointer to the opcode entry in the opcode table and the
+ array of operand expressions. Return the instruction. */
static unsigned long
-build_insn (opcode, opers, insn)
+build_insn (opcode, opers, insn)
struct d10v_opcode *opcode;
expressionS *opers;
unsigned long insn;
{
int i, bits, shift, flags, format;
unsigned long number;
-
- /* the insn argument is only used for the DIVS kludge */
+
+ /* The insn argument is only used for the DIVS kludge. */
if (insn)
format = LONG_R;
else
insn = opcode->opcode;
format = opcode->format;
}
-
- for (i=0;opcode->operands[i];i++)
+
+ for (i = 0; opcode->operands[i]; i++)
{
flags = d10v_operands[opcode->operands[i]].flags;
bits = d10v_operands[opcode->operands[i]].bits;
shift = d10v_operands[opcode->operands[i]].shift;
number = opers[i].X_add_number;
- if (flags & OPERAND_REG)
+ if (flags & OPERAND_REG)
{
number &= REGISTER_MASK;
if (format == LONG_L)
shift += 15;
}
- if (opers[i].X_op != O_register && opers[i].X_op != O_constant)
+ if (opers[i].X_op != O_register && opers[i].X_op != O_constant)
{
- /* now create a fixup */
+ /* Now create a fixup. */
if (fixups->fc >= MAX_INSN_FIXUPS)
as_fatal (_("too many fixups"));
if (AT_WORD_P (&opers[i]))
{
- /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD) */
+ /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD). */
fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18;
opers[i].X_op = O_symbol;
- opers[i].X_op_symbol = NULL; /* Should free it */
+ opers[i].X_op_symbol = NULL; /* Should free it. */
/* number is left shifted by AT_WORD_RIGHT_SHIFT so
that, it is aligned with the symbol's value. Later,
BFD_RELOC_D10V_18 will right shift (symbol_value +
- X_add_number). */
+ X_add_number). */
number <<= AT_WORD_RIGHT_SHIFT;
opers[i].X_add_number = number;
}
else
- fixups->fix[fixups->fc].reloc =
- get_reloc((struct d10v_operand *)&d10v_operands[opcode->operands[i]]);
+ fixups->fix[fixups->fc].reloc =
+ get_reloc ((struct d10v_operand *) &d10v_operands[opcode->operands[i]]);
- if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 ||
+ if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 ||
fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18)
- fixups->fix[fixups->fc].size = 2;
+ fixups->fix[fixups->fc].size = 2;
else
fixups->fix[fixups->fc].size = 4;
-
+
fixups->fix[fixups->fc].exp = opers[i];
fixups->fix[fixups->fc].operand = opcode->operands[i];
- fixups->fix[fixups->fc].pcrel = (flags & OPERAND_ADDR) ? true : false;
+ fixups->fix[fixups->fc].pcrel =
+ (flags & OPERAND_ADDR) ? true : false;
(fixups->fc)++;
}
- /* truncate to the proper number of bits */
+ /* Truncate to the proper number of bits. */
if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
- as_bad (_("operand out of range: %d"),number);
+ as_bad (_("operand out of range: %d"), number);
number &= 0x7FFFFFFF >> (31 - bits);
insn = insn | (number << shift);
}
- /* kludge: for DIVS, we need to put the operands in twice */
- /* on the second pass, format is changed to LONG_R to force */
- /* the second set of operands to not be shifted over 15 */
- if ((opcode->opcode == OPCODE_DIVS) && (format==LONG_L))
+ /* kludge: for DIVS, we need to put the operands in twice */
+ /* on the second pass, format is changed to LONG_R to force
+ the second set of operands to not be shifted over 15. */
+ if ((opcode->opcode == OPCODE_DIVS) && (format == LONG_L))
insn = build_insn (opcode, opers, insn);
-
+
return insn;
}
-/* write out a long form instruction */
+/* Write out a long form instruction. */
+
static void
-write_long (opcode, insn, fx)
+write_long (opcode, insn, fx)
struct d10v_opcode *opcode;
unsigned long insn;
Fixups *fx;
{
int i, where;
- char *f = frag_more(4);
+ char *f = frag_more (4);
insn |= FM11;
number_to_chars_bigendian (f, insn, 4);
- for (i=0; i < fx->fc; i++)
+ for (i = 0; i < fx->fc; i++)
{
if (fx->fix[i].reloc)
- {
- where = f - frag_now->fr_literal;
+ {
+ where = f - frag_now->fr_literal;
if (fx->fix[i].size == 2)
where += 2;
if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
- fx->fix[i].operand |= 4096;
+ fx->fix[i].operand |= 4096;
fix_new_exp (frag_now,
where,
fx->fc = 0;
}
+/* Write out a short form instruction by itself. */
-/* write out a short form instruction by itself */
static void
-write_1_short (opcode, insn, fx)
+write_1_short (opcode, insn, fx)
struct d10v_opcode *opcode;
unsigned long insn;
Fixups *fx;
{
- char *f = frag_more(4);
+ char *f = frag_more (4);
int i, where;
if (opcode->exec_type & PARONLY)
as_fatal (_("Instruction must be executed in parallel with another instruction."));
- /* the other container needs to be NOP */
- /* according to 4.3.1: for FM=00, sub-instructions performed only
- by IU cannot be encoded in L-container. */
+ /* The other container needs to be NOP. */
+ /* According to 4.3.1: for FM=00, sub-instructions performed only
+ by IU cannot be encoded in L-container. */
if (opcode->unit == IU)
- insn |= FM00 | (NOP << 15); /* right container */
+ insn |= FM00 | (NOP << 15); /* Right container. */
else
- insn = FM00 | (insn << 15) | NOP; /* left container */
+ insn = FM00 | (insn << 15) | NOP; /* Left container. */
number_to_chars_bigendian (f, insn, 4);
- for (i=0; i < fx->fc; i++)
+ for (i = 0; i < fx->fc; i++)
{
if (fx->fix[i].reloc)
- {
- where = f - frag_now->fr_literal;
+ {
+ where = f - frag_now->fr_literal;
if (fx->fix[i].size == 2)
where += 2;
if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
- fx->fix[i].operand |= 4096;
+ fx->fix[i].operand |= 4096;
- /* if it's an R reloc, we may have to switch it to L */
- if ( (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (opcode->unit != IU) )
+ /* If it's an R reloc, we may have to switch it to L. */
+ if ((fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R)
+ && (opcode->unit != IU))
fx->fix[i].operand |= 1024;
fix_new_exp (frag_now,
- where,
+ where,
fx->fix[i].size,
&(fx->fix[i].exp),
fx->fix[i].pcrel,
/* Expects two short instructions.
If possible, writes out both as a single packed instruction.
Otherwise, writes out the first one, packed with a NOP.
- Returns number of instructions not written out. */
+ Returns number of instructions not written out. */
static int
-write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
+write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
struct d10v_opcode *opcode1, *opcode2;
unsigned long insn1, insn2;
packing_type exec_type;
{
unsigned long insn;
char *f;
- int i,j, where;
+ int i, j, where;
- if ( (exec_type != PACK_PARALLEL) && ((opcode1->exec_type & PARONLY)
- || (opcode2->exec_type & PARONLY)))
+ if ((exec_type != PACK_PARALLEL)
+ && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY)))
as_fatal (_("Instruction must be executed in parallel"));
-
- if ( (opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
- as_fatal (_("Long instructions may not be combined."));
+ if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
+ as_fatal (_("Long instructions may not be combined."));
- switch (exec_type)
+ switch (exec_type)
{
- case PACK_UNSPEC: /* order not specified */
+ case PACK_UNSPEC: /* Order not specified. */
if (opcode1->exec_type & ALONE)
{
- /* Case of a short branch on a separate GAS line. Pack with NOP. */
+ /* Case of a short branch on a separate GAS line.
+ Pack with NOP. */
write_1_short (opcode1, insn1, fx->next);
return 1;
}
- if (Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
+ if (Optimizing
+ && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
{
- /* parallel */
+ /* Parallel. */
if (opcode1->unit == IU)
insn = FM00 | (insn2 << 15) | insn1;
else if (opcode2->unit == MU)
insn = FM00 | (insn2 << 15) | insn1;
else
{
- insn = FM00 | (insn1 << 15) | insn2;
- /* Advance over dummy fixup since packed insn1 in L */
+ insn = FM00 | (insn1 << 15) | insn2;
+ /* Advance over dummy fixup since packed insn1 in L. */
fx = fx->next;
}
}
- else if (opcode1->unit == IU)
- /* reverse sequential with IU opcode1 on right and done first */
+ else if (opcode1->unit == IU)
+ /* Reverse sequential with IU opcode1 on right and done first. */
insn = FM10 | (insn2 << 15) | insn1;
else
{
- /* sequential with non-IU opcode1 on left and done first */
+ /* Sequential with non-IU opcode1 on left and done first. */
insn = FM01 | (insn1 << 15) | insn2;
- /* Advance over dummy fixup since packed insn1 in L */
+ /* Advance over dummy fixup since packed insn1 in L. */
fx = fx->next;
}
break;
-
case PACK_PARALLEL:
if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ)
- as_fatal
- (_("One of these instructions may not be executed in parallel."));
+ as_fatal
+ (_("One of these instructions may not be executed in parallel."));
if (opcode1->unit == IU)
{
if (opcode2->unit == IU)
as_fatal (_("Two IU instructions may not be executed in parallel"));
- if (!flag_warn_suppress_instructionswap)
+ if (!flag_warn_suppress_instructionswap)
as_warn (_("Swapping instruction order"));
- insn = FM00 | (insn2 << 15) | insn1;
+ insn = FM00 | (insn2 << 15) | insn1;
}
else if (opcode2->unit == MU)
{
if (opcode1->unit == MU)
as_fatal (_("Two MU instructions may not be executed in parallel"));
- if (!flag_warn_suppress_instructionswap)
+ if (!flag_warn_suppress_instructionswap)
as_warn (_("Swapping instruction order"));
insn = FM00 | (insn2 << 15) | insn1;
}
else
{
- insn = FM00 | (insn1 << 15) | insn2;
- /* Advance over dummy fixup since packed insn1 in L */
+ insn = FM00 | (insn1 << 15) | insn2;
+ /* Advance over dummy fixup since packed insn1 in L. */
fx = fx->next;
}
break;
-
case PACK_LEFT_RIGHT:
if (opcode1->unit != IU)
- insn = FM01 | (insn1 << 15) | insn2;
+ insn = FM01 | (insn1 << 15) | insn2;
else if (opcode2->unit == MU || opcode2->unit == EITHER)
{
- if (!flag_warn_suppress_instructionswap)
+ if (!flag_warn_suppress_instructionswap)
as_warn (_("Swapping instruction order"));
insn = FM10 | (insn2 << 15) | insn1;
}
as_fatal (_("IU instruction may not be in the left container"));
if (opcode1->exec_type & ALONE)
as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
- /* Advance over dummy fixup */
+ /* Advance over dummy fixup. */
fx = fx->next;
break;
-
case PACK_RIGHT_LEFT:
if (opcode2->unit != MU)
insn = FM10 | (insn1 << 15) | insn2;
else if (opcode1->unit == IU || opcode1->unit == EITHER)
{
- if (!flag_warn_suppress_instructionswap)
+ if (!flag_warn_suppress_instructionswap)
as_warn (_("Swapping instruction order"));
- insn = FM01 | (insn2 << 15) | insn1;
+ insn = FM01 | (insn2 << 15) | insn1;
}
else
as_fatal (_("MU instruction may not be in the right container"));
if (opcode2->exec_type & ALONE)
as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
- /* Advance over dummy fixup */
+ /* Advance over dummy fixup. */
fx = fx->next;
break;
-
default:
as_fatal (_("unknown execution type passed to write_2_short()"));
}
-
- f = frag_more(4);
+ f = frag_more (4);
number_to_chars_bigendian (f, insn, 4);
- /* Process fixup chains.
+ /* Process fixup chains.
Note that the packing code above advanced fx conditionally.
dlindsay@cygnus.com: There's something subtle going on here involving
_dummy_first_bfd_reloc_code_real. This is related to the
difference between BFD_RELOC_D10V_10_PCREL_R and _L, ie whether
a fixup is done in the L or R container. A bug in this code
- can pass Plum Hall fine, yet still affect hand-written assembler. */
+ can pass Plum Hall fine, yet still affect hand-written assembler. */
- for (j=0; j<2; j++)
+ for (j = 0; j < 2; j++)
{
- for (i=0; i < fx->fc; i++)
+ for (i = 0; i < fx->fc; i++)
{
if (fx->fix[i].reloc)
{
- where = f - frag_now->fr_literal;
+ where = f - frag_now->fr_literal;
if (fx->fix[i].size == 2)
where += 2;
-
- if ( (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (j == 0) )
+
+ if ((fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (j == 0))
fx->fix[i].operand |= 1024;
-
+
if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
- fx->fix[i].operand |= 4096;
+ fx->fix[i].operand |= 4096;
fix_new_exp (frag_now,
- where,
+ where,
fx->fix[i].size,
&(fx->fix[i].exp),
fx->fix[i].pcrel,
return (0);
}
+/* Check 2 instructions and determine if they can be safely
+ executed in parallel. Return 1 if they can be. */
-/* Check 2 instructions and determine if they can be safely */
-/* executed in parallel. Returns 1 if they can be. */
static int
parallel_ok (op1, insn1, op2, insn2, exec_type)
struct d10v_opcode *op1, *op2;
return 0;
/* If this is auto parallization, and either instruction is a branch,
- don't parallel. */
+ don't parallel. */
if (exec_type == PACK_UNSPEC
&& (op1->exec_type & ALONE || op2->exec_type & ALONE))
return 0;
memory and the second reads, then they cannot be done in
parallel. Likewise, if the first instruction mucks with the psw
and the second reads the PSW (which includes C, F0, and F1), then
- they cannot operate safely in parallel. */
+ they cannot operate safely in parallel. */
- /* the bitmasks (mod and used) look like this (bit 31 = MSB) */
- /* r0-r15 0-15 */
- /* a0-a1 16-17 */
- /* cr (not psw) 18 */
- /* psw 19 */
- /* mem 20 */
+ /* The bitmasks (mod and used) look like this (bit 31 = MSB). */
+ /* r0-r15 0-15 */
+ /* a0-a1 16-17 */
+ /* cr (not psw) 18 */
+ /* psw 19 */
+ /* mem 20 */
- for (j=0;j<2;j++)
+ for (j = 0; j < 2; j++)
{
if (j == 0)
{
if (flags & OPERAND_REG)
{
regno = (ins >> shift) & mask;
- if (flags & (OPERAND_ACC0|OPERAND_ACC1))
+ if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
regno += 16;
- else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */
- {
+ else if (flags & OPERAND_CONTROL) /* mvtc or mvfc. */
+ {
if (regno == 0)
regno = 19;
else
- regno = 18;
+ regno = 18;
}
- else if (flags & (OPERAND_FFLAG|OPERAND_CFLAG))
+ else if (flags & (OPERAND_FFLAG | OPERAND_CFLAG))
regno = 19;
-
- if ( flags & OPERAND_DEST )
+
+ if (flags & OPERAND_DEST)
{
mod[j] |= 1 << regno;
if (flags & OPERAND_EVEN)
}
else
{
- used[j] |= 1 << regno ;
+ used[j] |= 1 << regno;
if (flags & OPERAND_EVEN)
used[j] |= 1 << (regno + 1);
/* Auto inc/dec also modifies the register. */
- if (op->operands[i+1] != 0
- && (d10v_operands[op->operands[i+1]].flags
+ if (op->operands[i + 1] != 0
+ && (d10v_operands[op->operands[i + 1]].flags
& (OPERAND_PLUS | OPERAND_MINUS)) != 0)
mod[j] |= 1 << regno;
}
}
else if (flags & OPERAND_ATMINUS)
{
- /* SP implicitly used/modified */
+ /* SP implicitly used/modified. */
mod[j] |= 1 << 15;
used[j] |= 1 << 15;
}
return 0;
}
-
-/* This is the main entry point for the machine-dependent assembler. str points to a
- machine-dependent instruction. This function is supposed to emit the frags/bytes
- it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing
- and leaves the difficult stuff to do_assemble().
- */
+/* This is the main entry point for the machine-dependent assembler.
+ STR points to a machine-dependent instruction. This function is
+ supposed to emit the frags/bytes it assembles to. For the D10V, it
+ mostly handles the special VLIW parsing and packing and leaves the
+ difficult stuff to do_assemble(). */
static unsigned long prev_insn;
static struct d10v_opcode *prev_opcode = 0;
md_assemble (str)
char *str;
{
- /* etype is saved extype. for multiline instructions */
+ /* etype is saved extype. For multi-line instructions. */
- packing_type extype = PACK_UNSPEC; /* parallel, etc */
+ packing_type extype = PACK_UNSPEC; /* Parallel, etc. */
- struct d10v_opcode * opcode;
+ struct d10v_opcode *opcode;
unsigned long insn;
- char * str2;
+ char *str2;
if (etype == PACK_UNSPEC)
{
- /* look for the special multiple instruction separators */
+ /* Look for the special multiple instruction separators. */
str2 = strstr (str, "||");
- if (str2)
+ if (str2)
extype = PACK_PARALLEL;
else
{
str2 = strstr (str, "->");
- if (str2)
+ if (str2)
extype = PACK_LEFT_RIGHT;
else
{
str2 = strstr (str, "<-");
- if (str2)
+ if (str2)
extype = PACK_RIGHT_LEFT;
}
}
- /* str2 points to the separator, if one */
- if (str2)
+ /* STR2 points to the separator, if there is one. */
+ if (str2)
{
*str2 = 0;
-
- /* if two instructions are present and we already have one saved
- then first write out the save one */
+
+ /* If two instructions are present and we already have one saved,
+ then first write out the saved one. */
d10v_cleanup ();
-
- /* assemble first instruction and save it */
+
+ /* Assemble first instruction and save it. */
prev_insn = do_assemble (str, &prev_opcode);
if (prev_insn == -1)
as_fatal (_("can't find opcode "));
etype = PACK_UNSPEC;
}
- /* if this is a long instruction, write it and any previous short instruction */
- if (opcode->format & LONG_OPCODE)
+ /* If this is a long instruction, write it and any previous short
+ instruction. */
+ if (opcode->format & LONG_OPCODE)
{
- if (extype != PACK_UNSPEC)
+ if (extype != PACK_UNSPEC)
as_fatal (_("Unable to mix instructions as specified"));
d10v_cleanup ();
write_long (opcode, insn, fixups);
prev_opcode = NULL;
return;
}
-
- if (prev_opcode && prev_seg && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
+
+ if (prev_opcode
+ && prev_seg
+ && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
d10v_cleanup ();
-
- if (prev_opcode && (write_2_short (prev_opcode, prev_insn, opcode, insn, extype, fixups) == 0))
+
+ if (prev_opcode
+ && (write_2_short (prev_opcode, prev_insn, opcode, insn, extype, fixups) == 0))
{
- /* no instructions saved */
+ /* No instructions saved. */
prev_opcode = NULL;
}
else
{
- if (extype != PACK_UNSPEC)
+ if (extype != PACK_UNSPEC)
as_fatal (_("Unable to mix instructions as specified"));
- /* save off last instruction so it may be packed on next pass */
+ /* Save last instruction so it may be packed on next pass. */
prev_opcode = opcode;
prev_insn = insn;
prev_seg = now_seg;
}
}
-
-/* do_assemble assembles a single instruction and returns an opcode */
-/* it returns -1 (an invalid opcode) on error */
+/* Assemble a single instruction.
+ Return an opcode, or -1 (an invalid opcode) on error. */
static unsigned long
-do_assemble (str, opcode)
+do_assemble (str, opcode)
char *str;
struct d10v_opcode **opcode;
{
if (nlen == 0)
return -1;
-
+
/* Find the first opcode with the proper name. */
- *opcode = (struct d10v_opcode *)hash_find (d10v_hash, name);
+ *opcode = (struct d10v_opcode *) hash_find (d10v_hash, name);
if (*opcode == NULL)
- as_fatal (_("unknown opcode: %s"),name);
+ as_fatal (_("unknown opcode: %s"), name);
save = input_line_pointer;
input_line_pointer = op_end;
return -1;
input_line_pointer = save;
- insn = build_insn ((*opcode), myops, 0);
+ insn = build_insn ((*opcode), myops, 0);
return (insn);
}
-/* Find the symbol which has the same name as the register in the given expression. */
+/* Find the symbol which has the same name as the register in EXP. */
+
static symbolS *
find_symbol_matching_register (exp)
- expressionS * exp;
+ expressionS *exp;
{
int i;
-
+
if (exp->X_op != O_register)
return NULL;
-
+
/* Find the name of the register. */
for (i = d10v_reg_name_cnt (); i--;)
- if (d10v_predefined_registers [i].value == exp->X_add_number)
+ if (d10v_predefined_registers[i].value == exp->X_add_number)
break;
if (i < 0)
abort ();
/* Now see if a symbol has been defined with the same name. */
- return symbol_find (d10v_predefined_registers [i].name);
+ return symbol_find (d10v_predefined_registers[i].name);
}
-
-/* find_opcode() gets a pointer to an entry in the opcode table. */
-/* It must look at all opcodes with the same name and use the operands */
-/* to choose the correct opcode. */
+/* Get a pointer to an entry in the opcode table.
+ The function must look at all opcodes with the same name and use
+ the operands to choose the correct opcode. */
static struct d10v_opcode *
find_opcode (opcode, myops)
int i, match, done;
struct d10v_opcode *next_opcode;
- /* get all the operands and save them as expressions */
+ /* Get all the operands and save them as expressions. */
get_operands (myops);
- /* now see if the operand is a fake. If so, find the correct size */
- /* instruction, if possible */
+ /* Now see if the operand is a fake. If so, find the correct size
+ instruction, if possible. */
if (opcode->format == OPCODE_FAKE)
{
int opnum = opcode->operands[0];
int flags;
-
+
if (myops[opnum].X_op == O_register)
{
myops[opnum].X_op = O_symbol;
- myops[opnum].X_add_symbol = symbol_find_or_make ((char *)myops[opnum].X_op_symbol);
+ myops[opnum].X_add_symbol =
+ symbol_find_or_make ((char *) myops[opnum].X_op_symbol);
myops[opnum].X_add_number = 0;
myops[opnum].X_op_symbol = NULL;
}
- next_opcode=opcode+1;
+ next_opcode = opcode + 1;
/* If the first operand is supposed to be a register, make sure
we got a valid one. */
}
}
- if (myops[opnum].X_op == O_constant || (myops[opnum].X_op == O_symbol &&
- S_IS_DEFINED(myops[opnum].X_add_symbol) &&
- (S_GET_SEGMENT(myops[opnum].X_add_symbol) == now_seg)))
+ if (myops[opnum].X_op == O_constant
+ || (myops[opnum].X_op == O_symbol
+ && S_IS_DEFINED (myops[opnum].X_add_symbol)
+ && (S_GET_SEGMENT (myops[opnum].X_add_symbol) == now_seg)))
{
- for (i=0; opcode->operands[i+1]; i++)
+ for (i = 0; opcode->operands[i + 1]; i++)
{
int bits = d10v_operands[next_opcode->operands[opnum]].bits;
int flags = d10v_operands[next_opcode->operands[opnum]].flags;
if (flags & OPERAND_ADDR)
bits += 2;
-
+
if (myops[opnum].X_op == O_constant)
{
if (!check_range (myops[opnum].X_add_number, bits, flags))
}
else
{
- fragS * sym_frag;
- fragS * f;
+ fragS *sym_frag;
+ fragS *f;
unsigned long current_position;
unsigned long symbol_position;
unsigned long value;
boolean found_symbol;
-
+
/* Calculate the address of the current instruction
and the address of the symbol. Do this by summing
the offsets of previous frags until we reach the
sym_frag = symbol_get_frag (myops[opnum].X_add_symbol);
found_symbol = false;
- current_position = obstack_next_free (&frchain_now->frch_obstack) - frag_now->fr_literal;
+ current_position =
+ obstack_next_free (&frchain_now->frch_obstack)
+ - frag_now->fr_literal;
symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol);
-
+
for (f = frchain_now->frch_root; f; f = f->fr_next)
{
current_position += f->fr_fix + f->fr_offset;
-
+
if (f == sym_frag)
found_symbol = true;
-
+
if (! found_symbol)
symbol_position += f->fr_fix + f->fr_offset;
}
value = symbol_position;
-
+
if (flags & OPERAND_ADDR)
value -= current_position;
-
+
if (AT_WORD_P (&myops[opnum]))
{
if (bits > 4)
}
else
{
- /* not a constant, so use a long instruction */
- return opcode+2;
+ /* Not a constant, so use a long instruction. */
+ return opcode + 2;
}
}
else
{
match = 0;
- /* now search the opcode table table for one with operands */
- /* that matches what we've got */
+ /* Now search the opcode table table for one with operands
+ that matches what we've got. */
while (!match)
{
match = 1;
- for (i = 0; opcode->operands[i]; i++)
+ for (i = 0; opcode->operands[i]; i++)
{
int flags = d10v_operands[opcode->operands[i]].flags;
int X_op = myops[i].X_op;
match = 0;
break;
}
-
+
if (flags & OPERAND_REG)
{
if ((X_op != O_register)
break;
}
}
-
+
if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) ||
((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) ||
((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) ||
match = 0;
break;
}
-
- /* Unfortunatly, for the indirect operand in instructions such as
- ``ldb r1, @(c,r14)'' this function can be passed X_op == O_register
- (because 'c' is a valid register name). However we cannot just
- ignore the case when X_op == O_register but flags & OPERAND_REG is
- null, so we check to see if a symbol of the same name as the register
- exists. If the symbol does exist, then the parser was unable to
- distinguish the two cases and we fix things here. (Ref: PR14826) */
-
+
+ /* Unfortunatly, for the indirect operand in
+ instructions such as ``ldb r1, @(c,r14)'' this
+ function can be passed X_op == O_register (because
+ 'c' is a valid register name). However we cannot
+ just ignore the case when X_op == O_register but
+ flags & OPERAND_REG is null, so we check to see if a
+ symbol of the same name as the register exists. If
+ the symbol does exist, then the parser was unable to
+ distinguish the two cases and we fix things here.
+ (Ref: PR14826) */
+
if (!(flags & OPERAND_REG) && (X_op == O_register))
{
- symbolS * sym;
-
- sym = find_symbol_matching_register (& myops[i]);
-
+ symbolS *sym = find_symbol_matching_register (&myops[i]);
+
if (sym != NULL)
{
- myops [i].X_op == X_op == O_symbol;
- myops [i].X_add_symbol = sym;
+ myops[i].X_op = X_op = O_symbol;
+ myops[i].X_add_symbol = sym;
}
else
as_bad
(_("illegal operand - register name found where none expected"));
}
}
-
+
/* We're only done if the operands matched so far AND there
are no more to check. */
- if (match && myops[i].X_op == 0)
+ if (match && myops[i].X_op == 0)
break;
else
match = 0;
next_opcode = opcode + 1;
-
- if (next_opcode->opcode == 0)
+
+ if (next_opcode->opcode == 0)
break;
-
+
if (strcmp (next_opcode->name, opcode->name))
break;
-
+
opcode = next_opcode;
}
}
- if (!match)
+ if (!match)
{
as_bad (_("bad opcode or operands"));
return (0);
}
- /* Check that all registers that are required to be even are. */
- /* Also, if any operands were marked as registers, but were really symbols */
- /* fix that here. */
- for (i=0; opcode->operands[i]; i++)
+ /* Check that all registers that are required to be even are.
+ Also, if any operands were marked as registers, but were really symbols,
+ fix that here. */
+ for (i = 0; opcode->operands[i]; i++)
{
if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) &&
- (myops[i].X_add_number & 1))
+ (myops[i].X_add_number & 1))
as_fatal (_("Register number must be EVEN"));
if (myops[i].X_op == O_register)
{
- if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG))
+ if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG))
{
myops[i].X_op = O_symbol;
- myops[i].X_add_symbol = symbol_find_or_make ((char *)myops[i].X_op_symbol);
+ myops[i].X_add_symbol =
+ symbol_find_or_make ((char *) myops[i].X_op_symbol);
myops[i].X_add_number = 0;
myops[i].X_op_symbol = NULL;
}
return opcode;
}
-/* if while processing a fixup, a reloc really needs to be created */
-/* then it is done here */
-
+/* If while processing a fixup, a reloc really needs to be created.
+ Then it is done here. */
+
arelent *
tc_gen_reloc (seg, fixp)
asection *seg;
if (reloc->howto == (reloc_howto_type *) NULL)
{
as_bad_where (fixp->fx_file, fixp->fx_line,
- _("reloc %d not supported by object file format"), (int)fixp->fx_r_type);
+ _("reloc %d not supported by object file format"),
+ (int) fixp->fx_r_type);
return NULL;
}
{
abort ();
return 0;
-}
+}
long
md_pcrel_from_section (fixp, sec)
fixS *fixp;
segT sec;
{
- if (fixp->fx_addsy != (symbolS *)NULL && (!S_IS_DEFINED (fixp->fx_addsy) ||
- (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
+ if (fixp->fx_addsy != (symbolS *) NULL
+ && (!S_IS_DEFINED (fixp->fx_addsy)
+ || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
return 0;
return fixp->fx_frag->fr_address + fixp->fx_where;
}
unsigned long insn;
long value;
int op_type;
- int left=0;
+ int left = 0;
if (fixp->fx_addsy == (symbolS *) NULL)
{
else
{
/* We don't actually support subtracting a symbol. */
- as_bad_where (fixp->fx_file, fixp->fx_line,
+ as_bad_where (fixp->fx_file, fixp->fx_line,
_("expression too complex"));
}
}
fixp->fx_r_type = BFD_RELOC_D10V_18;
}
else
- fixp->fx_r_type = get_reloc((struct d10v_operand *)&d10v_operands[op_type]);
+ fixp->fx_r_type =
+ get_reloc ((struct d10v_operand *) &d10v_operands[op_type]);
}
/* Fetch the instruction, insert the fully resolved operand
case BFD_RELOC_D10V_10_PCREL_R:
case BFD_RELOC_D10V_18_PCREL:
case BFD_RELOC_D10V_18:
- /* instruction addresses are always right-shifted by 2 */
+ /* Instruction addresses are always right-shifted by 2. */
value >>= AT_WORD_RIGHT_SHIFT;
if (fixp->fx_size == 2)
bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
as_fatal
(_("line %d: rep or repi must include at least 4 instructions"),
fixp->fx_line);
- insn = d10v_insert_operand (insn, op_type, (offsetT)value, left, fixp);
- bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
+ insn =
+ d10v_insert_operand (insn, op_type, (offsetT) value, left, fixp);
+ bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
}
break;
case BFD_RELOC_32:
return 1;
default:
- as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp->fx_line,fixp->fx_r_type);
+ as_fatal (_("line %d: unknown relocation type: 0x%x"),
+ fixp->fx_line, fixp->fx_r_type);
}
return 0;
}
-/* d10v_cleanup() is called after the assembler has finished parsing the input
- file or after a label is defined. Because the D10V assembler sometimes saves short
- instructions to see if it can package them with the next instruction, there may
- be a short instruction that still needs written.
+/* Called after the assembler has finished parsing the input file or
+ after a label is defined. Because the D10V assembler sometimes
+ saves short instructions to see if it can package them with the
+ next instruction, there may be a short instruction that still needs
+ to be written.
+
NOTE: accesses a global, etype.
NOTE: invoked by various macros such as md_cleanup: see. */
+
int
d10v_cleanup ()
{
return 1;
}
-/* Like normal .word, except support @word */
-/* clobbers input_line_pointer, checks end-of-line. */
+/* Like normal .word, except support @word. */
+/* Clobbers input_line_pointer, checks end-of-line. */
+
static void
d10v_dot_word (nbytes)
- register int nbytes; /* 1=.byte, 2=.word, 4=.long */
+ register int nbytes; /* 1=.byte, 2=.word, 4=.long */
{
expressionS exp;
bfd_reloc_code_real_type reloc;
{
exp.X_add_number = 0;
input_line_pointer += 5;
-
+
p = frag_more (2);
- fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
+ fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
&exp, 0, BFD_RELOC_D10V_18);
}
else
}
while (*input_line_pointer++ == ',');
- input_line_pointer--; /* Put terminator back into stream. */
+ input_line_pointer--; /* Put terminator back into stream. */
demand_empty_rest_of_line ();
}
+/* Mitsubishi asked that we support some old syntax that apparently
+ had immediate operands starting with '#'. This is in some of their
+ sample code but is not documented (although it appears in some
+ examples in their assembler manual). For now, we'll solve this
+ compatibility problem by simply ignoring any '#' at the beginning
+ of an operand. */
-/* Mitsubishi asked that we support some old syntax that apparently */
-/* had immediate operands starting with '#'. This is in some of their */
-/* sample code but is not documented (although it appears in some */
-/* examples in their assembler manual). For now, we'll solve this */
-/* compatibility problem by simply ignoring any '#' at the beginning */
-/* of an operand. */
+/* Operands that begin with '#' should fall through to here. */
+/* From expr.c. */
-/* operands that begin with '#' should fall through to here */
-/* from expr.c */
-
-void
+void
md_operand (expressionP)
expressionS *expressionP;
{
boolean
d10v_fix_adjustable (fixP)
- fixS *fixP;
+ fixS *fixP;
{
-
if (fixP->fx_addsy == NULL)
return 1;
-
- /* Prevent all adjustments to global symbols. */
+
+ /* Prevent all adjustments to global symbols. */
if (S_IS_EXTERN (fixP->fx_addsy))
return 0;
if (S_IS_WEAK (fixP->fx_addsy))
return 0;
- /* We need the symbol name for the VTABLE entries */
+ /* We need the symbol name for the VTABLE entries. */
if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
return 0;
int
d10v_force_relocation (fixp)
- fixS *fixp;
+ fixS *fixp;
{
if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
/* tc-sparc.c -- Assemble for the SPARC
- Copyright (C) 1989, 90-96, 97, 98, 99, 2000 Free Software Foundation, Inc.
+ Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
+ Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
|| SPARC_OPCODE_ARCH_V9_P (max_architecture))
#endif
-/* handle of the OPCODE hash table */
+/* Handle of the OPCODE hash table. */
static struct hash_control *op_hash;
static int log2 PARAMS ((int));
const pseudo_typeS md_pseudo_table[] =
{
- {"align", s_align_bytes, 0}, /* Defaulting is invalid (0) */
+ {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
{"common", s_common, 0},
{"empty", s_empty, 0},
{"global", s_globl, 0},
{"uaword", s_uacons, 4},
{"uaxword", s_uacons, 8},
#ifdef OBJ_ELF
- /* these are specific to sparc/svr4 */
+ /* These are specific to sparc/svr4. */
{"2byte", s_uacons, 2},
{"4byte", s_uacons, 4},
{"8byte", s_uacons, 8},
{NULL, 0, 0},
};
-const int md_reloc_size = 12; /* Size of relocation record */
+/* Size of relocation record. */
+const int md_reloc_size = 12;
/* This array holds the chars that always start a comment. If the
- pre-processor is disabled, these aren't very useful */
-const char comment_chars[] = "!"; /* JF removed '|' from comment_chars */
+ pre-processor is disabled, these aren't very useful. */
+const char comment_chars[] = "!"; /* JF removed '|' from
+ comment_chars. */
/* This array holds the chars that only start a comment at the beginning of
a line. If the line seems to have the form '# 123 filename'
- .line and .file directives will appear in the pre-processed output */
+ .line and .file directives will appear in the pre-processed output. */
/* Note that input_file.c hand checks for '#' at the beginning of the
first line of the input file. This is because the compiler outputs
- #NO_APP at the beginning of its output. */
+ #NO_APP at the beginning of its output. */
/* Also note that comments started like this one will always
- work if '/' isn't otherwise defined. */
+ work if '/' isn't otherwise defined. */
const char line_comment_chars[] = "#";
const char line_separator_chars[] = ";";
-/* Chars that can be used to separate mant from exp in floating point nums */
+/* Chars that can be used to separate mant from exp in floating point
+ nums. */
const char EXP_CHARS[] = "eE";
-/* Chars that mean this number is a floating point constant */
-/* As in 0f12.456 */
-/* or 0d1.2345e12 */
+/* Chars that mean this number is a floating point constant.
+ As in 0f12.456
+ or 0d1.2345e12 */
const char FLT_CHARS[] = "rRsSfFdDxXpP";
/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
abort ();
}
\f
-/*
- * md_parse_option
+/* md_parse_option
* Invocation line includes a switch not recognized by the base assembler.
* See if it's a processor-specific option. These are:
*
{"no-relax", no_argument, NULL, OPTION_NO_RELAX},
{NULL, no_argument, NULL, 0}
};
-size_t md_longopts_size = sizeof(md_longopts);
+
+size_t md_longopts_size = sizeof (md_longopts);
int
md_parse_option (c, arg)
as_bad (_("invalid architecture -xarch=%s"), arg);
return 0;
}
-
- /* fall through */
+ /* Fall through. */
case 'A':
{
case 'Q':
/* Qy - do emit .comment
- Qn - do not emit .comment */
+ Qn - do not emit .comment. */
break;
case 's':
- /* use .stab instead of .stab.excl */
+ /* Use .stab instead of .stab.excl. */
break;
case 'q':
- /* quick -- native assembler does fewer checks */
+ /* quick -- Native assembler does fewer checks. */
break;
case 'K':
if (! default_init_p)
init_default_arch ();
- fprintf(stream, _("SPARC options:\n"));
+ fprintf (stream, _("SPARC options:\n"));
for (arch = &sparc_arch_table[0]; arch->name; arch++)
{
if (arch != &sparc_arch_table[0])
#endif
}
\f
-/* native operand size opcode translation */
+/* Native operand size opcode translation. */
struct
{
char *name;
{NULL, NULL, NULL},
};
\f
-/* sparc64 priviledged registers */
+/* sparc64 priviledged registers. */
struct priv_reg_entry
{
{"wstate", 14},
{"fq", 15},
{"ver", 31},
- {"", -1}, /* end marker */
+ {"", -1}, /* End marker. */
};
-/* v9a specific asrs */
+/* v9a specific asrs. */
struct priv_reg_entry v9a_asr_table[] =
{
{"gsr", 19},
{"dcr", 18},
{"clear_softint", 21},
- {"", -1}, /* end marker */
+ {"", -1}, /* End marker. */
};
static int
}
\f
/* This function is called once, at assembler startup time. It should
- set up all the tables, etc. that the MD part of the assembler will need. */
+ set up all the tables, etc. that the MD part of the assembler will
+ need. */
void
md_begin ()
const struct sparc_opcode *insn;
char *name = sparc_arch_size == 32 ? native_op_table[i].name32 :
native_op_table[i].name64;
- insn = (struct sparc_opcode *)hash_find (op_hash, name);
+ insn = (struct sparc_opcode *) hash_find (op_hash, name);
if (insn == NULL)
- {
- as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
- name, native_op_table[i].name);
- lose = 1;
- }
+ {
+ as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
+ name, native_op_table[i].name);
+ lose = 1;
+ }
else
{
retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclite_le);
else
{
- /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
- be but for now it is (since that's the way it's always been
- treated). */
+ /* The sparclite is treated like a normal sparc. Perhaps it
+ shouldn't be but for now it is (since that's the way it's
+ always been treated). */
bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
}
}
0xffffffff is always considered -1 on sparc32. */
if (sparc_arch_size == 32)
{
- bfd_signed_vma sign = (bfd_signed_vma)1 << 31;
+ bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
val = ((val & 0xffffffff) ^ sign) - sign;
}
if (val > max)
static unsigned long last_opcode;
\f
/* Handle the set and setuw synthetic instructions. */
+
static void
synthetize_setuw (insn)
const struct sparc_opcode *insn;
{
if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
{
- if (sizeof(offsetT) > 4
+ if (sizeof (offsetT) > 4
&& (the_insn.exp.X_add_number < 0
|| the_insn.exp.X_add_number > (offsetT) 0xffffffff))
as_warn (_("set: number not in 0..4294967295 range"));
}
else
{
- if (sizeof(offsetT) > 4
+ if (sizeof (offsetT) > 4
&& (the_insn.exp.X_add_number < -(offsetT) 0x80000000
|| the_insn.exp.X_add_number > (offsetT) 0xffffffff))
as_warn (_("set: number not in -2147483648..4294967295 range"));
- the_insn.exp.X_add_number = (int)the_insn.exp.X_add_number;
+ the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
}
}
output_insn (insn, &the_insn);
}
}
-
+
/* Handle the setsw synthetic instruction. */
+
static void
synthetize_setsw (insn)
const struct sparc_opcode *insn;
return;
}
- if (sizeof(offsetT) > 4
+ if (sizeof (offsetT) > 4
&& (the_insn.exp.X_add_number < -(offsetT) 0x80000000
|| the_insn.exp.X_add_number > (offsetT) 0xffffffff))
as_warn (_("setsw: number not in -2147483648..4294967295 range"));
- low32 = the_insn.exp.X_add_number;
-
+ low32 = the_insn.exp.X_add_number;
+
if (low32 >= 0)
{
synthetize_setuw (insn);
}
opc = OR_INSN;
-
+
the_insn.reloc = BFD_RELOC_NONE;
/* See if operand is absolute and small; skip sethi if so. */
if (low32 < -(1 << 12))
}
/* Handle the setsw synthetic instruction. */
+
static void
synthetize_setx (insn)
const struct sparc_opcode *insn;
int upper_dstreg;
int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
int need_xor10_p = 0;
-
+
#define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
Otherwise fixup_segment will complain about not being able to
write an 8 byte number in a 4 byte field. */
the_insn.exp.X_add_number = 0;
-
+
/* Only need hh22 if `or' insn can't handle constant. */
if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
need_hh22_p = 1;
-
+
/* Does bottom part (after sethi) have bits? */
if ((need_hh22_p && (upper32 & 0x3ff) != 0)
/* No hh22, but does upper32 still have bits we can't set
from lower32? */
|| (! need_hh22_p && upper32 != 0 && upper32 != -1))
need_hm10_p = 1;
-
+
/* If the lower half is all zero, we build the upper half directly
into the dst reg. */
if (lower32 != 0
|| (lower32 < 0 && upper32 != -1)
|| (lower32 >= 0 && upper32 == -1))
need_hi22_p = 1;
-
+
if (need_hi22_p && upper32 == -1)
need_xor10_p = 1;
/* Output directly to dst reg if lower 32 bits are all zero. */
upper_dstreg = dstreg;
}
-
+
if (!upper_dstreg && dstreg)
as_warn (_("setx: illegal temporary register g0"));
? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
output_insn (insn, &the_insn);
}
-
+
if (need_hi22_p)
{
the_insn.opcode = (SETHI_INSN | RD (dstreg)
? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
output_insn (insn, &the_insn);
}
-
+
if (need_lo10_p)
{
/* FIXME: One nice optimization to do here is to OR the low part
? BFD_RELOC_LO10 : BFD_RELOC_NONE);
output_insn (insn, &the_insn);
}
-
+
/* If we needed to build the upper part, shift it into place. */
if (need_hh22_p || need_hm10_p)
{
the_insn.reloc = BFD_RELOC_NONE;
output_insn (insn, &the_insn);
}
-
+
/* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
if (need_xor10_p)
{
switch (special_case)
{
case SPECIAL_CASE_NONE:
- /* normal insn */
+ /* Normal insn. */
output_insn (insn, &the_insn);
break;
case SPECIAL_CASE_SETSW:
synthetize_setsw (insn);
break;
-
+
case SPECIAL_CASE_SET:
synthetize_setuw (insn);
break;
case SPECIAL_CASE_SETX:
synthetize_setx (insn);
break;
-
+
case SPECIAL_CASE_FDIV:
{
int rd = (the_insn.opcode >> 25) & 0x1f;
-
+
output_insn (insn, &the_insn);
-
+
/* According to information leaked from Sun, the "fdiv" instructions
on early SPARC machines would produce incorrect results sometimes.
The workaround is to add an fmovs of the destination register to
itself just after the instruction. This was true on machines
- with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
+ with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
assert (the_insn.reloc == BFD_RELOC_NONE);
the_insn.opcode = FMOVS_INSN | rd | RD (rd);
output_insn (insn, &the_insn);
return;
}
-
+
default:
as_fatal (_("failed special case insn sanity check"));
}
case ',':
comma = 1;
-
- /*FALLTHROUGH */
+ /* Fall through. */
case ' ':
*s++ = '\0';
the_insn.reloc = BFD_RELOC_NONE;
v9_arg_p = 0;
- /*
- * Build the opcode, checking as we go to make
- * sure that the operands match
- */
+ /* Build the opcode, checking as we go to make sure that the
+ operands match. */
for (args = insn->args;; ++args)
{
switch (*args)
if (*s == '%')
{
struct priv_reg_entry *p = priv_reg_table;
- unsigned int len = 9999999; /* init to make gcc happy */
+ unsigned int len = 9999999; /* Init to make gcc happy. */
s += 1;
while (p->name[0] > s[0])
if (*s == '%')
{
struct priv_reg_entry *p = v9a_asr_table;
- unsigned int len = 9999999; /* init to make gcc happy */
+ unsigned int len = 9999999; /* Init to make gcc happy. */
s += 1;
while (p->name[0] > s[0])
{
error_message = _(": rd on write only ancillary state register");
goto error;
- }
+ }
if (*args == '/')
opcode |= (p->regnum << 14);
else
error_message = _(": expecting %asrN");
goto error;
}
- } /* if %asr */
+ } /* if %asr */
break;
case 'I':
}
break;
- case '\0': /* end of args */
+ case '\0': /* End of args. */
if (*s == '\0')
{
match = 1;
}
break;
- case '[': /* these must match exactly */
+ case '[': /* These must match exactly. */
case ']':
case ',':
case ' ':
continue;
break;
- case '#': /* must be at least one digit */
+ case '#': /* Must be at least one digit. */
if (isdigit ((unsigned char) *s++))
{
while (isdigit ((unsigned char) *s))
}
break;
- case 'C': /* coprocessor state register */
+ case 'C': /* Coprocessor state register. */
if (strncmp (s, "%csr", 4) == 0)
{
s += 4;
}
break;
- case 'b': /* next operand is a coprocessor register */
+ case 'b': /* Next operand is a coprocessor register. */
case 'c':
case 'D':
if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s))
}
if ((mask & ~1) == 2 && sparc_arch_size == 64
- && no_undeclared_regs && ! globals [mask])
+ && no_undeclared_regs && ! globals[mask])
as_bad (_("detected global register use not covered by .register pseudo-op"));
/* Got the register, now figure out where
opcode |= RS1 (mask);
continue;
-
case 'f':
case 'B':
case 'R':
{ NULL }
};
const struct ops *o;
-
+
for (o = ops; o->name; o++)
if (strncmp (s + 1, o->name, o->len) == 0)
break;
if (o->name == NULL)
break;
-
+
if (s[o->len + 1] != '(')
{
as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
return special_case;
}
-
+
*s1 = '\0';
(void) get_expression (s);
*s1 = ')';
*s1 = '0';
s = s1;
op_exp = the_insn.exp;
- memset (&the_insn.exp, 0, sizeof(the_insn.exp));
+ memset (&the_insn.exp, 0, sizeof (the_insn.exp));
}
- for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) ;
+ for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
+ ;
if (s1 != s && isdigit ((unsigned char) s1[-1]))
{
case BFD_RELOC_SPARC_HH22:
val = BSR (val, 32);
- /* intentional fallthrough */
+ /* Fall through. */
case BFD_RELOC_SPARC_LM22:
case BFD_RELOC_HI22:
case BFD_RELOC_SPARC_HM10:
val = BSR (val, 32);
- /* intentional fallthrough */
+ /* Fall through. */
case BFD_RELOC_LO10:
val &= 0x3ff;
}
opcode |= ASI (asi);
continue;
- } /* alternate space */
+ } /* Alternate space. */
case 'p':
if (strncmp (s, "%psr", 4) == 0)
}
break;
- case 'q': /* floating point queue */
+ case 'q': /* Floating point queue. */
if (strncmp (s, "%fq", 3) == 0)
{
s += 3;
}
break;
- case 'Q': /* coprocessor queue */
+ case 'Q': /* Coprocessor queue. */
if (strncmp (s, "%cq", 3) == 0)
{
s += 3;
default:
as_fatal (_("failed sanity check."));
- } /* switch on arg code */
+ } /* switch on arg code. */
/* Break out of for() loop. */
break;
- } /* for each arg that we expect */
+ } /* For each arg that we expect. */
error:
if (match == 0)
{
- /* Args don't match. */
+ /* Args don't match. */
if (&insn[1] - sparc_opcodes < sparc_num_opcodes
&& (insn->name == insn[1].name
|| !strcmp (insn->name, insn[1].name)))
}
else
{
- /* We have a match. Now see if the architecture is ok. */
+ /* We have a match. Now see if the architecture is OK. */
int needed_arch_mask = insn->architecture;
if (v9_arg_p)
needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
}
- if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (current_architecture))
- ; /* ok */
+ if (needed_arch_mask
+ & SPARC_OPCODE_SUPPORTED (current_architecture))
+ /* OK. */
+ ;
/* Can we bump up the architecture? */
- else if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (max_architecture))
+ else if (needed_arch_mask
+ & SPARC_OPCODE_SUPPORTED (max_architecture))
{
enum sparc_opcode_arch_val needed_architecture =
sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
happen but what about tomorrow? */
else
{
- int arch,printed_one_p = 0;
+ int arch, printed_one_p = 0;
char *p;
char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
/* Create a list of the architectures that support the insn. */
- needed_arch_mask &= ~ SPARC_OPCODE_SUPPORTED (max_architecture);
+ needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
p = required_archs;
arch = sparc_ffs (needed_arch_mask);
while ((1 << arch) <= needed_arch_mask)
sparc_opcode_archs[max_architecture].name);
return special_case;
}
- } /* if no match */
+ } /* If no match. */
break;
- } /* forever looking for a match */
+ } /* Forever looking for a match. */
the_insn.opcode = opcode;
return special_case;
{
char *toP = frag_more (4);
- /* put out the opcode */
+ /* Put out the opcode. */
if (INSN_BIG_ENDIAN)
number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
else
number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
- /* put out the symbol-dependent stuff */
+ /* Put out the symbol-dependent stuff. */
if (the_insn->reloc != BFD_RELOC_NONE)
{
- fixS *fixP = fix_new_exp (frag_now, /* which frag */
- (toP - frag_now->fr_literal), /* where */
- 4, /* size */
+ fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
+ (toP - frag_now->fr_literal), /* Where. */
+ 4, /* Size. */
&the_insn->exp,
the_insn->pcrel,
the_insn->reloc);
last_opcode = the_insn->opcode;
}
\f
-/*
- This is identical to the md_atof in m68k.c. I think this is right,
- but I'm not sure.
+/* This is identical to the md_atof in m68k.c. I think this is right,
+ but I'm not sure.
- Turn a string in input_line_pointer into a floating point constant of type
- type, and store the appropriate bytes in *litP. The number of LITTLENUMS
- emitted is stored in *sizeP . An error message is returned, or NULL on OK.
- */
+ Turn a string in input_line_pointer into a floating point constant
+ of type TYPE, and store the appropriate bytes in *LITP. The number
+ of LITTLENUMS emitted is stored in *SIZEP. An error message is
+ returned, or NULL on OK. */
-/* Equal to MAX_PRECISION in atof-ieee.c */
+/* Equal to MAX_PRECISION in atof-ieee.c. */
#define MAX_LITTLENUMS 6
char *
char *litP;
int *sizeP;
{
- int i,prec;
+ int i, prec;
LITTLENUM_TYPE words[MAX_LITTLENUMS];
char *t;
litP += sizeof (LITTLENUM_TYPE);
}
}
-
+
return 0;
}
number_to_chars_bigendian (buf, val, n);
else if (target_little_endian_data
&& ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
- /* Output debug words, which are not in allocated sections, as big endian */
+ /* Output debug words, which are not in allocated sections, as big
+ endian. */
number_to_chars_bigendian (buf, val, n);
else if (target_little_endian_data || ! target_big_endian)
number_to_chars_littleendian (buf, val, n);
assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
- fixP->fx_addnumber = val; /* Remember value for emit_reloc */
+ fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
#ifdef OBJ_ELF
/* FIXME: SPARC ELF relocations don't use an addend in the data
{
md_number_to_chars (buf, val, 8);
}
- else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+ else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
{
fixP->fx_done = 0;
insn = bfd_getb32 ((unsigned char *) buf);
else
insn = bfd_getl32 ((unsigned char *) buf);
-
+
switch (fixP->fx_r_type)
{
case BFD_RELOC_32_PCREL_S2:
insn |= val & 0x3fffffff;
- /* See if we have a delay slot */
+ /* See if we have a delay slot. */
if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
{
#define G0 0
delay = bfd_getb32 ((unsigned char *) buf + 4);
else
delay = bfd_getl32 ((unsigned char *) buf + 4);
- if ((insn & OP(~0)) != OP(1) || (delay & OP(~0)) != OP(2))
+ if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
break;
- if ((delay & OP3(~0)) != OP3(0x3d) /* restore */
- && ((delay & OP3(0x28)) != 0 /* arithmetic */
- || ((delay & RD(~0)) != RD(O7))))
+ if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
+ && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
+ || ((delay & RD (~0)) != RD (O7))))
break;
- if ((delay & RS1(~0)) == RS1(O7)
- || ((delay & F3I(~0)) == 0
- && (delay & RS2(~0)) == RS2(O7)))
+ if ((delay & RS1 (~0)) == RS1 (O7)
+ || ((delay & F3I (~0)) == 0
+ && (delay & RS2 (~0)) == RS2 (O7)))
break;
/* Ensure the branch will fit into simm22. */
if ((val & 0x3fe00000)
|| (val & 0x3c0000) == 0x3c0000)
&& (sparc_arch_size == 64
|| current_architecture >= SPARC_OPCODE_ARCH_V9))
- /* ba,pt %xcc */
+ /* ba,pt %xcc */
insn = INSN_BPA | (val & 0x7ffff);
else
- /* ba */
+ /* ba */
insn = INSN_BA | (val & 0x3fffff);
if (fixP->fx_where >= 4
- && ((delay & (0xffffffff ^ RS1(~0)))
- == (INSN_OR | RD(O7) | RS2(G0))))
+ && ((delay & (0xffffffff ^ RS1 (~0)))
+ == (INSN_OR | RD (O7) | RS2 (G0))))
{
long setter;
int reg;
setter = bfd_getb32 ((unsigned char *) buf - 4);
else
setter = bfd_getl32 ((unsigned char *) buf - 4);
- if ((setter & (0xffffffff ^ RD(~0)))
- != (INSN_OR | RS1(O7) | RS2(G0)))
+ if ((setter & (0xffffffff ^ RD (~0)))
+ != (INSN_OR | RS1 (O7) | RS2 (G0)))
break;
/* The sequence was
or %o7, %g0, %rN
If call foo was replaced with ba, replace
or %rN, %g0, %o7 with nop. */
- reg = (delay & RS1(~0)) >> 14;
- if (reg != ((setter & RD(~0)) >> 25)
+ reg = (delay & RS1 (~0)) >> 14;
+ if (reg != ((setter & RD (~0)) >> 25)
|| reg == G0 || reg == O7)
break;
break;
case BFD_RELOC_SPARC_WDISP16:
- /* FIXME: simplify */
+ /* FIXME: simplify. */
if (((val > 0) && (val & ~0x3fffc))
|| ((val < 0) && (~(val - 1) & ~0x3fffc)))
as_bad_where (fixP->fx_file, fixP->fx_line,
break;
case BFD_RELOC_SPARC_WDISP19:
- /* FIXME: simplify */
+ /* FIXME: simplify. */
if (((val > 0) && (val & ~0x1ffffc))
|| ((val < 0) && (~(val - 1) & ~0x1ffffc)))
as_bad_where (fixP->fx_file, fixP->fx_line,
case BFD_RELOC_SPARC_HH22:
val = BSR (val, 32);
- /* intentional fallthrough */
+ /* Fall through. */
case BFD_RELOC_SPARC_LM22:
case BFD_RELOC_HI22:
case BFD_RELOC_SPARC_HM10:
val = BSR (val, 32);
- /* intentional fallthrough */
+ /* Fall through. */
case BFD_RELOC_LO10:
if (!fixP->fx_addsy)
case BFD_RELOC_SPARC_OLO10:
val &= 0x3ff;
val += fixP->tc_fix_data;
- /* intentional fallthrough */
+ /* Fall through. */
case BFD_RELOC_SPARC13:
if (! in_signed_range (val, 0x1fff))
case BFD_RELOC_SPARC_WDISP22:
val = (val >> 2) + 1;
- /* FALLTHROUGH */
+ /* Fall through. */
case BFD_RELOC_SPARC_BASE22:
insn |= val & 0x3fffff;
break;
/* Translate internal representation of relocation info to BFD target
format. */
+
arelent **
tc_gen_reloc (section, fixp)
asection *section;
break;
}
}
-#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
+#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
if (code == BFD_RELOC_SPARC_OLO10)
reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
else
reloc->addend = fixp->fx_offset - reloc->address;
-#else /* elf or coff */
+#else /* elf or coff */
if (reloc->howto->pc_relative == 0
|| code == BFD_RELOC_SPARC_PC10
return relocs;
}
\f
-/* We have no need to default values of symbols. */
+/* We have no need to default values of symbols. */
-/* ARGSUSED */
symbolS *
md_undefined_symbol (name)
char *name;
{
return 0;
-} /* md_undefined_symbol() */
+}
+
+/* Round up a section size to the appropriate boundary. */
-/* Round up a section size to the appropriate boundary. */
valueT
md_section_align (segment, size)
segT segment;
valueT align = ((valueT) 1
<< (valueT) bfd_get_section_alignment (stdoutput, segment));
valueT newsize;
- /* turn alignment value into a mask */
+
+ /* Turn alignment value into a mask. */
align--;
newsize = (size + align) & ~align;
return newsize;
/* Exactly what point is a PC-relative offset relative TO?
On the sparc, they're relative to the address of the offset, plus
its size. This gets us to the following instruction.
- (??? Is this right? FIXME-SOON) */
-long
+ (??? Is this right? FIXME-SOON) */
+long
md_pcrel_from (fixP)
fixS *fixP;
{
return (value == 1) ? shift : -1;
}
-/*
- * sort of like s_lcomm
- */
+/* Sort of like s_lcomm. */
#ifndef OBJ_ELF
static int max_alignment = 15;
as_bad (_("BSS length (%d.) <0! Ignored."), size);
ignore_rest_of_line ();
return;
- } /* bad length */
+ } /* Bad length. */
*p = 0;
symbolP = symbol_find_or_make (name);
segT current_seg = now_seg;
subsegT current_subseg = now_subseg;
- subseg_set (bss_section, 1); /* switch to bss */
+ /* Switch to bss. */
+ subseg_set (bss_section, 1);
if (align)
- frag_align (align, 0, 0); /* do alignment */
+ /* Do alignment. */
+ frag_align (align, 0, 0);
- /* detach from old frag */
+ /* Detach from old frag. */
if (S_GET_SEGMENT(symbolP) == bss_section)
symbol_get_frag (symbolP)->fr_symbol = NULL;
symbol_set_frag (symbolP, frag_now);
- pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, symbolP,
- (offsetT) size, (char *)0);
+ pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
+ (offsetT) size, (char *) 0);
*pfrag = 0;
S_SET_SEGMENT (symbolP, bss_section);
{
as_warn("Ignoring attempt to re-define symbol %s",
S_GET_NAME (symbolP));
- } /* if not redefining */
+ } /* if not redefining. */
demand_empty_rest_of_line ();
}
name = input_line_pointer;
c = get_symbol_end ();
- /* just after name is now '\0' */
+ /* Just after name is now '\0'. */
p = input_line_pointer;
*p = c;
SKIP_WHITESPACE ();
ignore_rest_of_line ();
return;
}
- input_line_pointer++; /* skip ',' */
+
+ /* Skip ','. */
+ input_line_pointer++;
+
if ((temp = get_absolute_expression ()) < 0)
{
as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
subseg_set (old_sec, old_subsec);
}
else
-#endif /* OBJ_ELF */
+#endif /* OBJ_ELF */
{
allocate_common:
S_SET_VALUE (symbolP, (valueT) size);
input_line_pointer += 5;
/* We only support 2 segments -- text and data -- for now, so
things in the "bss segment" will have to go into data for now.
- You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
- subseg_set (data_section, 255); /* FIXME-SOMEDAY */
+ You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
+ subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
return;
}
as_bad (_("Unknown segment type"));
/* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
global register.
The syntax is:
-
+
.register %g[2367],{#scratch|symbolname|#ignore}
- */
+*/
static void
s_register (ignore)
}
if (sparc_arch_size == 64)
{
- if (globals [reg])
+ if (globals[reg])
{
- if ((regname && globals [reg] != (symbolS *)1
- && strcmp (S_GET_NAME (globals [reg]), regname))
- || ((regname != NULL) ^ (globals [reg] != (symbolS *)1)))
+ if ((regname && globals[reg] != (symbolS *) 1
+ && strcmp (S_GET_NAME (globals[reg]), regname))
+ || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
as_bad (_("redefinition of global register"));
}
else
{
if (regname == NULL)
- globals [reg] = (symbolS *)1;
+ globals[reg] = (symbolS *) 1;
else
{
if (*regname)
as_bad (_("Register symbol %s already defined."),
regname);
}
- globals [reg] = symbol_make (regname);
- flags = symbol_get_bfdsym (globals [reg])->flags;
+ globals[reg] = symbol_make (regname);
+ flags = symbol_get_bfdsym (globals[reg])->flags;
if (! *regname)
flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
flags |= BSF_GLOBAL;
- symbol_get_bfdsym (globals [reg])->flags = flags;
- S_SET_VALUE (globals [reg], (valueT)reg);
- S_SET_ALIGN (globals [reg], reg);
- S_SET_SIZE (globals [reg], 0);
+ symbol_get_bfdsym (globals[reg])->flags = flags;
+ S_SET_VALUE (globals[reg], (valueT) reg);
+ S_SET_ALIGN (globals[reg], reg);
+ S_SET_SIZE (globals[reg], 0);
/* Although we actually want undefined_section here,
we have to use absolute_section, because otherwise
generic as code will make it a COM section.
We fix this up in sparc_adjust_symtab. */
- S_SET_SEGMENT (globals [reg], absolute_section);
- S_SET_OTHER (globals [reg], 0);
- elf_symbol (symbol_get_bfdsym (globals [reg]))
+ S_SET_SEGMENT (globals[reg], absolute_section);
+ S_SET_OTHER (globals[reg], 0);
+ elf_symbol (symbol_get_bfdsym (globals[reg]))
->internal_elf_sym.st_info =
ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
- elf_symbol (symbol_get_bfdsym (globals [reg]))
+ elf_symbol (symbol_get_bfdsym (globals[reg]))
->internal_elf_sym.st_shndx = SHN_UNDEF;
}
}
/* Adjust the symbol table. We set undefined sections for STT_REGISTER
symbols which need it. */
-
+
void
sparc_adjust_symtab ()
{
symbolS *sym;
-
+
for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
{
if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024)
{
int count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
-
+
if (count >= 4
&& !(count & 3)
&& count <= 1024
- && !((long)(fragp->fr_literal + fragp->fr_fix) & 3))
- {
- unsigned *p = (unsigned *)(fragp->fr_literal + fragp->fr_fix);
- int i;
-
- for (i = 0; i < count; i += 4, p++)
- if (INSN_BIG_ENDIAN)
- number_to_chars_bigendian ((char *)p, 0x01000000, 4); /* emit nops */
- else
- number_to_chars_littleendian ((char *)p, 0x10000000, 4);
-
- if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
- {
+ && !((long) (fragp->fr_literal + fragp->fr_fix) & 3))
+ {
+ unsigned *p = (unsigned *) (fragp->fr_literal + fragp->fr_fix);
+ int i;
+
+ for (i = 0; i < count; i += 4, p++)
+ if (INSN_BIG_ENDIAN)
+ /* Emit nops. */
+ number_to_chars_bigendian ((char *) p, 0x01000000, 4);
+ else
+ number_to_chars_littleendian ((char *) p, 0x10000000, 4);
+
+ if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
+ {
char *waddr = &fragp->fr_literal[fragp->fr_fix];
- unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
+ unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
if (INSN_BIG_ENDIAN)
number_to_chars_bigendian (waddr, wval, 4);
else
number_to_chars_littleendian (waddr, wval, 4);
- }
- fragp->fr_var = count;
- }
+ }
+ fragp->fr_var = count;
+ }
}
}
(nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
if (target_little_endian_data && nbytes == 4
- && now_seg->flags & SEC_ALLOC)
+ && now_seg->flags & SEC_ALLOC)
r = BFD_RELOC_SPARC_REV32;
fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
}
#ifdef OBJ_ELF
int
elf32_sparc_force_relocation (fixp)
- struct fix *fixp;
+ struct fix *fixp;
{
if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
return 1;
-
+
return 0;
}
#endif
-
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
-/*
- Written By Steve Chamberlain
- sac@cygnus.com
- */
+/* Written By Steve Chamberlain <sac@cygnus.com>. */
+
#define DEFINE_TABLE
#include <stdio.h>
int segmented_mode;
const int md_reloc_size;
-/* This table describes all the machine specific pseudo-ops the assembler
- has to support. The fields are:
- pseudo-op name without dot
- function to call to execute this pseudo-op
- Integer arg to pass to the function
- */
-
void cons ();
void
coff_flags = F_Z8002;
}
-static
-void
+static void
even ()
{
frag_align (1, 0, 0);
void
sval ()
{
-
SKIP_WHITESPACE ();
if (*input_line_pointer == '\'')
{
}
demand_empty_rest_of_line ();
}
-
}
-const pseudo_typeS md_pseudo_table[] =
-{
- {"int", cons, 2},
- {"data.b", cons, 1},
- {"data.w", cons, 2},
- {"data.l", cons, 4},
- {"form", listing_psize, 0},
- {"heading", listing_title, 0},
- {"import", s_ignore, 0},
- {"page", listing_eject, 0},
- {"program", s_ignore, 0},
- {"z8001", s_segm, 0},
- {"z8002", s_unseg, 0},
-
-
- {"segm", s_segm, 0},
- {"unsegm", s_unseg, 0},
- {"unseg", s_unseg, 0},
- {"name", s_app_file, 0},
- {"global", s_globl, 0},
- {"wval", cons, 2},
- {"lval", cons, 4},
- {"bval", cons, 1},
- {"sval", sval, 0},
- {"rsect", obj_coff_section, 0},
- {"sect", obj_coff_section, 0},
- {"block", s_space, 0},
- {"even", even, 0},
- {0, 0, 0}
+
+/* This table describes all the machine specific pseudo-ops the assembler
+ has to support. The fields are:
+ pseudo-op name without dot
+ function to call to execute this pseudo-op
+ Integer arg to pass to the function
+ */
+
+const pseudo_typeS md_pseudo_table[] = {
+ {"int" , cons , 2},
+ {"data.b" , cons , 1},
+ {"data.w" , cons , 2},
+ {"data.l" , cons , 4},
+ {"form" , listing_psize , 0},
+ {"heading", listing_title , 0},
+ {"import" , s_ignore , 0},
+ {"page" , listing_eject , 0},
+ {"program", s_ignore , 0},
+ {"z8001" , s_segm , 0},
+ {"z8002" , s_unseg , 0},
+
+ {"segm" , s_segm , 0},
+ {"unsegm" , s_unseg , 0},
+ {"unseg" , s_unseg , 0},
+ {"name" , s_app_file , 0},
+ {"global" , s_globl , 0},
+ {"wval" , cons , 2},
+ {"lval" , cons , 4},
+ {"bval" , cons , 1},
+ {"sval" , sval , 0},
+ {"rsect" , obj_coff_section, 0},
+ {"sect" , obj_coff_section, 0},
+ {"block" , s_space , 0},
+ {"even" , even , 0},
+ {0 , 0 , 0}
};
const char EXP_CHARS[] = "eE";
-/* Chars that mean this number is a floating point constant */
-/* As in 0f12.456 */
-/* or 0d1.2345e12 */
+/* Chars that mean this number is a floating point constant.
+ As in 0f12.456
+ or 0d1.2345e12 */
const char FLT_CHARS[] = "rRsSfFdDxXpP";
-static struct hash_control *opcode_hash_control; /* Opcode mnemonics */
+/* Opcode mnemonics. */
+static struct hash_control *opcode_hash_control;
void
md_begin ()
for (opcode = z8k_table; opcode->name; opcode++)
{
- /* Only enter unique codes into the table */
+ /* Only enter unique codes into the table. */
char *src = opcode->name;
if (strcmp (opcode->name, prev_name))
prev_name = opcode->name;
}
- /* default to z8002 */
+ /* Default to z8002. */
s_unseg ();
- /* insert the pseudo ops too */
+ /* Insert the pseudo ops, too. */
for (idx = 0; md_pseudo_table[idx].poc_name; idx++)
{
opcode_entry_type *fake_opcode;
char *e_end;
expressionS e_exp;
};
+
typedef struct z8k_op
{
- char regsize; /* 'b','w','r','q' */
- unsigned int reg; /* 0..15 */
+ /* 'b','w','r','q'. */
+ char regsize;
+
+ /* 0 .. 15. */
+ unsigned int reg;
int mode;
- unsigned int x_reg; /* any other register associated with the mode */
- expressionS exp; /* any expression */
+ /* Any other register associated with the mode. */
+ unsigned int x_reg;
+
+ /* Any expression. */
+ expressionS exp;
}
op_type;
}
}
-/*
- parse operands
-
- rh0-rh7, rl0-rl7
- r0-r15
- rr0-rr14
- rq0--rq12
- WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp
- r0l,r0h,..r7l,r7h
- @WREG
- @WREG+
- @-WREG
- #const
+/* Parse operands
- */
+ rh0-rh7, rl0-rl7
+ r0-r15
+ rr0-rr14
+ rq0--rq12
+ WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp
+ r0l,r0h,..r7l,r7h
+ @WREG
+ @WREG+
+ @-WREG
+ #const
+*/
/* Try to parse a reg name. Return a pointer to the first character
in SRC after the reg name. */
if (src[0] == 's' && src[1] == 'p')
{
if (segmented_mode)
- {
- *mode = CLASS_REG_LONG;
- *reg = 14;
- }
+ {
+ *mode = CLASS_REG_LONG;
+ *reg = 14;
+ }
else
- {
- *mode = CLASS_REG_WORD;
- *reg = 15;
- }
+ {
+ *mode = CLASS_REG_WORD;
+ *reg = 15;
+ }
return src + 2;
}
if (src[0] == 'r')
{
if (src[1] == 'r')
- {
- *mode = CLASS_REG_LONG;
- res = whatreg (reg, src + 2);
+ {
+ *mode = CLASS_REG_LONG;
+ res = whatreg (reg, src + 2);
regno = *reg;
if (regno > 14)
- as_warn (_("register rr%d, out of range."),regno);
- }
+ as_warn (_("register rr%d, out of range."), regno);
+ }
else if (src[1] == 'h')
- {
- *mode = CLASS_REG_BYTE;
- res = whatreg (reg, src + 2);
+ {
+ *mode = CLASS_REG_BYTE;
+ res = whatreg (reg, src + 2);
regno = *reg;
if (regno > 7)
- as_warn (_("register rh%d, out of range."),regno);
- }
+ as_warn (_("register rh%d, out of range."), regno);
+ }
else if (src[1] == 'l')
- {
- *mode = CLASS_REG_BYTE;
- res = whatreg (reg, src + 2);
+ {
+ *mode = CLASS_REG_BYTE;
+ res = whatreg (reg, src + 2);
regno = *reg;
if (regno > 7)
- as_warn (_("register rl%d, out of range."),regno);
- *reg += 8;
- }
+ as_warn (_("register rl%d, out of range."), regno);
+ *reg += 8;
+ }
else if (src[1] == 'q')
- {
- *mode = CLASS_REG_QUAD;
- res = whatreg (reg, src + 2);
+ {
+ *mode = CLASS_REG_QUAD;
+ res = whatreg (reg, src + 2);
regno = *reg;
if (regno > 12)
- as_warn (_("register rq%d, out of range."),regno);
- }
+ as_warn (_("register rq%d, out of range."), regno);
+ }
else
- {
- *mode = CLASS_REG_WORD;
- res = whatreg (reg, src + 1);
+ {
+ *mode = CLASS_REG_WORD;
+ res = whatreg (reg, src + 1);
regno = *reg;
if (regno > 15)
- as_warn (_("register r%d, out of range."),regno);
- }
+ as_warn (_("register r%d, out of range."), regno);
+ }
}
return res;
-
}
char *
exp(r)
r(#exp)
r(r)
-
-
-
*/
-static
-char *
+static char *
checkfor (ptr, what)
char *ptr;
char what;
if (*ptr == what)
ptr++;
else
- {
- as_bad (_("expected %c"), what);
- }
+ as_bad (_("expected %c"), what);
+
return ptr;
}
-/* Make sure the mode supplied is the size of a word */
+/* Make sure the mode supplied is the size of a word. */
+
static void
regword (mode, string)
int mode;
}
}
-/* Make sure the mode supplied is the size of an address */
+/* Make sure the mode supplied is the size of an address. */
+
static void
regaddr (mode, string)
int mode;
struct ctrl_names
{
- int value;
- char *name;
+ int value;
+ char *name;
};
-struct ctrl_names ctrl_table[] =
-{
- 0x2, "fcw",
- 0X3, "refresh",
- 0x4, "psapseg",
- 0x5, "psapoff",
- 0x5, "psap",
- 0x6, "nspseg",
- 0x7, "nspoff",
- 0x7, "nsp",
- 0, 0
+struct ctrl_names ctrl_table[] = {
+ 0x2, "fcw",
+ 0X3, "refresh",
+ 0x4, "psapseg",
+ 0x5, "psapoff",
+ 0x5, "psap",
+ 0x6, "nspseg",
+ 0x7, "nspoff",
+ 0x7, "nsp",
+ 0 , 0
};
-
+
static void
get_ctrl_operand (ptr, mode, dst)
char **ptr;
int j;
for (j = 0; ctrl_table[i].name[j]; j++)
- {
- if (ctrl_table[i].name[j] != src[j])
- goto fail;
- }
+ {
+ if (ctrl_table[i].name[j] != src[j])
+ goto fail;
+ }
the_ctrl = ctrl_table[i].value;
*ptr = src + j;
return;
- fail:;
+ fail:
+ ;
}
the_ctrl = 0;
return;
};
-struct flag_names flag_table[] =
-{
+struct flag_names flag_table[] = {
0x1, "p",
0x1, "v",
0x2, "s",
the_flags = 0;
for (j = 0; j <= 9; j++)
{
- if (!src[j])
+ if (!src[j])
goto done;
- for (i = 0; flag_table[i].name; i++)
- {
- if (flag_table[i].name[0] == src[j])
- {
- the_flags = the_flags | flag_table[i].value;
- goto match;
- }
- }
+ for (i = 0; flag_table[i].name; i++)
+ {
+ if (flag_table[i].name[0] == src[j])
+ {
+ the_flags = the_flags | flag_table[i].value;
+ goto match;
+ }
+ }
goto done;
match:
- ;
+ ;
}
- done:
+ done:
*ptr = src + j;
return;
}
-
struct interrupt_names
{
int value;
int j;
for (j = 0; intr_table[i].name[j]; j++)
- {
- if (intr_table[i].name[j] != src[j])
- goto fail;
- }
+ {
+ if (intr_table[i].name[j] != src[j])
+ goto fail;
+ }
the_interrupt = intr_table[i].value;
*ptr = src + j;
return;
- fail:;
+ fail:
+ ;
}
the_interrupt = 0x0;
return;
};
-struct cc_names table[] =
-{
+struct cc_names table[] = {
0x0, "f",
0x1, "lt",
0x2, "le",
0xe, "nz",
0xf, "nc",
0xf, "uge",
- 0, 0
+ 0 , 0
};
static void
the_cc = table[i].value;
*ptr = src + j;
return;
- fail:;
+ fail:
+ ;
}
the_cc = 0x8;
}
end = parse_reg (src, &nw, &nr);
if (end)
{
- /* Got Ra(Rb) */
+ /* Got Ra(Rb). */
src = end;
if (*src != ')')
- {
- as_bad (_("Missing ) in ra(rb)"));
- }
+ as_bad (_("Missing ) in ra(rb)"));
else
- {
- src++;
- }
+ src++;
regaddr (mode->mode, "ra(rb) ra");
-/* regword (mode->mode, "ra(rb) rb");*/
+#if 0
+ regword (mode->mode, "ra(rb) rb");
+#endif
mode->mode = CLASS_BX;
mode->reg = regn;
mode->x_reg = nr;
}
else
{
- /* Got Ra(disp) */
+ /* Got Ra(disp). */
if (*src == '#')
src++;
src = parse_exp (src, &(mode->exp));
}
else
{
- /* No initial reg */
+ /* No initial reg. */
src = parse_exp (src, &(mode->exp));
if (*src == '(')
{
}
else
{
- /* Just an address */
+ /* Just an address. */
mode->mode = CLASS_DA;
mode->reg = 0;
mode->x_reg = 0;
*ptr = src;
}
-static
-char *
+static char *
get_operands (opcode, op_end, operand)
opcode_entry_type *opcode;
char *op_end;
op_type *operand;
{
char *ptr = op_end;
-char *savptr;
+ char *savptr;
+
switch (opcode->noperands)
{
case 0:
case 1:
ptr++;
if (opcode->arg_info[0] == CLASS_CC)
- {
- get_cc_operand (&ptr, operand + 0, 0);
- }
+ {
+ get_cc_operand (&ptr, operand + 0, 0);
+ }
else if (opcode->arg_info[0] == CLASS_FLAGS)
- {
- get_flags_operand (&ptr, operand + 0, 0);
- }
- else if (opcode->arg_info[0] == (CLASS_IMM +(ARG_IMM2)))
- {
- get_interrupt_operand (&ptr, operand + 0, 0);
- }
+ {
+ get_flags_operand (&ptr, operand + 0, 0);
+ }
+ else if (opcode->arg_info[0] == (CLASS_IMM + (ARG_IMM2)))
+ {
+ get_interrupt_operand (&ptr, operand + 0, 0);
+ }
else
- {
- get_operand (&ptr, operand + 0, 0);
- }
+ {
+ get_operand (&ptr, operand + 0, 0);
+ }
operand[1].mode = 0;
break;
ptr++;
savptr = ptr;
if (opcode->arg_info[0] == CLASS_CC)
- {
- get_cc_operand (&ptr, operand + 0, 0);
- }
+ {
+ get_cc_operand (&ptr, operand + 0, 0);
+ }
else if (opcode->arg_info[0] == CLASS_CTRL)
- {
- get_ctrl_operand (&ptr, operand + 0, 0);
- if (the_ctrl == 0)
- {
- ptr = savptr;
- get_operand (&ptr, operand + 0, 0);
- if (ptr == 0)
- return;
- if (*ptr == ',')
- ptr++;
- get_ctrl_operand (&ptr, operand + 1, 1);
- return ptr;
- }
- }
+ {
+ get_ctrl_operand (&ptr, operand + 0, 0);
+ if (the_ctrl == 0)
+ {
+ ptr = savptr;
+ get_operand (&ptr, operand + 0, 0);
+ if (ptr == 0)
+ return;
+ if (*ptr == ',')
+ ptr++;
+ get_ctrl_operand (&ptr, operand + 1, 1);
+ return ptr;
+ }
+ }
else
- {
- get_operand (&ptr, operand + 0, 0);
- }
+ {
+ get_operand (&ptr, operand + 0, 0);
+ }
if (ptr == 0)
- return;
+ return;
if (*ptr == ',')
- ptr++;
+ ptr++;
get_operand (&ptr, operand + 1, 1);
break;
ptr++;
get_cc_operand (&ptr, operand + 3, 3);
break;
+
default:
abort ();
}
}
/* Passed a pointer to a list of opcodes which use different
- addressing modes, return the opcode which matches the opcodes
- provided
- */
+ addressing modes. Return the opcode which matches the opcodes
+ provided. */
-static
-opcode_entry_type *
+static opcode_entry_type *
get_specific (opcode, operands)
opcode_entry_type *opcode;
op_type *operands;
if ((mode & CLASS_MASK) != (this_try->arg_info[i] & CLASS_MASK))
{
- /* it could be an pc rel operand, if this is a da mode and
- we like disps, then insert it */
+ /* It could be an pc rel operand, if this is a da mode
+ and we like disps, then insert it. */
if (mode == CLASS_DA && this_try->arg_info[i] == CLASS_DISP)
{
- /* This is the case */
+ /* This is the case. */
operands[i].mode = CLASS_DISP;
}
else if (mode == CLASS_BA && this_try->arg_info[i])
{
- /* Can't think of a way to turn what we've been given into
- something that's ok */
+ /* Can't think of a way to turn what we've been
+ given into something that's OK. */
goto fail;
}
else if (this_try->arg_info[i] & CLASS_PR)
{
if (mode == CLASS_REG_LONG && segmented_mode)
{
- /* ok */
+ /* OK. */
}
else if (mode == CLASS_REG_WORD && !segmented_mode)
{
- /* ok */
+ /* OK. */
}
else
goto fail;
}
found = 1;
- fail:;
+ fail:
+ ;
}
if (found)
return this_try;
&& operand->exp.X_op_symbol == 0)
{
- /* No symbol involved, let's look at offset, it's dangerous if any of
- the high bits are not 0 or ff's, find out by oring or anding with
- the width and seeing if the answer is 0 or all fs*/
+ /* No symbol involved, let's look at offset, it's dangerous if
+ any of the high bits are not 0 or ff's, find out by oring or
+ anding with the width and seeing if the answer is 0 or all
+ fs. */
if ((operand->exp.X_add_number & ~width) != 0 &&
(operand->exp.X_add_number | width) != (~0))
{
- as_warn (_("operand %s0x%x out of range."), string, operand->exp.X_add_number);
+ as_warn (_("operand %s0x%x out of range."),
+ string, operand->exp.X_add_number);
}
}
#if 1
switch (size)
{
- case 8: /* 8 nibbles == 32 bits */
+ case 8: /* 8 nibbles == 32 bits */
*ptr++ = n >> 28;
*ptr++ = n >> 24;
*ptr++ = n >> 20;
*ptr++ = n >> 16;
- case 4: /* 4 niblles == 16 bits */
+ case 4: /* 4 niblles == 16 bits */
*ptr++ = n >> 12;
*ptr++ = n >> 8;
case 2:
}
-/* Now we know what sort of opcodes it is, lets build the bytes -
- */
+/* Now we know what sort of opcodes it is. Let's build the bytes. */
+
#define INSERT(x,y) *x++ = y>>24; *x++ = y>> 16; *x++=y>>8; *x++ =y;
static void
build_bytes (this_try, operand)
- opcode_entry_type * this_try;
+ opcode_entry_type *this_try;
struct z8k_op *operand;
{
unsigned int i;
memset (buffer, 20, 0);
class_ptr = this_try->byte_info;
-top:;
+ top:
for (nibble = 0; c = *class_ptr++; nibble++)
{
switch (c & CLASS_MASK)
{
default:
-
abort ();
+
case CLASS_ADDRESS:
- /* Direct address, we don't cope with the SS mode right now */
+ /* Direct address, we don't cope with the SS mode right now. */
if (segmented_mode)
{
da_operand->X_add_number |= 0x80000000;
da_operand = 0;
break;
case CLASS_DISP8:
- /* pc rel 8 bit */
+ /* pc rel 8 bit */
output_ptr = apply_fix (output_ptr, R_JR, da_operand, 2);
da_operand = 0;
break;
case CLASS_0DISP7:
- /* pc rel 7 bit */
+ /* pc rel 7 bit */
*output_ptr = 0;
output_ptr = apply_fix (output_ptr, R_DISP7, da_operand, 2);
da_operand = 0;
break;
case CLASS_1DISP7:
- /* pc rel 7 bit */
+ /* pc rel 7 bit */
*output_ptr = 0x80;
output_ptr = apply_fix (output_ptr, R_DISP7, da_operand, 2);
- output_ptr[-2] = 0x8;
+ output_ptr[-2] = 0x8;
da_operand = 0;
break;
if (imm_operand)
{
if (imm_operand->X_add_number == 2)
- {
- *output_ptr |= 2;
- }
+ *output_ptr |= 2;
else if (imm_operand->X_add_number != 1)
- {
- as_bad (_("immediate must be 1 or 2"));
- }
+ as_bad (_("immediate must be 1 or 2"));
}
else
- {
- as_bad (_("immediate 1 or 2 expected"));
- }
+ as_bad (_("immediate 1 or 2 expected"));
output_ptr++;
break;
case CLASS_CC:
*output_ptr++ = the_cc;
break;
- case CLASS_0CCC:
- *output_ptr++ = the_ctrl;
- break;
- case CLASS_1CCC:
- *output_ptr++ = the_ctrl | 0x8;
- break;
- case CLASS_00II:
- *output_ptr++ = (~the_interrupt & 0x3);
- break;
- case CLASS_01II:
- *output_ptr++ = (~the_interrupt & 0x3) | 0x4;
- break;
- case CLASS_FLAGS:
- *output_ptr++ = the_flags;
- break;
+ case CLASS_0CCC:
+ *output_ptr++ = the_ctrl;
+ break;
+ case CLASS_1CCC:
+ *output_ptr++ = the_ctrl | 0x8;
+ break;
+ case CLASS_00II:
+ *output_ptr++ = (~the_interrupt & 0x3);
+ break;
+ case CLASS_01II:
+ *output_ptr++ = (~the_interrupt & 0x3) | 0x4;
+ break;
+ case CLASS_FLAGS:
+ *output_ptr++ = the_flags;
+ break;
case CLASS_BIT:
*output_ptr++ = c & 0xf;
break;
case CLASS_REGN0:
if (reg[c & 0xf] == 0)
- {
- as_bad (_("can't use R0 here"));
- }
+ as_bad (_("can't use R0 here"));
+ /* Fall through. */
case CLASS_REG:
case CLASS_REG_BYTE:
case CLASS_REG_WORD:
case CLASS_REG_LONG:
case CLASS_REG_QUAD:
- /* Insert bit mattern of
- right reg */
+ /* Insert bit mattern of right reg. */
*output_ptr++ = reg[c & 0xf];
break;
case CLASS_DISP:
}
}
- /* Copy from the nibble buffer into the frag */
-
+ /* Copy from the nibble buffer into the frag. */
{
int length = (output_ptr - buffer) / 2;
char *src = buffer;
src += 2;
fragp++;
}
-
}
-
}
/* This is the guts of the machine-dependent assembler. STR points to a
char *dot = 0;
char c;
- /* Drop leading whitespace */
+ /* Drop leading whitespace. */
while (*str == ' ')
str++;
- /* find the op code end */
+ /* Find the op code end. */
for (op_start = op_end = str;
*op_end != 0 && *op_end != ' ';
op_end++)
- {
- }
-
- ;
+ ;
if (op_end == op_start)
{
*op_end = 0;
- opcode = (opcode_entry_type *) hash_find (opcode_hash_control,
- op_start);
-
+ opcode = (opcode_entry_type *) hash_find (opcode_hash_control, op_start);
if (opcode == NULL)
{
if (opcode->opcode == 250)
{
- /* was really a pseudo op */
+ /* Was really a pseudo op. */
pseudo_typeS *p;
char oc;
char *old = input_line_pointer;
*op_end = c;
-
input_line_pointer = op_end;
oc = *old;
}
else
{
- input_line_pointer = get_operands (opcode, op_end,
- operand);
+ input_line_pointer = get_operands (opcode, op_end, operand);
prev_opcode = opcode;
opcode = get_specific (opcode, operand);
if (opcode == 0)
{
- /* Couldn't find an opcode which matched the operands */
+ /* Couldn't find an opcode which matched the operands. */
char *where = frag_more (2);
where[0] = 0x0;
printf (_("call to tc_headers_hook \n"));
}
-/* Various routines to kill one day */
-/* Equal to MAX_PRECISION in atof-ieee.c */
+/* Various routines to kill one day. */
+/* Equal to MAX_PRECISION in atof-ieee.c. */
#define MAX_LITTLENUMS 6
-/* Turn a string in input_line_pointer into a floating point constant of type
- type, and store the appropriate bytes in *litP. The number of LITTLENUMS
- emitted is stored in *sizeP . An error message is returned, or NULL on OK.
- */
+/* Turn a string in input_line_pointer into a floating point constant
+ of type TYPE, and store the appropriate bytes in *LITP. The number
+ of LITTLENUMS emitted is stored in *SIZEP. An error message is
+ returned, or NULL on OK. */
+
char *
md_atof (type, litP, sizeP)
char type;
}
\f
CONST char *md_shortopts = "z:";
+
struct option md_longopts[] = {
{NULL, no_argument, NULL, 0}
};
-size_t md_longopts_size = sizeof(md_longopts);
+
+size_t md_longopts_size = sizeof (md_longopts);
int
md_parse_option (c, arg)
md_show_usage (stream)
FILE *stream;
{
- fprintf(stream, _("\
+ fprintf (stream, _("\
Z8K options:\n\
-z8001 generate segmented code\n\
-z8002 generate unsegmented code\n"));
segT seg;
valueT size;
{
- return ((size + (1 << section_alignment[(int) seg]) - 1) & (-1 << section_alignment[(int) seg]));
+ return ((size + (1 << section_alignment[(int) seg]) - 1)
+ & (-1 << section_alignment[(int) seg]));
}
case R_JR:
*buf++ = val;
- /* if (val != 0) abort();*/
+#if 0
+ if (val != 0)
+ abort ();
+#endif
break;
case R_DISP7:
*buf++ += val;
- /* if (val != 0) abort();*/
+#if 0
+ if (val != 0)
+ abort ();
+#endif
break;
case R_IMM8:
default:
abort ();
-
}
}
abort ();
}
-/* Put number into target byte order */
+/* Put number into target byte order. */
void
md_number_to_chars (ptr, use, nbytes)
{
number_to_chars_bigendian (ptr, use, nbytes);
}
+
long
md_pcrel_from (fixP)
fixS *fixP;
{
symbolS *symbol_ptr;
- if (fix_ptr->fx_addsy &&
- fix_ptr->fx_subsy)
+ if (fix_ptr->fx_addsy
+ && fix_ptr->fx_subsy)
{
symbolS *add = fix_ptr->fx_addsy;
symbolS *sub = fix_ptr->fx_subsy;
- if (S_GET_SEGMENT(add) != S_GET_SEGMENT(sub))
+
+ if (S_GET_SEGMENT (add) != S_GET_SEGMENT (sub))
+ as_bad (_("Can't subtract symbols in different sections %s %s"),
+ S_GET_NAME (add), S_GET_NAME (sub));
+ else
{
- as_bad(_("Can't subtract symbols in different sections %s %s"),
- S_GET_NAME(add), S_GET_NAME(sub));
+ int diff = S_GET_VALUE (add) - S_GET_VALUE (sub);
+
+ fix_ptr->fx_addsy = 0;
+ fix_ptr->fx_subsy = 0;
+ fix_ptr->fx_offset += diff;
}
- else {
- int diff = S_GET_VALUE(add) - S_GET_VALUE(sub);
- fix_ptr->fx_addsy = 0;
- fix_ptr->fx_subsy = 0;
- fix_ptr->fx_offset += diff;
- }
}
symbol_ptr = fix_ptr->fx_addsy;
/* If this relocation is attached to a symbol then it's ok
- to output it */
+ to output it. */
if (fix_ptr->fx_r_type == 0)
{
- /* cons likes to create reloc32's whatever the size of the reloc.. */
+ /* cons likes to create reloc32's whatever the size of the reloc. */
switch (fix_ptr->fx_size)
{
case 2:
default:
abort ();
}
-
}
else
- {
- intr->r_type = fix_ptr->fx_r_type;
- }
+ intr->r_type = fix_ptr->fx_r_type;
intr->r_vaddr = fix_ptr->fx_frag->fr_address + fix_ptr->fx_where + base;
intr->r_offset = fix_ptr->fx_offset;
else
intr->r_symndx = -1;
}
-
projects / external / binutils.git / commitdiff