} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
// Single-Width Floating-Point/Integer Type-Convert Instructions
+let mayRaiseFPException = true in {
+let Uses = [FRM] in {
defm VFCVT_XU_F_V : VCVTI_FV_VS2<"vfcvt.xu.f.v", 0b010010, 0b00000>;
defm VFCVT_X_F_V : VCVTI_FV_VS2<"vfcvt.x.f.v", 0b010010, 0b00001>;
+}
defm VFCVT_RTZ_XU_F_V : VCVTI_FV_VS2<"vfcvt.rtz.xu.f.v", 0b010010, 0b00110>;
defm VFCVT_RTZ_X_F_V : VCVTI_FV_VS2<"vfcvt.rtz.x.f.v", 0b010010, 0b00111>;
+let Uses = [FRM] in {
defm VFCVT_F_XU_V : VCVTF_IV_VS2<"vfcvt.f.xu.v", 0b010010, 0b00010>;
defm VFCVT_F_X_V : VCVTF_IV_VS2<"vfcvt.f.x.v", 0b010010, 0b00011>;
+}
+} // mayRaiseFPException = true
// Widening Floating-Point/Integer Type-Convert Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt in {
+let Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt,
+ mayRaiseFPException = true in {
+let Uses = [FRM] in {
defm VFWCVT_XU_F_V : VWCVTI_FV_VS2<"vfwcvt.xu.f.v", 0b010010, 0b01000>;
defm VFWCVT_X_F_V : VWCVTI_FV_VS2<"vfwcvt.x.f.v", 0b010010, 0b01001>;
+}
defm VFWCVT_RTZ_XU_F_V : VWCVTI_FV_VS2<"vfwcvt.rtz.xu.f.v", 0b010010, 0b01110>;
defm VFWCVT_RTZ_X_F_V : VWCVTI_FV_VS2<"vfwcvt.rtz.x.f.v", 0b010010, 0b01111>;
defm VFWCVT_F_XU_V : VWCVTF_IV_VS2<"vfwcvt.f.xu.v", 0b010010, 0b01010>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt
// Narrowing Floating-Point/Integer Type-Convert Instructions
-let Constraints = "@earlyclobber $vd" in {
+let Constraints = "@earlyclobber $vd", mayRaiseFPException = true in {
+let Uses = [FRM] in {
defm VFNCVT_XU_F_W : VNCVTI_FV_VS2<"vfncvt.xu.f.w", 0b010010, 0b10000>;
defm VFNCVT_X_F_W : VNCVTI_FV_VS2<"vfncvt.x.f.w", 0b010010, 0b10001>;
+}
defm VFNCVT_RTZ_XU_F_W : VNCVTI_FV_VS2<"vfncvt.rtz.xu.f.w", 0b010010, 0b10110>;
defm VFNCVT_RTZ_X_F_W : VNCVTI_FV_VS2<"vfncvt.rtz.x.f.w", 0b010010, 0b10111>;
+let Uses = [FRM] in {
defm VFNCVT_F_XU_W : VNCVTF_IV_VS2<"vfncvt.f.xu.w", 0b010010, 0b10010>;
defm VFNCVT_F_X_W : VNCVTF_IV_VS2<"vfncvt.f.x.w", 0b010010, 0b10011>;
defm VFNCVT_F_F_W : VNCVTF_FV_VS2<"vfncvt.f.f.w", 0b010010, 0b10100>;
+}
defm VFNCVT_ROD_F_F_W : VNCVTF_FV_VS2<"vfncvt.rod.f.f.w", 0b010010, 0b10101>;
-} // Constraints = "@earlyclobber $vd"
+} // Constraints = "@earlyclobber $vd", mayRaiseFPException = true
} // Predicates = HasVInstructionsAnyF]
let Predicates = [HasVInstructions] in {
//===----------------------------------------------------------------------===//
// 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions
//===----------------------------------------------------------------------===//
+let mayRaiseFPException = true in {
+let Uses = [FRM] in {
defm PseudoVFCVT_XU_F : VPseudoVCVTI_V;
defm PseudoVFCVT_X_F : VPseudoVCVTI_V;
+}
defm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V;
defm PseudoVFCVT_RTZ_X_F : VPseudoVCVTI_V;
+let Uses = [FRM] in {
defm PseudoVFCVT_F_XU : VPseudoVCVTF_V;
defm PseudoVFCVT_F_X : VPseudoVCVTF_V;
+}
+} // mayRaiseFPException = true
//===----------------------------------------------------------------------===//
// 14.18. Widening Floating-Point/Integer Type-Convert Instructions
//===----------------------------------------------------------------------===//
+let mayRaiseFPException = true in {
+let Uses = [FRM] in {
defm PseudoVFWCVT_XU_F : VPseudoVWCVTI_V;
defm PseudoVFWCVT_X_F : VPseudoVWCVTI_V;
+}
defm PseudoVFWCVT_RTZ_XU_F : VPseudoVWCVTI_V;
defm PseudoVFWCVT_RTZ_X_F : VPseudoVWCVTI_V;
defm PseudoVFWCVT_F_XU : VPseudoVWCVTF_V;
defm PseudoVFWCVT_F_X : VPseudoVWCVTF_V;
defm PseudoVFWCVT_F_F : VPseudoVWCVTD_V;
+} // mayRaiseFPException = true
//===----------------------------------------------------------------------===//
// 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
//===----------------------------------------------------------------------===//
+let mayRaiseFPException = true in {
+let Uses = [FRM] in {
defm PseudoVFNCVT_XU_F : VPseudoVNCVTI_W;
defm PseudoVFNCVT_X_F : VPseudoVNCVTI_W;
+}
defm PseudoVFNCVT_RTZ_XU_F : VPseudoVNCVTI_W;
defm PseudoVFNCVT_RTZ_X_F : VPseudoVNCVTI_W;
+let Uses = [FRM] in {
defm PseudoVFNCVT_F_XU : VPseudoVNCVTF_W;
defm PseudoVFNCVT_F_X : VPseudoVNCVTF_W;
defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W;
+}
defm PseudoVFNCVT_ROD_F_F : VPseudoVNCVTD_W;
+} // mayRaiseFPException = true
} // Predicates = [HasVInstructionsAnyF]
let Predicates = [HasVInstructions] in {
; MIR-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v9
; MIR-NEXT: [[COPY3:%[0-9]+]]:vrnov0 = COPY $v8
; MIR-NEXT: $v0 = COPY [[COPY1]]
- ; MIR-NEXT: early-clobber %4:vrnov0 = PseudoVFNCVT_RTZ_X_F_W_MF2_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 4 /* e16 */, 0
+ ; MIR-NEXT: early-clobber %4:vrnov0 = nofpexcept PseudoVFNCVT_RTZ_X_F_W_MF2_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 4 /* e16 */, 0
; MIR-NEXT: $v8 = COPY %4
; MIR-NEXT: PseudoRET implicit $v8
%splat = insertelement <8 x i1> poison, i1 -1, i32 0
; MIR-NEXT: [[COPY2:%[0-9]+]]:vrm2 = COPY $v10m2
; MIR-NEXT: [[COPY3:%[0-9]+]]:vrnov0 = COPY $v8
; MIR-NEXT: $v0 = COPY [[COPY1]]
- ; MIR-NEXT: early-clobber %4:vrnov0 = PseudoVFNCVT_F_X_W_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0
+ ; MIR-NEXT: early-clobber %4:vrnov0 = nofpexcept PseudoVFNCVT_F_X_W_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0, implicit $frm
; MIR-NEXT: $v8 = COPY %4
; MIR-NEXT: PseudoRET implicit $v8
%splat = insertelement <8 x i1> poison, i1 -1, i32 0
; MIR-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v10
; MIR-NEXT: [[COPY3:%[0-9]+]]:vrm2nov0 = COPY $v8m2
; MIR-NEXT: $v0 = COPY [[COPY1]]
- ; MIR-NEXT: early-clobber %4:vrm2nov0 = PseudoVFWCVT_F_F_V_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0
+ ; MIR-NEXT: early-clobber %4:vrm2nov0 = nofpexcept PseudoVFWCVT_F_F_V_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0
; MIR-NEXT: $v8m2 = COPY %4
; MIR-NEXT: PseudoRET implicit $v8m2
%splat = insertelement <8 x i1> poison, i1 -1, i32 0
; MIR-NEXT: [[COPY2:%[0-9]+]]:vrm2 = COPY $v10m2
; MIR-NEXT: [[COPY3:%[0-9]+]]:vrnov0 = COPY $v8
; MIR-NEXT: $v0 = COPY [[COPY1]]
- ; MIR-NEXT: early-clobber %4:vrnov0 = PseudoVFNCVT_F_F_W_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0
+ ; MIR-NEXT: early-clobber %4:vrnov0 = nofpexcept PseudoVFNCVT_F_F_W_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0, implicit $frm
; MIR-NEXT: $v8 = COPY %4
; MIR-NEXT: PseudoRET implicit $v8
%splat = insertelement <8 x i1> poison, i1 -1, i32 0
; MIR-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v9
; MIR-NEXT: [[COPY3:%[0-9]+]]:vrnov0 = COPY $v8
; MIR-NEXT: $v0 = COPY [[COPY1]]
- ; MIR-NEXT: early-clobber %4:vrnov0 = PseudoVFNCVT_RTZ_X_F_W_MF2_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 4 /* e16 */, 0
+ ; MIR-NEXT: early-clobber %4:vrnov0 = nofpexcept PseudoVFNCVT_RTZ_X_F_W_MF2_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 4 /* e16 */, 0
; MIR-NEXT: $v8 = COPY %4
; MIR-NEXT: PseudoRET implicit $v8
%splat = insertelement <vscale x 2 x i1> poison, i1 -1, i32 0
; MIR-NEXT: [[COPY2:%[0-9]+]]:vrm2 = COPY $v10m2
; MIR-NEXT: [[COPY3:%[0-9]+]]:vrnov0 = COPY $v8
; MIR-NEXT: $v0 = COPY [[COPY1]]
- ; MIR-NEXT: early-clobber %4:vrnov0 = PseudoVFNCVT_F_X_W_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0
+ ; MIR-NEXT: early-clobber %4:vrnov0 = nofpexcept PseudoVFNCVT_F_X_W_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0, implicit $frm
; MIR-NEXT: $v8 = COPY %4
; MIR-NEXT: PseudoRET implicit $v8
%splat = insertelement <vscale x 2 x i1> poison, i1 -1, i32 0
; MIR-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v10
; MIR-NEXT: [[COPY3:%[0-9]+]]:vrm2nov0 = COPY $v8m2
; MIR-NEXT: $v0 = COPY [[COPY1]]
- ; MIR-NEXT: early-clobber %4:vrm2nov0 = PseudoVFWCVT_F_F_V_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0
+ ; MIR-NEXT: early-clobber %4:vrm2nov0 = nofpexcept PseudoVFWCVT_F_F_V_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0
; MIR-NEXT: $v8m2 = COPY %4
; MIR-NEXT: PseudoRET implicit $v8m2
%splat = insertelement <vscale x 2 x i1> poison, i1 -1, i32 0
; MIR-NEXT: [[COPY2:%[0-9]+]]:vrm2 = COPY $v10m2
; MIR-NEXT: [[COPY3:%[0-9]+]]:vrnov0 = COPY $v8
; MIR-NEXT: $v0 = COPY [[COPY1]]
- ; MIR-NEXT: early-clobber %4:vrnov0 = PseudoVFNCVT_F_F_W_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0
+ ; MIR-NEXT: early-clobber %4:vrnov0 = nofpexcept PseudoVFNCVT_F_F_W_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0, implicit $frm
; MIR-NEXT: $v8 = COPY %4
; MIR-NEXT: PseudoRET implicit $v8
%splat = insertelement <vscale x 2 x i1> poison, i1 -1, i32 0
; MIR-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v9
; MIR-NEXT: [[COPY3:%[0-9]+]]:vrnov0 = COPY $v8
; MIR-NEXT: $v0 = COPY [[COPY1]]
- ; MIR-NEXT: early-clobber %4:vrnov0 = PseudoVFNCVT_RTZ_X_F_W_MF2_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 4 /* e16 */, 0
+ ; MIR-NEXT: early-clobber %4:vrnov0 = nofpexcept PseudoVFNCVT_RTZ_X_F_W_MF2_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 4 /* e16 */, 0
; MIR-NEXT: $v8 = COPY %4
; MIR-NEXT: PseudoRET implicit $v8
%a = fptosi <vscale x 2 x float> %x to <vscale x 2 x i16>
; MIR-NEXT: [[COPY2:%[0-9]+]]:vrm2 = COPY $v10m2
; MIR-NEXT: [[COPY3:%[0-9]+]]:vrnov0 = COPY $v8
; MIR-NEXT: $v0 = COPY [[COPY1]]
- ; MIR-NEXT: early-clobber %4:vrnov0 = PseudoVFNCVT_F_X_W_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0
+ ; MIR-NEXT: early-clobber %4:vrnov0 = nofpexcept PseudoVFNCVT_F_X_W_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0, implicit $frm
; MIR-NEXT: $v8 = COPY %4
; MIR-NEXT: PseudoRET implicit $v8
%a = sitofp <vscale x 2 x i64> %x to <vscale x 2 x float>
; MIR-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v10
; MIR-NEXT: [[COPY3:%[0-9]+]]:vrm2nov0 = COPY $v8m2
; MIR-NEXT: $v0 = COPY [[COPY1]]
- ; MIR-NEXT: early-clobber %4:vrm2nov0 = PseudoVFWCVT_F_F_V_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0
+ ; MIR-NEXT: early-clobber %4:vrm2nov0 = nofpexcept PseudoVFWCVT_F_F_V_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0
; MIR-NEXT: $v8m2 = COPY %4
; MIR-NEXT: PseudoRET implicit $v8m2
%a = fpext <vscale x 2 x float> %x to <vscale x 2 x double>
; MIR-NEXT: [[COPY2:%[0-9]+]]:vrm2 = COPY $v10m2
; MIR-NEXT: [[COPY3:%[0-9]+]]:vrnov0 = COPY $v8
; MIR-NEXT: $v0 = COPY [[COPY1]]
- ; MIR-NEXT: early-clobber %4:vrnov0 = PseudoVFNCVT_F_F_W_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0
+ ; MIR-NEXT: early-clobber %4:vrnov0 = nofpexcept PseudoVFNCVT_F_F_W_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 5 /* e32 */, 0, implicit $frm
; MIR-NEXT: $v8 = COPY %4
; MIR-NEXT: PseudoRET implicit $v8
%a = fptrunc <vscale x 2 x double> %x to <vscale x 2 x float>