drm/amdgpu: change how we update mmRLC_SPM_MC_CNTL

In pp_one_vf mode avoid the extra overhead and read/write the
registers without the KIQ.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Acked-by: Yintian Tao <yintian.tao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 40314aeddf17ba2ffec95a73ec7ae25d8b76da31..212492244e33ee5f1dfc58fd94dc0631066f1c86 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7030,14 +7030,21 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 
 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
 {
-       u32 data;
+       u32 reg, data;
 
-       data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
+       reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
+       if (amdgpu_sriov_is_pp_one_vf(adev))
+               data = RREG32_NO_KIQ(reg);
+       else
+               data = RREG32(reg);
 
        data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
        data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
 
-       WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
+       if (amdgpu_sriov_is_pp_one_vf(adev))
+               WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
+       else
+               WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
 }
 
 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index f3554b5a091d7252e31fe560c01fc6029a7e264c..053a599dd877ec5adcac98041772a12f88d849bb 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5615,12 +5615,18 @@ static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
 {
        u32 data;
 
-       data = RREG32(mmRLC_SPM_VMID);
+       if (amdgpu_sriov_is_pp_one_vf(adev))
+               data = RREG32_NO_KIQ(mmRLC_SPM_VMID);
+       else
+               data = RREG32(mmRLC_SPM_VMID);
 
        data &= ~RLC_SPM_VMID__RLC_SPM_VMID_MASK;
        data |= (vmid & RLC_SPM_VMID__RLC_SPM_VMID_MASK) << RLC_SPM_VMID__RLC_SPM_VMID__SHIFT;
 
-       WREG32(mmRLC_SPM_VMID, data);
+       if (amdgpu_sriov_is_pp_one_vf(adev))
+               WREG32_NO_KIQ(mmRLC_SPM_VMID, data);
+       else
+               WREG32(mmRLC_SPM_VMID, data);
 }
 
 static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index a0faf642daf2a027f45979d77350655f1e604277..f8273fd8191ac03d439e9d9bb5589fd7f545aada 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4950,14 +4950,21 @@ static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 
 static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
 {
-       u32 data;
+       u32 reg, data;
 
-       data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
+       reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
+       if (amdgpu_sriov_is_pp_one_vf(adev))
+               data = RREG32_NO_KIQ(reg);
+       else
+               data = RREG32(reg);
 
        data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
        data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
 
-       WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
+       if (amdgpu_sriov_is_pp_one_vf(adev))
+               WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
+       else
+               WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
 }
 
 static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev,