Allow MOVK for R_AARCH64_TLSLE_MOVW_TPREL_G{0,1}NC

bfd/
	PR gas/17843
	* elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Expect
	R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
	to be used with MOVK rather than MOVZ.

gas/
	PR gas/17843
	* config/tc-aarch64.c (process_movw_reloc_info): Allow
	R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
	for MOVK.

gas/testsuite/
	PR gas/17843
	* gas/aarch64/tls.s, gas/aarch64/tls.d: Add test for
	R_AARCH64_TLSLE_MOVW_TPREL_G0/R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
	sequence.

ld/testsuite/
	PR gas/17843
	* ld-aarch64/tlsle.s, ld-aarch64/tlsle.d: New test.
	* ld-aarch64/aarch64-elf.exp: Run it.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 72c9196..ee6adb8 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,10 @@
+2015-03-04  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR gas/17843
+       * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Expect
+       R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
+       to be used with MOVK rather than MOVZ.
+
 2015-03-03  DJ Delorie  <dj@redhat.com>
 
        * elf32-rl78.c (rl78_elf_relax_section): Only relax ADDR16's if

diff --git a/bfd/elfxx-aarch64.c b/bfd/elfxx-aarch64.c
index 1d661b3..35f3e22 100644 (file)
--- a/bfd/elfxx-aarch64.c
+++ b/bfd/elfxx-aarch64.c
@@ -304,9 +304,7 @@ _bfd_aarch64_elf_put_addend (bfd *abfd,
 
     case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
     case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
-    case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
     case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
-    case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
     case BFD_RELOC_AARCH64_MOVW_G0_S:
     case BFD_RELOC_AARCH64_MOVW_G1_S:
     case BFD_RELOC_AARCH64_MOVW_G2_S:
@@ -327,6 +325,8 @@ _bfd_aarch64_elf_put_addend (bfd *abfd,
       /* Group relocations to create a 16, 32, 48 or 64 bit unsigned
          data or abs address inline.  */
 
+    case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
+    case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
     case BFD_RELOC_AARCH64_MOVW_G0:
     case BFD_RELOC_AARCH64_MOVW_G0_NC:
     case BFD_RELOC_AARCH64_MOVW_G1:

diff --git a/gas/ChangeLog b/gas/ChangeLog
index d5cc47f..d6d6c95 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2015-03-04  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR gas/17843
+       * config/tc-aarch64.c (process_movw_reloc_info): Allow
+       R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
+       for MOVK.
+
 2015-02-28  Alan Modra  <amodra@gmail.com>
 
        * write.c (SUB_SEGMENT_ALIGN): Don't pad non-code sections at

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 1e2b182..9179fc6 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4520,9 +4520,7 @@ process_movw_reloc_info (void)
       case BFD_RELOC_AARCH64_MOVW_G1_S:
       case BFD_RELOC_AARCH64_MOVW_G2_S:
       case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
-      case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
       case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
-      case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
       case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
        set_syntax_error
          (_("the specified relocation type is not allowed for MOVK"));

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index f19792b..fb6e592 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2015-03-04  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR gas/17843
+       * gas/aarch64/tls.s, gas/aarch64/tls.d: Add test for
+       R_AARCH64_TLSLE_MOVW_TPREL_G0/R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
+       sequence.
+
 2015-02-28  Alan Modra  <amodra@gmail.com>
 
        * gas/sparc/pcrel.d: Update for changed padding in data sections.

diff --git a/gas/testsuite/gas/aarch64/tls.d b/gas/testsuite/gas/aarch64/tls.d
index 9b79c85..ab67c6a 100644 (file)
--- a/gas/testsuite/gas/aarch64/tls.d
+++ b/gas/testsuite/gas/aarch64/tls.d
@@ -31,3 +31,7 @@ Disassembly of section \.text:
                        2c: R_AARCH64_TLSLE_ADD_TPREL_HI12      var
   30:  91000020        add     x0, x1, #0x0
                        30: R_AARCH64_TLSLE_ADD_TPREL_LO12_NC   var
+  34:  d2a00000        movz    x0, #0x0, lsl #16
+                       34: R_AARCH64_TLSLE_MOVW_TPREL_G1       var
+  38:  f2800000        movk    x0, #0x0
+                       38: R_AARCH64_TLSLE_MOVW_TPREL_G0_NC    var

diff --git a/gas/testsuite/gas/aarch64/tls.s b/gas/testsuite/gas/aarch64/tls.s
index 3098970..5c85409 100644 (file)
--- a/gas/testsuite/gas/aarch64/tls.s
+++ b/gas/testsuite/gas/aarch64/tls.s
@@ -51,3 +51,6 @@ func:
        add  x0, x1, #:tprel_hi12:var, lsl #12
        // R_AARCH64_TLSLE_ADD_TPREL_LO12_NC    var
        add  x0, x1, #:tprel_lo12_nc:var
+
+       movz x0, #:tprel_g1:var
+       movk x0, #:tprel_g0_nc:var

diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index 82ff52d..acd6d81 100644 (file)
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2015-03-04  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR gas/17843
+       * ld-aarch64/tlsle.s, ld-aarch64/tlsle.d: New test.
+       * ld-aarch64/aarch64-elf.exp: Run it.
+
 2015-02-28  Alan Modra  <amodra@gmail.com>
 
        * ld-sparc/gotop32.rd: Update for changed padding in data sections.

diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp
index 37fc70a..a7ce3f2 100644 (file)
--- a/ld/testsuite/ld-aarch64/aarch64-elf.exp
+++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp
@@ -131,6 +131,7 @@ run_dump_test "tls-tiny-desc"
 run_dump_test "tls-tiny-desc-ie"
 run_dump_test "tls-tiny-desc-le"
 run_dump_test "tls-tiny-ie"
+run_dump_test "tlsle"
 run_dump_test "tlsle-symbol-offset"
 run_dump_test "gc-got-relocs"
 run_dump_test "gc-tls-relocs"

diff --git a/ld/testsuite/ld-aarch64/tlsle.d b/ld/testsuite/ld-aarch64/tlsle.d
new file mode 100644 (file)
index 0000000..c74f662
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/tlsle.d
@@ -0,0 +1,73 @@
+#source: tlsle.s
+#ld: -shared -T relocs.ld -e0
+#objdump: -dr
+
+.*: .*
+
+Disassembly of section .text:
+
+0+10000 <.text>:
+ +10000:       d2a00000        movz    x0, #0x0, lsl #16
+ +10004:       f2800200        movk    x0, #0x10
+ +10008:       d2a00000        movz    x0, #0x0, lsl #16
+ +1000c:       f28fffe0        movk    x0, #0x7fff
+ +10010:       d2a00000        movz    x0, #0x0, lsl #16
+ +10014:       f2900000        movk    x0, #0x8000
+ +10018:       d2a00000        movz    x0, #0x0, lsl #16
+ +1001c:       f29fffe0        movk    x0, #0xffff
+ +10020:       d2a00020        mov     x0, #0x10000                    // #65536
+ +10024:       f2800000        movk    x0, #0x0
+ +10028:       d2afffe0        mov     x0, #0x7fff0000                 // #2147418112
+ +1002c:       f29fffe0        movk    x0, #0xffff
+ +10030:       d2b00000        mov     x0, #0x80000000                 // #2147483648
+ +10034:       f2800000        movk    x0, #0x0
+ +10038:       d2bfffe0        mov     x0, #0xffff0000                 // #4294901760
+ +1003c:       f2800000        movk    x0, #0x0
+ +10040:       d2bfffe0        mov     x0, #0xffff0000                 // #4294901760
+ +10044:       f29fffe0        movk    x0, #0xffff
+ +10048:       d2c00000        movz    x0, #0x0, lsl #32
+ +1004c:       f2a00000        movk    x0, #0x0, lsl #16
+ +10050:       f2800200        movk    x0, #0x10
+ +10054:       d2c00000        movz    x0, #0x0, lsl #32
+ +10058:       f2a00000        movk    x0, #0x0, lsl #16
+ +1005c:       f28fffe0        movk    x0, #0x7fff
+ +10060:       d2c00000        movz    x0, #0x0, lsl #32
+ +10064:       f2a00000        movk    x0, #0x0, lsl #16
+ +10068:       f2900000        movk    x0, #0x8000
+ +1006c:       d2c00000        movz    x0, #0x0, lsl #32
+ +10070:       f2a00000        movk    x0, #0x0, lsl #16
+ +10074:       f29fffe0        movk    x0, #0xffff
+ +10078:       d2c00000        movz    x0, #0x0, lsl #32
+ +1007c:       f2a00020        movk    x0, #0x1, lsl #16
+ +10080:       f2800000        movk    x0, #0x0
+ +10084:       d2c00000        movz    x0, #0x0, lsl #32
+ +10088:       f2afffe0        movk    x0, #0x7fff, lsl #16
+ +1008c:       f29fffe0        movk    x0, #0xffff
+ +10090:       d2c00000        movz    x0, #0x0, lsl #32
+ +10094:       f2b00000        movk    x0, #0x8000, lsl #16
+ +10098:       f2800000        movk    x0, #0x0
+ +1009c:       d2c00000        movz    x0, #0x0, lsl #32
+ +100a0:       f2bfffe0        movk    x0, #0xffff, lsl #16
+ +100a4:       f2800000        movk    x0, #0x0
+ +100a8:       d2c00000        movz    x0, #0x0, lsl #32
+ +100ac:       f2bfffe0        movk    x0, #0xffff, lsl #16
+ +100b0:       f29fffe0        movk    x0, #0xffff
+ +100b4:       d2c00020        mov     x0, #0x100000000                // #4294967296
+ +100b8:       f2a00000        movk    x0, #0x0, lsl #16
+ +100bc:       f2824660        movk    x0, #0x1233
+ +100c0:       d2c24680        mov     x0, #0x123400000000             // #20014547599360
+ +100c4:       f2aacf00        movk    x0, #0x5678, lsl #16
+ +100c8:       f2921560        movk    x0, #0x90ab
+ +100cc:       d2c24680        mov     x0, #0x123400000000             // #20014547599360
+ +100d0:       f2bfffe0        movk    x0, #0xffff, lsl #16
+ +100d4:       f2800000        movk    x0, #0x0
+ +100d8:       d2c24680        mov     x0, #0x123400000000             // #20014547599360
+ +100dc:       f2bfffe0        movk    x0, #0xffff, lsl #16
+ +100e0:       f29fffc0        movk    x0, #0xfffe
+ +100e4:       d2d00000        mov     x0, #0x800000000000             // #140737488355328
+ +100e8:       f2a00000        movk    x0, #0x0, lsl #16
+ +100ec:       f2800020        movk    x0, #0x1
+ +100f0:       d2dfffe0        mov     x0, #0xffff00000000             // #281470681743360
+ +100f4:       f2bfffe0        movk    x0, #0xffff, lsl #16
+ +100f8:       f29fffe0        movk    x0, #0xffff
+ +100fc:       d65f03c0        ret

diff --git a/ld/testsuite/ld-aarch64/tlsle.s b/ld/testsuite/ld-aarch64/tlsle.s
new file mode 100644 (file)
index 0000000..2d68fe7
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/tlsle.s
@@ -0,0 +1,98 @@
+       .section        .tbss,"awT",%nobits
+a10:
+       .zero   0x7fef
+a7fff:
+       .zero   0x1
+a8000:
+       .zero   0x7fff
+affff:
+       .zero   0x1
+a10000:
+       .zero   0x7ffeffff
+a7fffffff:
+       .zero   0x1
+a80000000:
+       .zero   0x7fff0000
+affff0000:
+       .zero   0x0000ffff
+affffffff:
+       .zero   0x1234
+a100001233:
+       .zero   0x123356787e78
+a1234567890ab:
+       .zero   0xa9866f55
+a1234ffff0000:
+       .zero   0xfffe
+a1234fffffffe:
+       .zero   0x6dcb00000003
+a800000000001:
+       .zero   0x7ffffffffffe
+affffffffffff:
+       .zero   0x1234
+
+       .text
+       movz    x0, #:tprel_g1:a10
+       movk    x0, #:tprel_g0_nc:a10
+       movz    x0, #:tprel_g1:a7fff
+       movk    x0, #:tprel_g0_nc:a7fff
+       movz    x0, #:tprel_g1:a8000
+       movk    x0, #:tprel_g0_nc:a8000
+       movz    x0, #:tprel_g1:affff
+       movk    x0, #:tprel_g0_nc:affff
+       movz    x0, #:tprel_g1:a10000
+       movk    x0, #:tprel_g0_nc:a10000
+       movz    x0, #:tprel_g1:a7fffffff
+       movk    x0, #:tprel_g0_nc:a7fffffff
+       movz    x0, #:tprel_g1:a80000000
+       movk    x0, #:tprel_g0_nc:a80000000
+       movz    x0, #:tprel_g1:affff0000
+       movk    x0, #:tprel_g0_nc:affff0000
+       movz    x0, #:tprel_g1:affffffff
+       movk    x0, #:tprel_g0_nc:affffffff
+
+       movz    x0, #:tprel_g2:a10
+       movk    x0, #:tprel_g1_nc:a10
+       movk    x0, #:tprel_g0_nc:a10
+       movz    x0, #:tprel_g2:a7fff
+       movk    x0, #:tprel_g1_nc:a7fff
+       movk    x0, #:tprel_g0_nc:a7fff
+       movz    x0, #:tprel_g2:a8000
+       movk    x0, #:tprel_g1_nc:a8000
+       movk    x0, #:tprel_g0_nc:a8000
+       movz    x0, #:tprel_g2:affff
+       movk    x0, #:tprel_g1_nc:affff
+       movk    x0, #:tprel_g0_nc:affff
+       movz    x0, #:tprel_g2:a10000
+       movk    x0, #:tprel_g1_nc:a10000
+       movk    x0, #:tprel_g0_nc:a10000
+       movz    x0, #:tprel_g2:a7fffffff
+       movk    x0, #:tprel_g1_nc:a7fffffff
+       movk    x0, #:tprel_g0_nc:a7fffffff
+       movz    x0, #:tprel_g2:a80000000
+       movk    x0, #:tprel_g1_nc:a80000000
+       movk    x0, #:tprel_g0_nc:a80000000
+       movz    x0, #:tprel_g2:affff0000
+       movk    x0, #:tprel_g1_nc:affff0000
+       movk    x0, #:tprel_g0_nc:affff0000
+       movz    x0, #:tprel_g2:affffffff
+       movk    x0, #:tprel_g1_nc:affffffff
+       movk    x0, #:tprel_g0_nc:affffffff
+       movz    x0, #:tprel_g2:a100001233
+       movk    x0, #:tprel_g1_nc:a100001233
+       movk    x0, #:tprel_g0_nc:a100001233
+       movz    x0, #:tprel_g2:a1234567890ab
+       movk    x0, #:tprel_g1_nc:a1234567890ab
+       movk    x0, #:tprel_g0_nc:a1234567890ab
+       movz    x0, #:tprel_g2:a1234ffff0000
+       movk    x0, #:tprel_g1_nc:a1234ffff0000
+       movk    x0, #:tprel_g0_nc:a1234ffff0000
+       movz    x0, #:tprel_g2:a1234fffffffe
+       movk    x0, #:tprel_g1_nc:a1234fffffffe
+       movk    x0, #:tprel_g0_nc:a1234fffffffe
+       movz    x0, #:tprel_g2:a800000000001
+       movk    x0, #:tprel_g1_nc:a800000000001
+       movk    x0, #:tprel_g0_nc:a800000000001
+       movz    x0, #:tprel_g2:affffffffffff
+       movk    x0, #:tprel_g1_nc:affffffffffff
+       movk    x0, #:tprel_g0_nc:affffffffffff
+       ret