reset: imx7: Add support for i.MX8MP SoC

i.MX8MP is a new SoC of i.MX8M family, it has same src IP
inside but with different module layout, add support for it.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index 1443a55..d170fe6 100644 (file)
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -15,6 +15,7 @@
 #include <linux/regmap.h>
 #include <dt-bindings/reset/imx7-reset.h>
 #include <dt-bindings/reset/imx8mq-reset.h>
+#include <dt-bindings/reset/imx8mp-reset.h>
 
 struct imx7_src_signal {
        unsigned int offset, bit;
@@ -145,6 +146,18 @@ enum imx8mq_src_registers {
        SRC_DDRC2_RCR           = 0x1004,
 };
 
+enum imx8mp_src_registers {
+       SRC_SUPERMIX_RCR        = 0x0018,
+       SRC_AUDIOMIX_RCR        = 0x001c,
+       SRC_MLMIX_RCR           = 0x0028,
+       SRC_GPU2D_RCR           = 0x0038,
+       SRC_GPU3D_RCR           = 0x003c,
+       SRC_VPU_G1_RCR          = 0x0048,
+       SRC_VPU_G2_RCR          = 0x004c,
+       SRC_VPUVC8KE_RCR        = 0x0050,
+       SRC_NOC_RCR             = 0x0054,
+};
+
 static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
        [IMX8MQ_RESET_A53_CORE_POR_RESET0]      = { SRC_A53RCR0, BIT(0) },
        [IMX8MQ_RESET_A53_CORE_POR_RESET1]      = { SRC_A53RCR0, BIT(1) },
@@ -253,6 +266,93 @@ static const struct imx7_src_variant variant_imx8mq = {
        },
 };
 
+static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = {
+       [IMX8MP_RESET_A53_CORE_POR_RESET0]      = { SRC_A53RCR0, BIT(0) },
+       [IMX8MP_RESET_A53_CORE_POR_RESET1]      = { SRC_A53RCR0, BIT(1) },
+       [IMX8MP_RESET_A53_CORE_POR_RESET2]      = { SRC_A53RCR0, BIT(2) },
+       [IMX8MP_RESET_A53_CORE_POR_RESET3]      = { SRC_A53RCR0, BIT(3) },
+       [IMX8MP_RESET_A53_CORE_RESET0]          = { SRC_A53RCR0, BIT(4) },
+       [IMX8MP_RESET_A53_CORE_RESET1]          = { SRC_A53RCR0, BIT(5) },
+       [IMX8MP_RESET_A53_CORE_RESET2]          = { SRC_A53RCR0, BIT(6) },
+       [IMX8MP_RESET_A53_CORE_RESET3]          = { SRC_A53RCR0, BIT(7) },
+       [IMX8MP_RESET_A53_DBG_RESET0]           = { SRC_A53RCR0, BIT(8) },
+       [IMX8MP_RESET_A53_DBG_RESET1]           = { SRC_A53RCR0, BIT(9) },
+       [IMX8MP_RESET_A53_DBG_RESET2]           = { SRC_A53RCR0, BIT(10) },
+       [IMX8MP_RESET_A53_DBG_RESET3]           = { SRC_A53RCR0, BIT(11) },
+       [IMX8MP_RESET_A53_ETM_RESET0]           = { SRC_A53RCR0, BIT(12) },
+       [IMX8MP_RESET_A53_ETM_RESET1]           = { SRC_A53RCR0, BIT(13) },
+       [IMX8MP_RESET_A53_ETM_RESET2]           = { SRC_A53RCR0, BIT(14) },
+       [IMX8MP_RESET_A53_ETM_RESET3]           = { SRC_A53RCR0, BIT(15) },
+       [IMX8MP_RESET_A53_SOC_DBG_RESET]        = { SRC_A53RCR0, BIT(20) },
+       [IMX8MP_RESET_A53_L2RESET]              = { SRC_A53RCR0, BIT(21) },
+       [IMX8MP_RESET_SW_NON_SCLR_M7C_RST]      = { SRC_M4RCR, BIT(0) },
+       [IMX8MP_RESET_OTG1_PHY_RESET]           = { SRC_USBOPHY1_RCR, BIT(0) },
+       [IMX8MP_RESET_OTG2_PHY_RESET]           = { SRC_USBOPHY2_RCR, BIT(0) },
+       [IMX8MP_RESET_SUPERMIX_RESET]           = { SRC_SUPERMIX_RCR, BIT(0) },
+       [IMX8MP_RESET_AUDIOMIX_RESET]           = { SRC_AUDIOMIX_RCR, BIT(0) },
+       [IMX8MP_RESET_MLMIX_RESET]              = { SRC_MLMIX_RCR, BIT(0) },
+       [IMX8MP_RESET_PCIEPHY]                  = { SRC_PCIEPHY_RCR, BIT(2) },
+       [IMX8MP_RESET_PCIEPHY_PERST]            = { SRC_PCIEPHY_RCR, BIT(3) },
+       [IMX8MP_RESET_PCIE_CTRL_APPS_EN]        = { SRC_PCIEPHY_RCR, BIT(6) },
+       [IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF]   = { SRC_PCIEPHY_RCR, BIT(11) },
+       [IMX8MP_RESET_HDMI_PHY_APB_RESET]       = { SRC_HDMI_RCR, BIT(0) },
+       [IMX8MP_RESET_MEDIA_RESET]              = { SRC_DISP_RCR, BIT(0) },
+       [IMX8MP_RESET_GPU2D_RESET]              = { SRC_GPU2D_RCR, BIT(0) },
+       [IMX8MP_RESET_GPU3D_RESET]              = { SRC_GPU3D_RCR, BIT(0) },
+       [IMX8MP_RESET_GPU_RESET]                = { SRC_GPU_RCR, BIT(0) },
+       [IMX8MP_RESET_VPU_RESET]                = { SRC_VPU_RCR, BIT(0) },
+       [IMX8MP_RESET_VPU_G1_RESET]             = { SRC_VPU_G1_RCR, BIT(0) },
+       [IMX8MP_RESET_VPU_G2_RESET]             = { SRC_VPU_G2_RCR, BIT(0) },
+       [IMX8MP_RESET_VPUVC8KE_RESET]           = { SRC_VPUVC8KE_RCR, BIT(0) },
+       [IMX8MP_RESET_NOC_RESET]                = { SRC_NOC_RCR, BIT(0) },
+};
+
+static int imx8mp_reset_set(struct reset_controller_dev *rcdev,
+                           unsigned long id, bool assert)
+{
+       struct imx7_src *imx7src = to_imx7_src(rcdev);
+       const unsigned int bit = imx7src->signals[id].bit;
+       unsigned int value = assert ? bit : 0;
+
+       switch (id) {
+       case IMX8MP_RESET_PCIEPHY:
+               /*
+                * wait for more than 10us to release phy g_rst and
+                * btnrst
+                */
+               if (!assert)
+                       udelay(10);
+               break;
+
+       case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
+               value = assert ? 0 : bit;
+               break;
+       }
+
+       return imx7_reset_update(imx7src, id, value);
+}
+
+static int imx8mp_reset_assert(struct reset_controller_dev *rcdev,
+                              unsigned long id)
+{
+       return imx8mp_reset_set(rcdev, id, true);
+}
+
+static int imx8mp_reset_deassert(struct reset_controller_dev *rcdev,
+                                unsigned long id)
+{
+       return imx8mp_reset_set(rcdev, id, false);
+}
+
+static const struct imx7_src_variant variant_imx8mp = {
+       .signals = imx8mp_src_signals,
+       .signals_num = ARRAY_SIZE(imx8mp_src_signals),
+       .ops = {
+               .assert   = imx8mp_reset_assert,
+               .deassert = imx8mp_reset_deassert,
+       },
+};
+
 static int imx7_reset_probe(struct platform_device *pdev)
 {
        struct imx7_src *imx7src;
@@ -283,6 +383,7 @@ static int imx7_reset_probe(struct platform_device *pdev)
 static const struct of_device_id imx7_reset_dt_ids[] = {
        { .compatible = "fsl,imx7d-src", .data = &variant_imx7 },
        { .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq },
+       { .compatible = "fsl,imx8mp-src", .data = &variant_imx8mp },
        { /* sentinel */ },
 };