dtsi:Add reset nodes about timer

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index c119732..a0e1134 100755 (executable)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -419,6 +419,13 @@
                                 <&clkgen JH7110_TIMER_CLK_APB>;
                        clock-names = "timer0", "timer1",
                                      "timer2", "timer3", "apb_clk";
+                       resets = <&rstgen RSTN_U0_TIMER_TIMER0>,
+                                <&rstgen RSTN_U0_TIMER_TIMER1>,
+                                <&rstgen RSTN_U0_TIMER_TIMER2>,
+                                <&rstgen RSTN_U0_TIMER_TIMER3>,
+                                <&rstgen RSTN_U0_TIMER_APB>;
+                       reset-names = "timer0", "timer1",
+                                     "timer2", "timer3", "apb_rst";
                        clock-frequency = <24000000>;
                        status = "okay";
                };