// * TYP_SIMD16: 0x10
// * TYP_SIMD32: 0x20
// * TYP_SIMD64: 0x40
- toggleBit = 0x4040404040404040 >> ((elemSize / 2) + (simdSize / 32));
-
- assert(((simdSize == 16) && (toggleBit == 0x1010101010101010)) ||
- ((simdSize == 32) && (toggleBit == 0x2020202020202020)) ||
- ((simdSize == 64) && (toggleBit == 0x4040404040404040)));
+ switch (simdSize)
+ {
+ case 16:
+ toggleBit = 0x1010101010101010;
+ break;
+ case 32:
+ toggleBit = 0x2020202020202020;
+ break;
+ default:
+ assert(simdSize == 64);
+ toggleBit = 0x4040404040404040;
+ break;
+ }
break;
}
// * TYP_SIMD16: 0x08
// * TYP_SIMD32: 0x10
// * TYP_SIMD64: 0x20
- toggleBit = 0x0020002000200020 >> ((elemSize / 2) + (simdSize / 32));
-
- assert(((simdSize == 16) && (toggleBit == 0x0008000800080008)) ||
- ((simdSize == 32) && (toggleBit == 0x0010001000100010)) ||
- ((simdSize == 64) && (toggleBit == 0x0020002000200020)));
+ switch (simdSize)
+ {
+ case 16:
+ toggleBit = 0x0008000800080008;
+ break;
+ case 32:
+ toggleBit = 0x0010001000100010;
+ break;
+ default:
+ assert(simdSize == 64);
+ toggleBit = 0x0020002000200020;
+ break;
+ }
break;
}
// * TYP_SIMD16: 0x04
// * TYP_SIMD32: 0x08
// * TYP_SIMD64: 0x10
- toggleBit = 0x0000001000000010 >> ((elemSize / 2) + (simdSize / 32));
-
- assert(((simdSize == 16) && (toggleBit == 0x0000000400000004)) ||
- ((simdSize == 32) && (toggleBit == 0x0000000800000008)) ||
- ((simdSize == 64) && (toggleBit == 0x0000001000000010)));
+ switch (simdSize)
+ {
+ case 16:
+ toggleBit = 0x0000000400000004;
+ break;
+ case 32:
+ toggleBit = 0x0000000800000008;
+ break;
+ default:
+ assert(simdSize == 64);
+ toggleBit = 0x0000001000000010;
+ break;
+ }
break;
}
// * TYP_SIMD16: 0x02
// * TYP_SIMD32: 0x04
// * TYP_SIMD64: 0x08
- toggleBit = 0x0000000000000008 >> ((elemSize / 2) + (simdSize / 32));
-
- assert(((simdSize == 16) && (toggleBit == 0x0000000000000002)) ||
- ((simdSize == 32) && (toggleBit == 0x0000000000000004)) ||
- ((simdSize == 64) && (toggleBit == 0x0000000000000008)));
+ switch (simdSize)
+ {
+ case 16:
+ toggleBit = 0x0000000000000002;
+ break;
+ case 32:
+ toggleBit = 0x0000000000000004;
+ break;
+ default:
+ assert(simdSize == 64);
+ toggleBit = 0x0000000000000008;
+ break;
+ }
break;
}
--- /dev/null
+// Licensed to the .NET Foundation under one or more agreements.
+// The .NET Foundation licenses this file to you under the MIT license.
+
+using System.Runtime.CompilerServices;
+using System.Runtime.Intrinsics;
+using System.Runtime.Intrinsics.X86;
+using Xunit;
+
+public class Runtime_89456
+{
+ [MethodImpl(MethodImplOptions.NoInlining)]
+ private static Vector512<ushort> PermuteVar32x16x2Test(Vector512<ushort> left, ushort right)
+ {
+ var r8w = right;
+ var zmm0 = left;
+ var zmm1 = Vector512.CreateScalarUnsafe(r8w);
+ var zmm2 = Vector512.Create((ushort)1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+ return Avx512BW.PermuteVar32x16x2(zmm0, zmm2, zmm1);
+ }
+
+ [Fact]
+ public static int TestEntryPoint()
+ {
+ if (Avx512BW.IsSupported)
+ {
+ var expected = Vector512.Create((ushort)1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+ Vector512<ushort> actual = PermuteVar32x16x2Test(Vector512.Create(ushort.MinValue, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31), 32);
+ if (actual != expected)
+ {
+ return 101;
+ }
+ }
+ return 100;
+ }
+}