Merge tag 'dm-pull-1apr20' of git://git.denx.de/u-boot-dm

Vboot vulnerability fix

diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi
index 81a363d..422dad1 100644 (file)
--- a/arch/arm/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi
@@ -288,6 +288,57 @@
                                };
                        };
 
+                       ethernet0_rgmii_pins_b: rgmii-1 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
+                                                <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
+                                                <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */
+                                                <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+                                                <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+                                                <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
+                                                <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */
+                                                <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <2>;
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <0>;
+                               };
+                               pins3 {
+                                       pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
+                                                <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
+                                                <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
+                                                <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
+                                                <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
+                                                <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
+                                       bias-disable;
+                               };
+                       };
+
+                       ethernet0_rgmii_pins_sleep_b: rgmii-sleep-1 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
+                                                <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+                                                <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */
+                                                <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
+                                                <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
+                                                <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
+                                                <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
+                                                <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+                                                <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
+                                                <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+                                                <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
+                                                <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
+                                                <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
+                                                <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
+                                                <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
+                               };
+                       };
+
                        fmc_pins_a: fmc-0 {
                                pins1 {
                                        pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
@@ -832,6 +883,30 @@
                                };
                        };
 
+                       sdmmc1_dir_pins_b: sdmmc1-dir-1 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
+                                                <STM32_PINMUX('E', 14, AF8)>, /* SDMMC1_D123DIR */
+                                                <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
+                                       slew-rate = <1>;
+                                       drive-push-pull;
+                                       bias-pull-up;
+                               };
+                               pins2{
+                                       pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
+                                       bias-pull-up;
+                               };
+                       };
+
+                       sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
+                                                <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */
+                                                <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
+                                                <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
+                               };
+                       };
+
                        sdmmc2_b4_pins_a: sdmmc2-b4-0 {
                                pins1 {
                                        pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
@@ -907,6 +982,27 @@
                                };
                        };
 
+                       sdmmc2_d47_pins_b: sdmmc2-d47-1 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+                                                <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
+                                                <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
+                                                <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+                                       slew-rate = <1>;
+                                       drive-push-pull;
+                                       bias-pull-up;
+                               };
+                       };
+
+                       sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
+                                                <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */
+                                                <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
+                                                <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
+                               };
+                       };
+
                        spdifrx_pins_a: spdifrx-0 {
                                pins {
                                        pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */

diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi
index d6dc746..2c7dc50 100644 (file)
--- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi
@@ -150,9 +150,12 @@
        };
 };
 
-&sdmmc1_dir_pins_a {
+&sdmmc1_dir_pins_b {
        u-boot,dm-spl;
-       pins {
+       pins1 {
+               u-boot,dm-spl;
+       };
+       pins2 {
                u-boot,dm-spl;
        };
 };
@@ -171,7 +174,7 @@
        };
 };
 
-&sdmmc2_d47_pins_a {
+&sdmmc2_d47_pins_b {
        u-boot,dm-spl;
        pins {
                u-boot,dm-spl;

diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts
index 3065593..1f32395 100644 (file)
--- a/arch/arm/dts/stm32mp157a-avenger96.dts
+++ b/arch/arm/dts/stm32mp157a-avenger96.dts
@@ -16,10 +16,12 @@
        compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
 
        aliases {
+               eeprom0 = &eeprom0;
                ethernet0 = &ethernet0;
                mmc0 = &sdmmc1;
                serial0 = &uart4;
                serial1 = &uart7;
+               spi0 = &qspi;
        };
 
        chosen {
@@ -76,16 +78,42 @@
                        default-state = "off";
                };
        };
+
+       sd_switch: regulator-sd_switch {
+               compatible = "regulator-gpio";
+               regulator-name = "sd_switch";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <2900000>;
+               regulator-type = "voltage";
+               regulator-always-on;
+
+               gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
+               gpios-states = <0>;
+               states = <1800000 0x1>,
+                        <2900000 0x0>;
+       };
+
+       /* Enpirion EP3A8LQI U2 on the DHCOR */
+       vdd_io: regulator-buck-io {
+               compatible = "regulator-fixed";
+               regulator-name = "buck-io";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-always-on;
+               regulator-boot-on;
+               vin-supply = <&vdd>;
+       };
 };
 
 &ethernet0 {
        status = "okay";
-       pinctrl-0 = <&ethernet0_rgmii_pins_a>;
-       pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
+       pinctrl-0 = <&ethernet0_rgmii_pins_b>;
+       pinctrl-1 = <&ethernet0_rgmii_pins_sleep_b>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rgmii";
        max-speed = <1000>;
        phy-handle = <&phy0>;
+       phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
 
        mdio0 {
                #address-cells = <1>;
@@ -151,7 +179,7 @@
 
                        vddcore: buck1 {
                                regulator-name = "vddcore";
-                               regulator-min-microvolt = <1200000>;
+                               regulator-min-microvolt = <800000>;
                                regulator-max-microvolt = <1350000>;
                                regulator-always-on;
                                regulator-initial-mode = <0>;
@@ -169,8 +197,8 @@
 
                        vdd: buck3 {
                                regulator-name = "vdd";
-                               regulator-min-microvolt = <3300000>;
-                               regulator-max-microvolt = <3300000>;
+                               regulator-min-microvolt = <2900000>;
+                               regulator-max-microvolt = <2900000>;
                                regulator-always-on;
                                st,mask_reset;
                                regulator-initial-mode = <0>;
@@ -252,6 +280,7 @@
                                regulator-name = "vbus_otg";
                                interrupts = <IT_OCP_OTG 0>;
                                interrupt-parent = <&pmic>;
+                               regulator-active-discharge = <1>;
                        };
 
                        vbus_sw: pwr_sw2 {
@@ -274,6 +303,12 @@
                        status = "disabled";
                };
        };
+
+       eeprom0: eeprom@53 {
+               compatible = "atmel,24c02";
+               reg = <0x53>;
+               pagesize = <16>;
+       };
 };
 
 &iwdg2 {
@@ -282,10 +317,29 @@
 };
 
 &pwr_regulators {
-       vdd-supply = <&vdd>;
+       vdd-supply = <&vdd_io>;
        vdd_3v3_usbfs-supply = <&vdd_usb>;
 };
 
+&qspi {
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
+       pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
+       reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "okay";
+
+       flash0: spi-flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-rx-bus-width = <4>;
+               spi-max-frequency = <108000000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+       };
+};
+
 &rng1 {
        status = "okay";
 };
@@ -296,21 +350,24 @@
 
 &sdmmc1 {
        pinctrl-names = "default", "opendrain", "sleep";
-       pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
-       pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
-       pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
-       broken-cd;
+       pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
+       pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
+       pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
+       cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;
+       disable-wp;
        st,sig-dir;
        st,neg-edge;
        st,use-ckin;
+       sd-uhs-sdr104;
        bus-width = <4>;
        vmmc-supply = <&vdd_sd>;
+       vqmmc-supply = <&sd_switch>;
        status = "okay";
 };
 
 &sdmmc2 {
        pinctrl-names = "default";
-       pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+       pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>;
        non-removable;
        no-sd;
        no-sdio;

diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
index bed69c9..e5be0a7 100644 (file)
--- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
@@ -10,6 +10,10 @@
 #include <dt-bindings/mfd/st,stpmic1.h>
 
 / {
+       aliases {
+               eeprom0 = &eeprom0;
+       };
+
        memory@c0000000 {
                device_type = "memory";
                reg = <0xC0000000 0x40000000>;
@@ -187,7 +191,7 @@
                };
        };
 
-       eeprom@50 {
+       eeprom0: eeprom@50 {
                compatible = "atmel,24c02";
                reg = <0x50>;
                pagesize = <16>;

diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index b663696..7bcd713 100644 (file)
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -78,22 +78,21 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int setup_mac_address(void)
 {
-       struct udevice *dev;
-       ofnode eeprom;
        unsigned char enetaddr[6];
-       int ret;
+       struct udevice *dev;
+       int off, ret;
 
        ret = eth_env_get_enetaddr("ethaddr", enetaddr);
        if (ret)        /* ethaddr is already set */
                return 0;
 
-       eeprom = ofnode_path("/soc/i2c@5c002000/eeprom@50");
-       if (!ofnode_valid(eeprom)) {
-               printf("Invalid hardware path to EEPROM!\n");
-               return -ENODEV;
+       off = fdt_path_offset(gd->fdt_blob, "eeprom0");
+       if (off < 0) {
+               printf("%s: No eeprom0 path offset\n", __func__);
+               return off;
        }
 
-       ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
+       ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
        if (ret) {
                printf("Cannot find EEPROM!\n");
                return ret;