case MONO_TYPE_U8:
return calli? OP_LCALL_REG: virt? OP_LCALL_MEMBASE: OP_LCALL;
case MONO_TYPE_R4:
- if (cfg->r4fp)
- return calli? OP_RCALL_REG: virt? OP_RCALL_MEMBASE: OP_RCALL;
- else
- return calli? OP_FCALL_REG: virt? OP_FCALL_MEMBASE: OP_FCALL;
+ return calli? OP_RCALL_REG: virt? OP_RCALL_MEMBASE: OP_RCALL;
case MONO_TYPE_R8:
return calli? OP_FCALL_REG: virt? OP_FCALL_MEMBASE: OP_FCALL;
case MONO_TYPE_VALUETYPE:
MONO_OPT_GSHARED | \
MONO_OPT_SIMD | \
MONO_OPT_ALIAS_ANALYSIS | \
- MONO_OPT_AOT | \
- MONO_OPT_FLOAT32)
+ MONO_OPT_AOT)
#define EXCLUDED_FROM_ALL (MONO_OPT_PRECOMP | MONO_OPT_UNSAFE | MONO_OPT_GSHAREDVT)
MonoInst *ins = NULL;
int opcode = 0;
// Convert Math and MathF methods into LLVM intrinsics, e.g. MathF.Sin -> @llvm.sin.f32
- if (in_corlib && !strcmp (m_class_get_name (cmethod->klass), "MathF") && cfg->r4fp) {
+ if (in_corlib && !strcmp (m_class_get_name (cmethod->klass), "MathF")) {
// (float)
if (fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R4) {
if (!strcmp (cmethod->name, "Ceiling")) {
return OP_LMOVE;
#endif
case MONO_TYPE_R4:
- return cfg->r4fp ? OP_RMOVE : OP_FMOVE;
+ return OP_RMOVE;
case MONO_TYPE_R8:
return OP_FMOVE;
case MONO_TYPE_VALUETYPE:
MonoInst *arg1 = *arg1_ref;
MonoInst *arg2 = *arg2_ref;
- if (cfg->r4fp &&
- ((arg1->type == STACK_R4 && arg2->type == STACK_R8) ||
+ if (((arg1->type == STACK_R4 && arg2->type == STACK_R8) ||
(arg1->type == STACK_R8 && arg2->type == STACK_R4))) {
MonoInst *conv;
static MonoInst*
convert_value (MonoCompile *cfg, MonoType *type, MonoInst *ins)
{
- if (!cfg->r4fp)
- return ins;
type = mini_get_underlying_type (type);
switch (type->type) {
case MONO_TYPE_R4:
MONO_EMIT_NEW_ICONST (cfg, dreg, 0);
} else if (t == MONO_TYPE_I8 || t == MONO_TYPE_U8) {
MONO_EMIT_NEW_I8CONST (cfg, dreg, 0);
- } else if (cfg->r4fp && t == MONO_TYPE_R4) {
+ } else if (t == MONO_TYPE_R4) {
MONO_INST_NEW (cfg, ins, OP_R4CONST);
ins->type = STACK_R4;
ins->inst_p0 = (void*)&r4_0;
ins->dreg = dreg;
MONO_ADD_INS (cfg->cbb, ins);
- } else if (t == MONO_TYPE_R4 || t == MONO_TYPE_R8) {
+ } else if (t == MONO_TYPE_R8) {
MONO_INST_NEW (cfg, ins, OP_R8CONST);
ins->type = STACK_R8;
ins->inst_p0 = (void*)&r8_0;
MONO_EMIT_NEW_DUMMY_INIT (cfg, dreg, OP_DUMMY_ICONST);
} else if (t == MONO_TYPE_I8 || t == MONO_TYPE_U8) {
MONO_EMIT_NEW_DUMMY_INIT (cfg, dreg, OP_DUMMY_I8CONST);
- } else if (cfg->r4fp && t == MONO_TYPE_R4) {
+ } else if (t == MONO_TYPE_R4) {
MONO_EMIT_NEW_DUMMY_INIT (cfg, dreg, OP_DUMMY_R4CONST);
- } else if (t == MONO_TYPE_R4 || t == MONO_TYPE_R8) {
+ } else if (t == MONO_TYPE_R8) {
MONO_EMIT_NEW_DUMMY_INIT (cfg, dreg, OP_DUMMY_R8CONST);
} else if ((t == MONO_TYPE_VALUETYPE) || (t == MONO_TYPE_TYPEDBYREF) ||
((t == MONO_TYPE_GENERICINST) && mono_type_generic_inst_is_valuetype (rtype))) {
amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (target_mgreg_t));
break;
case OP_AMD64_SET_XMMREG_R4: {
- if (cfg->r4fp) {
- if (ins->dreg != ins->sreg1)
- amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
- } else {
- amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
- }
+ if (ins->dreg != ins->sreg1)
+ amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
break;
}
case OP_AMD64_SET_XMMREG_R8: {
float f = *(float *)ins->inst_p0;
if ((f == 0.0) && (mono_signbit (f) == 0)) {
- if (cfg->r4fp)
- amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
- else
- amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
+ amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
} else {
if (cfg->compile_aot && cfg->code_exec_only) {
mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4_GOT, ins->inst_p0);
mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
}
- if (!cfg->r4fp)
- amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
}
break;
}
amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
break;
case OP_STORER4_MEMBASE_REG:
- if (cfg->r4fp) {
- amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
- } else {
- /* This requires a double->single conversion */
- amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
- amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
- }
+ amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
break;
case OP_LOADR4_MEMBASE:
- if (cfg->r4fp) {
- amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
- } else {
- amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
- amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
- }
+ amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
break;
case OP_ICONV_TO_R4:
- if (cfg->r4fp) {
- amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
- } else {
- amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
- amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
- }
+ amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
break;
case OP_ICONV_TO_R8:
amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
break;
case OP_LCONV_TO_R4:
- if (cfg->r4fp) {
- amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
- } else {
- amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
- amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
- }
+ amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
break;
case OP_LCONV_TO_R8:
amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
break;
case OP_FCONV_TO_R4:
- if (cfg->r4fp) {
- amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
- } else {
- amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
- amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
- }
+ amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
break;
case OP_FCONV_TO_I1:
code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
break;
case OP_MOVE_F_TO_I4:
- if (cfg->r4fp) {
- amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
- } else {
- amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
- amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
- }
+ amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
break;
case OP_MOVE_I4_TO_F:
amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
- if (!cfg->r4fp)
- amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
break;
case OP_MOVE_F_TO_I8:
amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
break;
}
case OP_ATOMIC_LOAD_R4: {
- if (cfg->r4fp) {
- amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
- } else {
- amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
- amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
- }
+ amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
break;
}
case OP_ATOMIC_LOAD_R8: {
break;
}
case OP_ATOMIC_STORE_R4: {
- if (cfg->r4fp) {
- amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
- } else {
- amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
- amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
- }
-
+ amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
x86_mfence (code);
break;
case OP_INSERTX_R4_SLOW:
switch (ins->inst_c0) {
case 0:
- if (cfg->r4fp)
- amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
- else
- amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
+ amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
break;
case 1:
amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
- if (cfg->r4fp)
- amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
- else
- amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
+ amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
break;
case 2:
amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
- if (cfg->r4fp)
- amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
- else
- amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
+ amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
break;
case 3:
amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
- if (cfg->r4fp)
- amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
- else
- amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
+ amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
break;
}
break;
case OP_ICONV_TO_R4_RAW:
amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
- if (!cfg->r4fp)
- amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
break;
case OP_FCONV_TO_R8_X:
amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
break;
case OP_EXPAND_R4:
- if (cfg->r4fp) {
- amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
- } else {
- amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
- amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
- }
+ amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
break;
case OP_EXPAND_R8:
#define MONO_ARCH_HAVE_SDB_TRAMPOLINES 1
#define MONO_ARCH_HAVE_OP_GENERIC_CLASS_INIT 1
#define MONO_ARCH_HAVE_GENERAL_RGCTX_LAZY_FETCH_TRAMPOLINE 1
-#define MONO_ARCH_FLOAT32_SUPPORTED 1
#define MONO_ARCH_LLVM_TARGET_LAYOUT "e-i64:64-i128:128-n8:16:32:64-S128"
#define MONO_ARCH_HAVE_INTERP_PINVOKE_TRAMP
ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
break;
case OP_ATOMIC_LOAD_R4:
- if (cfg->r4fp) {
- ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
- ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
- } else {
- code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
- ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
- ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
- ARM_CVTS (code, ins->dreg, vfp_scratch1);
- code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
- }
+ ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
+ ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
break;
case OP_ATOMIC_LOAD_R8:
ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
break;
case OP_ATOMIC_STORE_R4:
- if (cfg->r4fp) {
- ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
- ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
- } else {
- code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
- ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
- ARM_CVTD (code, vfp_scratch1, ins->sreg1);
- ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
- code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
- }
+ ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
+ ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
break;
case OP_ATOMIC_STORE_R8:
ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
ARM_CPYS (code, ins->dreg, ins->sreg1);
break;
case OP_MOVE_F_TO_I4:
- if (cfg->r4fp) {
- ARM_FMRS (code, ins->dreg, ins->sreg1);
- } else {
- code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
- ARM_CVTD (code, vfp_scratch1, ins->sreg1);
- ARM_FMRS (code, ins->dreg, vfp_scratch1);
- code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
- }
+ ARM_FMRS (code, ins->dreg, ins->sreg1);
break;
case OP_MOVE_I4_TO_F:
- if (cfg->r4fp) {
- ARM_FMSR (code, ins->dreg, ins->sreg1);
- } else {
- ARM_FMSR (code, ins->dreg, ins->sreg1);
- ARM_CVTS (code, ins->dreg, ins->dreg);
- }
+ ARM_FMSR (code, ins->dreg, ins->sreg1);
break;
case OP_FCONV_TO_R4:
- if (IS_VFP) {
- if (cfg->r4fp) {
- ARM_CVTD (code, ins->dreg, ins->sreg1);
- } else {
- ARM_CVTD (code, ins->dreg, ins->sreg1);
- ARM_CVTS (code, ins->dreg, ins->dreg);
- }
- }
+ if (IS_VFP)
+ ARM_CVTD (code, ins->dreg, ins->sreg1);
break;
case OP_TAILCALL_PARAMETER:
ARM_B (code, 0);
*(guint32*)code = ((guint32*)(ins->inst_p0))[0];
code += 4;
- if (!cfg->r4fp)
- ARM_CVTS (code, ins->dreg, ins->dreg);
} else {
code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)(gsize)ins->inst_p0);
ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
- if (!cfg->r4fp)
- ARM_CVTS (code, ins->dreg, ins->dreg);
}
break;
case OP_STORER8_MEMBASE_REG:
break;
case OP_STORER4_MEMBASE_REG:
g_assert (arm_is_fpimm8 (ins->inst_offset));
- if (cfg->r4fp) {
- ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
- } else {
- code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
- ARM_CVTD (code, vfp_scratch1, ins->sreg1);
- ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
- code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
- }
+ ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
break;
case OP_LOADR4_MEMBASE:
- if (cfg->r4fp) {
- ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
- } else {
- g_assert (arm_is_fpimm8 (ins->inst_offset));
- code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
- ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
- ARM_CVTS (code, ins->dreg, vfp_scratch1);
- code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
- }
+ ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
break;
case OP_ICONV_TO_R_UN: {
g_assert_not_reached ();
break;
}
case OP_ICONV_TO_R4:
- if (cfg->r4fp) {
- ARM_FMSR (code, ins->dreg, ins->sreg1);
- ARM_FSITOS (code, ins->dreg, ins->dreg);
- } else {
- code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
- ARM_FMSR (code, vfp_scratch1, ins->sreg1);
- ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
- ARM_CVTS (code, ins->dreg, vfp_scratch1);
- code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
- }
+ ARM_FMSR (code, ins->dreg, ins->sreg1);
+ ARM_FSITOS (code, ins->dreg, ins->dreg);
break;
case OP_ICONV_TO_R8:
code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
case OP_SETFRET: {
MonoType *sig_ret = mini_get_underlying_type (mono_method_signature_internal (cfg->method)->ret);
if (sig_ret->type == MONO_TYPE_R4) {
- if (cfg->r4fp) {
- if (IS_HARD_FLOAT) {
- if (ins->sreg1 != ARM_VFP_D0)
- ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
- } else {
- ARM_FMRS (code, ARMREG_R0, ins->sreg1);
- }
+ if (IS_HARD_FLOAT) {
+ if (ins->sreg1 != ARM_VFP_D0)
+ ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
} else {
- ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
-
- if (!IS_HARD_FLOAT)
- ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
+ ARM_FMRS (code, ARMREG_R0, ins->sreg1);
}
} else {
if (IS_HARD_FLOAT)
#define MONO_ARCH_HAVE_OBJC_GET_SELECTOR 1
#define MONO_ARCH_HAVE_SDB_TRAMPOLINES 1
#define MONO_ARCH_HAVE_OP_GENERIC_CLASS_INIT 1
-#define MONO_ARCH_FLOAT32_SUPPORTED 1
#define MONO_ARCH_LLVM_TARGET_LAYOUT "e-p:32:32-n32-S64"
#define MONO_ARCH_HAVE_INTERP_ENTRY_TRAMPOLINE 1
case ArgInFRegR4:
if (COMPILE_LLVM (cfg))
MONO_INST_NEW (cfg, ins, OP_FMOVE);
- else if (cfg->r4fp)
- MONO_INST_NEW (cfg, ins, OP_RMOVE);
else
- MONO_INST_NEW (cfg, ins, OP_ARM_SETFREG_R4);
+ MONO_INST_NEW (cfg, ins, OP_RMOVE);
ins->dreg = mono_alloc_freg (cfg);
ins->sreg1 = arg->dreg;
MONO_ADD_INS (cfg->cbb, ins);
case ArgInFRegR4:
if (COMPILE_LLVM (cfg))
MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
- else if (cfg->r4fp)
- MONO_EMIT_NEW_UNALU (cfg, OP_RMOVE, cfg->ret->dreg, val->dreg);
else
- MONO_EMIT_NEW_UNALU (cfg, OP_ARM_SETFREG_R4, cfg->ret->dreg, val->dreg);
+ MONO_EMIT_NEW_UNALU (cfg, OP_RMOVE, cfg->ret->dreg, val->dreg);
break;
default:
g_assert_not_reached ();
arm_fmovd (code, call->inst.dreg, cinfo->ret.reg);
break;
case ArgInFRegR4:
- if (cfg->r4fp)
- arm_fmovs (code, call->inst.dreg, cinfo->ret.reg);
- else
- arm_fcvt_sd (code, call->inst.dreg, cinfo->ret.reg);
+ arm_fmovs (code, call->inst.dreg, cinfo->ret.reg);
break;
case ArgVtypeInIRegs: {
MonoInst *loc = cfg->arch.vret_addr_loc;
code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
arm_dmb (code, ARM_DMB_ISH);
- if (cfg->r4fp) {
- arm_ldarw (code, ARMREG_LR, ARMREG_LR);
- arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
- } else {
- arm_ldarw (code, ARMREG_LR, ARMREG_LR);
- arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
- arm_fcvt_sd (code, ins->dreg, FP_TEMP_REG);
- }
+ arm_ldarw (code, ARMREG_LR, ARMREG_LR);
+ arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
break;
}
case OP_ATOMIC_LOAD_R8: {
}
case OP_ATOMIC_STORE_R4: {
code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
- if (cfg->r4fp) {
- arm_fmov_double_to_rx (code, ARMREG_IP0, ins->sreg1);
- arm_stlrw (code, ARMREG_LR, ARMREG_IP0);
- } else {
- arm_fcvt_ds (code, FP_TEMP_REG, ins->sreg1);
- arm_fmov_double_to_rx (code, ARMREG_IP0, FP_TEMP_REG);
- arm_stlrw (code, ARMREG_LR, ARMREG_IP0);
- }
+ arm_fmov_double_to_rx (code, ARMREG_IP0, ins->sreg1);
+ arm_stlrw (code, ARMREG_LR, ARMREG_IP0);
if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
arm_dmb (code, ARM_DMB_ISH);
break;
guint64 imm = *(guint32*)ins->inst_p0;
code = emit_imm64 (code, ARMREG_LR, imm);
- if (cfg->r4fp) {
- arm_fmov_rx_to_double (code, dreg, ARMREG_LR);
- } else {
- arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
- arm_fcvt_sd (code, dreg, FP_TEMP_REG);
- }
+ arm_fmov_rx_to_double (code, dreg, ARMREG_LR);
break;
}
case OP_LOADR8_MEMBASE:
code = emit_ldrfpx (code, dreg, ins->inst_basereg, ins->inst_offset);
break;
case OP_LOADR4_MEMBASE:
- if (cfg->r4fp) {
- code = emit_ldrfpw (code, dreg, ins->inst_basereg, ins->inst_offset);
- } else {
- code = emit_ldrfpw (code, FP_TEMP_REG, ins->inst_basereg, ins->inst_offset);
- arm_fcvt_sd (code, dreg, FP_TEMP_REG);
- }
+ code = emit_ldrfpw (code, dreg, ins->inst_basereg, ins->inst_offset);
break;
case OP_STORER8_MEMBASE_REG:
code = emit_strfpx (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
break;
case OP_STORER4_MEMBASE_REG:
- if (cfg->r4fp) {
- code = emit_strfpw (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
- } else {
- arm_fcvt_ds (code, FP_TEMP_REG, sreg1);
- code = emit_strfpw (code, FP_TEMP_REG, ins->inst_destbasereg, ins->inst_offset);
- }
+ code = emit_strfpw (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
break;
case OP_FMOVE:
if (dreg != sreg1)
arm_fmovs (code, dreg, sreg1);
break;
case OP_MOVE_F_TO_I4:
- if (cfg->r4fp) {
- arm_fmov_double_to_rx (code, ins->dreg, ins->sreg1);
- } else {
- arm_fcvt_ds (code, ins->dreg, ins->sreg1);
- arm_fmov_double_to_rx (code, ins->dreg, ins->dreg);
- }
+ arm_fmov_double_to_rx (code, ins->dreg, ins->sreg1);
break;
case OP_MOVE_I4_TO_F:
- if (cfg->r4fp) {
- arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
- } else {
- arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
- arm_fcvt_sd (code, ins->dreg, ins->dreg);
- }
+ arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
break;
case OP_MOVE_F_TO_I8:
arm_fmov_double_to_rx (code, ins->dreg, ins->sreg1);
arm_fcvtzu_dx (code, dreg, sreg1);
break;
case OP_FCONV_TO_R4:
- if (cfg->r4fp) {
- arm_fcvt_ds (code, dreg, sreg1);
- } else {
- arm_fcvt_ds (code, FP_TEMP_REG, sreg1);
- arm_fcvt_sd (code, dreg, FP_TEMP_REG);
- }
+ arm_fcvt_ds (code, dreg, sreg1);
break;
case OP_ICONV_TO_R4:
- if (cfg->r4fp) {
- arm_scvtf_rw_to_s (code, dreg, sreg1);
- } else {
- arm_scvtf_rw_to_s (code, FP_TEMP_REG, sreg1);
- arm_fcvt_sd (code, dreg, FP_TEMP_REG);
- }
+ arm_scvtf_rw_to_s (code, dreg, sreg1);
break;
case OP_LCONV_TO_R4:
- if (cfg->r4fp) {
- arm_scvtf_rx_to_s (code, dreg, sreg1);
- } else {
- arm_scvtf_rx_to_s (code, FP_TEMP_REG, sreg1);
- arm_fcvt_sd (code, dreg, FP_TEMP_REG);
- }
+ arm_scvtf_rx_to_s (code, dreg, sreg1);
break;
case OP_ICONV_TO_R8:
arm_scvtf_rw_to_d (code, dreg, sreg1);
#define MONO_ARCH_HAVE_OP_GENERIC_CLASS_INIT 1
#define MONO_ARCH_HAVE_OPCODE_NEEDS_EMULATION 1
#define MONO_ARCH_HAVE_DECOMPOSE_LONG_OPTS 1
-#define MONO_ARCH_FLOAT32_SUPPORTED 1
#define MONO_ARCH_HAVE_INTERP_PINVOKE_TRAMP 1
#define MONO_ARCH_LLVM_TARGET_LAYOUT "e-i64:64-i128:128-n32:64-S128"
-#ifdef TARGET_OSX
-#define MONO_ARCH_FORCE_FLOAT32 1
-#endif
// Does the ABI have a volatile non-parameter register, so tailcall
// can pass context to generics or interfaces?
return LLVMInt32Type ();
else if (type == LLVMInt16Type ())
return LLVMInt32Type ();
- else if (!cfg->r4fp && type == LLVMFloatType ())
- return LLVMDoubleType ();
else
return type;
}
if (mono_isnan (val))
*(int *)&val = 0x7FC00000;
#endif
- if (cfg->r4fp)
- return LLVMConstReal (LLVMFloatType (), val);
- else
- return LLVMConstFPExt (LLVMConstReal (LLVMFloatType (), val), LLVMDoubleType ());
+ return LLVMConstReal (LLVMFloatType (), val);
}
static LLVMValueRef
case OP_ICONV_TO_R4:
case OP_LCONV_TO_R4:
v = LLVMBuildSIToFP (builder, lhs, LLVMFloatType (), "");
- if (cfg->r4fp)
- values [ins->dreg] = v;
- else
- values [ins->dreg] = LLVMBuildFPExt (builder, v, LLVMDoubleType (), dname);
+ values [ins->dreg] = v;
break;
case OP_FCONV_TO_R4:
v = LLVMBuildFPTrunc (builder, lhs, LLVMFloatType (), "");
- if (cfg->r4fp)
- values [ins->dreg] = v;
- else
- values [ins->dreg] = LLVMBuildFPExt (builder, v, LLVMDoubleType (), dname);
+ values [ins->dreg] = v;
break;
case OP_RCONV_TO_R8:
values [ins->dreg] = LLVMBuildFPExt (builder, lhs, LLVMDoubleType (), dname);
values [ins->dreg] = LLVMBuildSExt (builder, values [ins->dreg], LLVMInt32Type (), dname);
else if (zext)
values [ins->dreg] = LLVMBuildZExt (builder, values [ins->dreg], LLVMInt32Type (), dname);
- else if (!cfg->r4fp && ins->opcode == OP_LOADR4_MEMBASE)
- values [ins->dreg] = LLVMBuildFPExt (builder, values [ins->dreg], LLVMDoubleType (), dname);
break;
}
return 4;
else if (type->type == MONO_TYPE_I8 || type->type == MONO_TYPE_U8)
return 8;
- else if (type->type == MONO_TYPE_R4 && !m_type_is_byref (type) && (!cfg || cfg->r4fp))
+ else if (type->type == MONO_TYPE_R4 && !m_type_is_byref (type))
return 4;
else if (type->type == MONO_TYPE_R8 && !m_type_is_byref (type))
return 8;
{
MonoInst *ins;
- if (cfg->r4fp && info->conv_4_to_8 == OP_FCONV_TO_R8)
+ if (info->conv_4_to_8 == OP_FCONV_TO_R8)
MONO_INST_NEW (cfg, ins, OP_RCONV_TO_R8);
else
MONO_INST_NEW (cfg, ins, info->conv_4_to_8);
int type_index;
MonoStackType stack_type;
- if (info->op_index == 2 && cfg->r4fp && TARGET_SIZEOF_VOID_P == 4) {
+ if (info->op_index == 2 && TARGET_SIZEOF_VOID_P == 4) {
type_index = 3;
stack_type = STACK_R4;
} else {
s390_ldgr (code, ins->dreg, ins->sreg1);
break;
case OP_MOVE_F_TO_I4:
- if (!cfg->r4fp) {
- s390_ledbr (code, s390_f0, ins->sreg1);
- s390_lgdr (code, ins->dreg, s390_f0);
- } else {
- s390_lgdr (code, ins->dreg, ins->sreg1);
- }
+ s390_lgdr (code, ins->dreg, ins->sreg1);
s390_srag (code, ins->dreg, ins->dreg, 0, 32);
break;
case OP_MOVE_I4_TO_F:
s390_slag (code, s390_r0, ins->sreg1, 0, 32);
s390_ldgr (code, ins->dreg, s390_r0);
- if (!cfg->r4fp)
- s390_ldebr (code, ins->dreg, ins->dreg);
break;
case OP_FCONV_TO_R4:
s390_ledbr (code, ins->dreg, ins->sreg1);
- if (!cfg->r4fp)
- s390_ldebr (code, ins->dreg, ins->dreg);
break;
case OP_S390_SETF4RET:
- if (!cfg->r4fp)
- s390_ledbr (code, ins->dreg, ins->sreg1);
- else
- s390_ldr (code, ins->dreg, ins->sreg1);
+ s390_ldr (code, ins->dreg, ins->sreg1);
break;
case OP_TLS_GET: {
if (s390_is_imm16 (ins->inst_offset)) {
call = (MonoCallInst *) ins;
const MonoJumpInfoTarget patch = mono_call_to_patch (call);
code = emit_call (cfg, code, patch.type, patch.target);
- if (!cfg->r4fp && call->signature->ret->type == MONO_TYPE_R4)
- s390_ldebr (code, s390_f0, s390_f0);
}
break;
- case OP_RCALL: {
- call = (MonoCallInst *) ins;
- const MonoJumpInfoTarget patch = mono_call_to_patch (call);
- code = emit_call (cfg, code, patch.type, patch.target);
- if (ins->dreg != s390_f0)
- s390_ldr (code, ins->dreg, s390_f0);
- break;
- }
+ case OP_RCALL: {
+ call = (MonoCallInst *) ins;
+ const MonoJumpInfoTarget patch = mono_call_to_patch (call);
+ code = emit_call (cfg, code, patch.type, patch.target);
+ if (ins->dreg != s390_f0)
+ s390_ldr (code, ins->dreg, s390_f0);
+ break;
+ }
case OP_LCALL:
case OP_VCALL:
case OP_VCALL2:
call = (MonoCallInst*)ins;
s390_lgr (code, s390_r1, ins->sreg1);
s390_basr (code, s390_r14, s390_r1);
- if (!cfg->r4fp && call->signature->ret->type == MONO_TYPE_R4)
- s390_ldebr (code, s390_f0, s390_f0);
- break;
- case OP_RCALL_REG:
- call = (MonoCallInst*)ins;
- s390_lgr (code, s390_r1, ins->sreg1);
- s390_basr (code, s390_r14, s390_r1);
- if (ins->dreg != s390_f0)
- s390_ldr (code, ins->dreg, s390_f0);
- break;
+ break;
+ case OP_RCALL_REG:
+ call = (MonoCallInst*)ins;
+ s390_lgr (code, s390_r1, ins->sreg1);
+ s390_basr (code, s390_r14, s390_r1);
+ if (ins->dreg != s390_f0)
+ s390_ldr (code, ins->dreg, s390_f0);
+ break;
case OP_LCALL_REG:
case OP_VCALL_REG:
case OP_VCALL2_REG:
call = (MonoCallInst*)ins;
s390_lg (code, s390_r1, 0, ins->sreg1, ins->inst_offset);
s390_basr (code, s390_r14, s390_r1);
- if (!cfg->r4fp && call->signature->ret->type == MONO_TYPE_R4)
- s390_ldebr (code, s390_f0, s390_f0);
- break;
- case OP_RCALL_MEMBASE:
- call = (MonoCallInst*)ins;
- s390_lg (code, s390_r1, 0, ins->sreg1, ins->inst_offset);
- s390_basr (code, s390_r14, s390_r1);
- if (ins->dreg != s390_f0)
- s390_ldr (code, ins->dreg, s390_f0);
+ break;
+ case OP_RCALL_MEMBASE:
+ call = (MonoCallInst*)ins;
+ s390_lg (code, s390_r1, 0, ins->sreg1, ins->inst_offset);
+ s390_basr (code, s390_r14, s390_r1);
+ if (ins->dreg != s390_f0)
+ s390_ldr (code, ins->dreg, s390_f0);
break;
case OP_LCALL_MEMBASE:
case OP_VCALL_MEMBASE:
case OP_R4CONST: {
float f = *(float *) ins->inst_p0;
if (f == 0) {
- if (cfg->r4fp) {
- s390_lzer (code, ins->dreg);
- if (mono_signbit (f) != 0)
- s390_lnebr (code, ins->dreg, ins->dreg);
- } else {
- s390_lzdr (code, ins->dreg);
- if (mono_signbit (f) != 0)
- s390_lndbr (code, ins->dreg, ins->dreg);
- }
+ s390_lzer (code, ins->dreg);
+ if (mono_signbit (f) != 0)
+ s390_lnebr (code, ins->dreg, ins->dreg);
} else {
S390_SET (code, s390_r13, ins->inst_p0);
s390_le (code, ins->dreg, 0, s390_r13, 0);
- if (!cfg->r4fp)
- s390_ldebr (code, ins->dreg, ins->dreg);
- else
- s390_le (code, ins->dreg, 0, s390_r13, 0);
+ s390_le (code, ins->dreg, 0, s390_r13, 0);
}
}
break;
}
break;
case OP_STORER4_MEMBASE_REG: {
- if (cfg->r4fp) {
- S390_LONG (code, stey, ste, ins->sreg1, 0,
- ins->inst_destbasereg, ins->inst_offset);
- } else {
- s390_ledbr (code, ins->sreg1, ins->sreg1);
- S390_LONG (code, stey, ste, ins->sreg1, 0,
+ S390_LONG (code, stey, ste, ins->sreg1, 0,
ins->inst_destbasereg, ins->inst_offset);
- s390_ldebr (code, ins->sreg1, ins->sreg1);
- }
}
break;
case OP_LOADR4_MEMBASE: {
- if (cfg->r4fp) {
- S390_LONG (code, ley, le, ins->dreg, 0,
- ins->inst_basereg, ins->inst_offset);
- } else {
- S390_LONG (code, ley, le, ins->dreg, 0,
+ S390_LONG (code, ley, le, ins->dreg, 0,
ins->inst_basereg, ins->inst_offset);
- s390_ldebr (code, ins->dreg, ins->dreg);
- }
}
break;
case OP_ICONV_TO_R_UN: {
break;
case OP_ICONV_TO_R4:
s390_cefbr (code, ins->dreg, ins->sreg1);
- if (!cfg->r4fp)
- s390_ldebr (code, ins->dreg, ins->dreg);
break;
case OP_LCONV_TO_R4:
s390_cegbr (code, ins->dreg, ins->sreg1);
- if (!cfg->r4fp)
- s390_ldebr (code, ins->dreg, ins->dreg);
break;
case OP_ICONV_TO_R8:
s390_cdfbr (code, ins->dreg, ins->sreg1);
}
break;
case OP_RCEQ: {
- if (cfg->r4fp)
- s390_cebr (code, ins->sreg1, ins->sreg2);
- else
- s390_cdbr (code, ins->sreg1, ins->sreg2);
+ s390_cebr (code, ins->sreg1, ins->sreg2);
s390_lghi (code, ins->dreg, 1);
s390_je (code, 4);
s390_lghi (code, ins->dreg, 0);
}
break;
case OP_RCLT: {
- if (cfg->r4fp)
- s390_cebr (code, ins->sreg1, ins->sreg2);
- else
- s390_cdbr (code, ins->sreg1, ins->sreg2);
+ s390_cebr (code, ins->sreg1, ins->sreg2);
s390_lghi (code, ins->dreg, 1);
s390_jl (code, 4);
s390_lghi (code, ins->dreg, 0);
}
break;
case OP_RCLT_UN: {
- if (cfg->r4fp)
- s390_cebr (code, ins->sreg1, ins->sreg2);
- else
- s390_cdbr (code, ins->sreg1, ins->sreg2);
+ s390_cebr (code, ins->sreg1, ins->sreg2);
s390_lghi (code, ins->dreg, 1);
s390_jlo (code, 4);
s390_lghi (code, ins->dreg, 0);
}
break;
case OP_RCGT: {
- if (cfg->r4fp)
- s390_cebr (code, ins->sreg1, ins->sreg2);
- else
- s390_cdbr (code, ins->sreg1, ins->sreg2);
+ s390_cebr (code, ins->sreg1, ins->sreg2);
s390_lghi (code, ins->dreg, 1);
s390_jh (code, 4);
s390_lghi (code, ins->dreg, 0);
}
break;
case OP_RCGT_UN: {
- if (cfg->r4fp)
- s390_cebr (code, ins->sreg1, ins->sreg2);
- else
- s390_cdbr (code, ins->sreg1, ins->sreg2);
+ s390_cebr (code, ins->sreg1, ins->sreg2);
s390_lghi (code, ins->dreg, 1);
s390_jho (code, 4);
s390_lghi (code, ins->dreg, 0);
}
break;
case OP_RCNEQ: {
- if (cfg->r4fp)
- s390_cebr (code, ins->sreg1, ins->sreg2);
- else
- s390_cdbr (code, ins->sreg1, ins->sreg2);
+ s390_cebr (code, ins->sreg1, ins->sreg2);
s390_lghi (code, ins->dreg, 1);
s390_jne (code, 4);
s390_lghi (code, ins->dreg, 0);
}
break;
case OP_RCGE: {
- if (cfg->r4fp)
- s390_cebr (code, ins->sreg1, ins->sreg2);
- else
- s390_cdbr (code, ins->sreg1, ins->sreg2);
+ s390_cebr (code, ins->sreg1, ins->sreg2);
s390_lghi (code, ins->dreg, 1);
s390_jhe (code, 4);
s390_lghi (code, ins->dreg, 0);
}
break;
case OP_RCLE: {
- if (cfg->r4fp)
- s390_cebr (code, ins->sreg1, ins->sreg2);
- else
- s390_cdbr (code, ins->sreg1, ins->sreg2);
+ s390_cebr (code, ins->sreg1, ins->sreg2);
s390_lghi (code, ins->dreg, 1);
s390_jle (code, 4);
s390_lghi (code, ins->dreg, 0);
case OP_INSERTX_R4_SLOW:
switch (ins->inst_c0) {
case 0:
- if (cfg->r4fp)
- s390x_movss (code, ins->dreg, ins->sreg2);
- else
- s390x_cvtsd2ss (code, ins->dreg, ins->sreg2);
+ s390x_movss (code, ins->dreg, ins->sreg2);
break;
case 1:
s390x_pshufd_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
- if (cfg->r4fp)
- s390x_movss (code, ins->dreg, ins->sreg2);
- else
- s390x_cvtsd2ss (code, ins->dreg, ins->sreg2);
+ s390x_movss (code, ins->dreg, ins->sreg2);
s390x_pshufd_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
break;
case 2:
s390x_pshufd_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
- if (cfg->r4fp)
- s390x_movss (code, ins->dreg, ins->sreg2);
- else
- s390x_cvtsd2ss (code, ins->dreg, ins->sreg2);
+ s390x_movss (code, ins->dreg, ins->sreg2);
s390x_pshufd_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
break;
case 3:
s390x_pshufd_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
- if (cfg->r4fp)
- s390x_movss (code, ins->dreg, ins->sreg2);
- else
- s390x_cvtsd2ss (code, ins->dreg, ins->sreg2);
+ s390x_movss (code, ins->dreg, ins->sreg2);
s390x_pshufd_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
break;
}
s390x_pshufd_imm (code, ins->dreg, ins->dreg, 0x44);
break;
case OP_EXPAND_R4:
- if (cfg->r4fp) {
- s390x_movsd (code, ins->dreg, ins->sreg1);
- } else {
- s390x_movsd (code, ins->dreg, ins->sreg1);
- s390x_cvtsd2ss (code, ins->dreg, ins->dreg);
- }
+ s390x_movsd (code, ins->dreg, ins->sreg1);
s390x_pshufd_imm (code, ins->dreg, ins->dreg, 0);
break;
case OP_EXPAND_R8:
s390_ldr (code, inst->dreg, ainfo->reg);
}
} else if (ainfo->regtype == RegTypeFPR4) {
- if (!cfg->r4fp)
- s390_ledbr (code, inst->dreg, ainfo->reg);
} else if (ainfo->regtype == RegTypeBase) {
s390_lgr (code, s390_r13, STK_BASE);
s390_aghi (code, s390_r13, alloc_size);
// unary float (overloaded)
else if (fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R4) {
if (strcmp (cmethod->name, "Abs") == 0) {
- if (cfg->r4fp) {
- opcode = OP_ABSF;
- stack_type = STACK_R4;
- } else {
- opcode = OP_ABS;
- }
+ opcode = OP_ABSF;
+ stack_type = STACK_R4;
}
}
// binary double
if (fsig->param_count == 1) {
stack_type = STACK_R4;
if (strcmp (cmethod->name, "Abs") == 0) {
- if (cfg->r4fp) {
- opcode = OP_ABSF;
- stack_type = STACK_R4;
- } else {
- opcode = OP_ABS;
- }
+ opcode = OP_ABSF;
+ stack_type = STACK_R4;
} else if (strcmp (cmethod->name, "Ceiling") == 0) {
- if (cfg->r4fp) {
- opcode = OP_CEILF;
- stack_type = STACK_R4;
- } else {
- opcode = OP_CEIL;
- }
+ opcode = OP_CEILF;
+ stack_type = STACK_R4;
} else if (strcmp (cmethod->name, "Floor") == 0) {
- if (cfg->r4fp) {
- opcode = OP_FLOORF;
- stack_type = STACK_R4;
- } else {
- opcode = OP_FLOOR;
- }
+ opcode = OP_FLOORF;
+ stack_type = STACK_R4;
} else if (strcmp (cmethod->name, "Sqrt") == 0) {
- if (cfg->r4fp) {
- opcode = OP_SQRTF;
- stack_type = STACK_R4;
- } else {
- opcode = OP_SQRT;
- }
+ opcode = OP_SQRTF;
+ stack_type = STACK_R4;
} else if (strcmp (cmethod->name, "Truncate") == 0) {
- if (cfg->r4fp) {
- opcode = OP_TRUNCF;
- stack_type = STACK_R4;
- } else {
- opcode = OP_TRUNC;
- }
opcode = OP_TRUNCF;
+ stack_type = STACK_R4;
}
}
}
#define MONO_ARCH_HAVE_SDB_TRAMPOLINES 1
#define MONO_ARCH_HAVE_SETUP_RESUME_FROM_SIGNAL_HANDLER_CTX 1
#define MONO_ARCH_HAVE_UNWIND_BACKTRACE 1
-#define MONO_ARCH_FLOAT32_SUPPORTED 1
#define S390_STACK_ALIGNMENT 8
#define S390_FIRST_ARG_REG s390_r2
if (!m_type_is_byref (ret)) {
if (ret->type == MONO_TYPE_R4) {
- MONO_EMIT_NEW_UNALU (cfg, cfg->r4fp ? OP_RMOVE : OP_FMOVE, cfg->ret->dreg, val->dreg);
+ MONO_EMIT_NEW_UNALU (cfg, OP_RMOVE, cfg->ret->dreg, val->dreg);
return;
} else if (ret->type == MONO_TYPE_R8) {
MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
#define MONO_ARCH_EMULATE_FCONV_TO_U4 1
#define MONO_ARCH_NO_EMULATE_LONG_SHIFT_OPS 1
#define MONO_ARCH_NO_EMULATE_LONG_MUL_OPTS 1
-#define MONO_ARCH_FLOAT32_SUPPORTED 1
//mini-codegen stubs - this doesn't do anything
#define MONO_ARCH_CALLEE_REGS (1 << 0)
#ifdef MONO_ARCH_HAVE_OPTIMIZED_DIV
backend->optimized_div = 1;
#endif
-#ifdef MONO_ARCH_FORCE_FLOAT32
- backend->force_float32 = 1;
-#endif
}
static gboolean
try_llvm = mono_use_llvm || llvm;
#endif
-#ifndef MONO_ARCH_FLOAT32_SUPPORTED
- opts &= ~MONO_OPT_FLOAT32;
-#endif
- if (current_backend->force_float32)
- /* Force float32 mode on newer platforms */
- opts |= MONO_OPT_FLOAT32;
-
restart_compile:
if (method_is_gshared) {
method_to_compile = method;
cfg->explicit_null_checks = FALSE;
}
- /*
- if (!mono_debug_count ())
- cfg->opt &= ~MONO_OPT_FLOAT32;
- */
if (!is_simd_supported (cfg))
cfg->opt &= ~MONO_OPT_SIMD;
- cfg->r4fp = (cfg->opt & MONO_OPT_FLOAT32) ? 1 : 0;
- cfg->r4_stack_type = cfg->r4fp ? STACK_R4 : STACK_R8;
+ cfg->r4_stack_type = STACK_R4;
if (cfg->gen_seq_points)
cfg->seq_points = g_ptr_array_new ();
guint disable_div_with_mul : 1;
guint explicit_null_checks : 1;
guint optimized_div : 1;
- guint force_float32 : 1;
int monitor_enter_adjustment;
int dyn_call_param_area;
} MonoBackend;
guint no_inline : 1;
guint gshared : 1;
guint gsharedvt : 1;
- guint r4fp : 1;
guint llvm_only : 1;
guint interp : 1;
guint use_current_cpu : 1;