net: phy: dp83867: Add rx-fifo-depth and tx-fifo-depth

This code changes the TI specific ti,fifo-depth to the common
tx-fifo-depth property.  The tx depth is applicable for both RGMII and
SGMII modes of operation.

rx-fifo-depth was added as well but this is only applicable for SGMII
mode.

So in summary
if RGMII mode write tx fifo depth only
if SGMII mode write both rx and tx fifo depths

If the property is not populated in the device tree then set the value
to the default values.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reported-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 9cd9dce..adda0d0 100644 (file)
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -93,9 +93,11 @@
 #define DP83867_STRAP_STS2_CLK_SKEW_NONE       BIT(2)
 
 /* PHY CTRL bits */
-#define DP83867_PHYCR_FIFO_DEPTH_SHIFT         14
+#define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT      14
+#define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT      12
 #define DP83867_PHYCR_FIFO_DEPTH_MAX           0x03
-#define DP83867_PHYCR_FIFO_DEPTH_MASK          GENMASK(15, 14)
+#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK       GENMASK(15, 14)
+#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK       GENMASK(13, 12)
 #define DP83867_PHYCR_RESERVED_MASK            BIT(11)
 
 /* RGMIIDCTL bits */
@@ -131,7 +133,8 @@ enum {
 struct dp83867_private {
        u32 rx_id_delay;
        u32 tx_id_delay;
-       u32 fifo_depth;
+       u32 tx_fifo_depth;
+       u32 rx_fifo_depth;
        int io_impedance;
        int port_mirroring;
        bool rxctrl_strap_quirk;
@@ -408,18 +411,32 @@ static int dp83867_of_init(struct phy_device *phydev)
                dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
 
        ret = of_property_read_u32(of_node, "ti,fifo-depth",
-                                  &dp83867->fifo_depth);
+                                  &dp83867->tx_fifo_depth);
        if (ret) {
-               phydev_err(phydev,
-                          "ti,fifo-depth property is required\n");
-               return ret;
+               ret = of_property_read_u32(of_node, "tx-fifo-depth",
+                                          &dp83867->tx_fifo_depth);
+               if (ret)
+                       dp83867->tx_fifo_depth =
+                                       DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
        }
-       if (dp83867->fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
-               phydev_err(phydev,
-                          "ti,fifo-depth value %u out of range\n",
-                          dp83867->fifo_depth);
+
+       if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
+               phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
+                          dp83867->tx_fifo_depth);
+               return -EINVAL;
+       }
+
+       ret = of_property_read_u32(of_node, "rx-fifo-depth",
+                                  &dp83867->rx_fifo_depth);
+       if (ret)
+               dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
+
+       if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
+               phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
+                          dp83867->rx_fifo_depth);
                return -EINVAL;
        }
+
        return 0;
 }
 #else
@@ -458,12 +475,31 @@ static int dp83867_config_init(struct phy_device *phydev)
                phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
                                   BIT(7));
 
+       if (phy_interface_is_rgmii(phydev) ||
+           phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+               val = phy_read(phydev, MII_DP83867_PHYCTRL);
+               if (val < 0)
+                       return val;
+
+               val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
+               val |= (dp83867->tx_fifo_depth <<
+                       DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
+
+               if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+                       val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
+                       val |= (dp83867->rx_fifo_depth <<
+                               DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
+               }
+
+               ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
+               if (ret)
+                       return ret;
+       }
+
        if (phy_interface_is_rgmii(phydev)) {
                val = phy_read(phydev, MII_DP83867_PHYCTRL);
                if (val < 0)
                        return val;
-               val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
-               val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 
                /* The code below checks if "port mirroring" N/A MODE4 has been
                 * enabled during power on bootstrap.